Imaging device and imaging system

1. Field of the Invention

The present invention relates to an imaging device and an imaging system.

2. Description of the Related Art

As an example of a structure for speeding up an imaging device, there is known a structure including a first accumulation unit configured to hold signals output from pixels, a buffer unit configured to transmit the signals held by the first accumulation unit, and a second accumulation unit, to which the signals are transmitted from the buffer unit, as described in Japanese Patent Application Laid-Open No. 2009-089367. In the imaging device of Japanese Patent Application Laid-Open No. 2009-089367, the first accumulation unit first holds a signal of a first pixel. The buffer unit then transmits the signal of the first pixel held in the first accumulation unit to the second accumulation unit. Thereafter, the first accumulation unit holds a signal of a second pixel during a period, in which the signal of the first pixel is read out from the second accumulation unit. Thus, a period, in which the signal of the first pixel is read out from the second accumulation unit, and a period, in which the signal is output from the second pixel to the first accumulation unit, can be superposed. Therefore, speed-up of the imaging device can be realized in comparison to an imaging device having a structure without a second accumulation unit.

Japanese Patent Application Laid-Open No. 2004-134867 describes an imaging device, in which an amplifying element is shared by a plurality of photoelectric conversion unit and configured to output signals based on electric charges accumulated in the photoelectric conversion units to a vertical signal line. The amplifying element then outputs a first signal based on electric charges generated by a first photoelectric conversion unit and a second signal based on electric charges obtained by adding electric charges generated by the first photoelectric conversion unit and electric charges generated by another photoelectric conversion unit.

However, further speed-up of the operation is not considered in Japanese Patent Application Laid-Open No. 2009-089367 or Japanese Patent Application Laid-Open No. 2004-134867.

An aspect of the invention is an imaging device comprising: a pixel cell including a first photoelectric conversion unit, a second photoelectric conversion unit, and an output unit; and a read-out circuit including a buffer unit configured to buffer a signal output from the output unit, a capacitor element configured to hold a signal output from the buffer unit, and a switching unit configured to switch a state, between the buffer unit and the capacitor element, between a conductive state and a non-conductive state, wherein the output unit outputs the first signal based on electric charges accumulated in the first photoelectric conversion unit, and the buffer unit outputs a first buffer signal obtained by buffering the first signal, the output unit outputs a second signal based on electric charges obtained by adding electric charges accumulated in the first photoelectric conversion unit and electric charges accumulated in the second photoelectric conversion unit, and the buffer unit outputs a second buffer signal obtained by buffering the second signal, and a period, in which the switching unit keeps a path between the buffer unit and the capacitor element in the conductive state to cause the capacitor element to hold the first buffer signal, is shorter than a period, in which the switching unit keeps the electrical path between the buffer unit and the capacitor element in the conductive state to cause the capacitor element to hold the second buffer signal.

Further features of the present invention will become apparent from the following description of exemplary embodiments (with reference to the attached drawings).

FIG. 1 illustrates an example of a structure of an imaging device.

FIG. 2 illustrates an example of operation of the imaging device.

FIG. 3 illustrates an example of a structure of an imaging device.

FIG. 4 illustrates an example of operation of the imaging device.

FIG. 5 illustrates an example of operation of the imaging device.

FIG. 6 illustrates an example of a structure of an imaging device.

FIG. 7 illustrates an example of operation of the imaging device.

FIG. 8 illustrates an example of a structure of an imaging system.

Imaging devices of respective exemplary embodiments will be described below with reference to the accompanying drawings.

(First Exemplary Embodiment)

FIG. 1 illustrates a structure of an imaging device of the present exemplary embodiment.

The imaging device includes a pixel array 1 including pixel cells 3 , and a peripheral circuit unit 5 including buffer circuits AP as buffer units. The pixel array 1 includes the plurality of pixel cells 3 . Each of the pixel cells 3 includes a photodiode D 1 , a photodiode D 2 , a transistor M 1 , a transistor M 2 , a transistor M 21 , a transistor M 31 , and a transistor M 41 . The photodiode D 1 is a first photoelectric conversion unit included in each of the pixel cells 3 . The photodiode D 2 is a second photoelectric conversion unit included in each of the pixel cells 3 . A node NF is electrically connected to an input node of the transistor M 31 , one of main nodes of the transistor M 21 , one of main nodes of the transistor M 1 , and one of main nodes of the transistor M 2 . One of the pixel cells 3 includes two pixels: a pixel including the photodiode D 1 and a pixel including the photodiode D 2 . The transistor M 31 is an output unit configured to output a signal based on electric charges accumulated in each of the photodiode D 1 and the photodiode D 2 or a signal based on electric charges obtained by adding electric charges accumulated respectively in the photodiode D 1 and the photodiode D 2 .

The imaging device includes the pixel cells 3 arranged in a two-dimensional array having thousands of rows and thousands of columns. FIG. 1 illustrates pixel cells 3 arranged in an array of one row and two columns as a part of the pixel cells 3 of two-dimensional array. Note that, unless otherwise specifically noted, an indication of X-th row indicates pixel cells 3 in the X-th row from the left of the drawing. An indication of Y-th column similarly indicates pixel cells 3 in the Y-th column from the top of the drawing.

The imaging device further includes the peripheral circuit unit 5 outside the pixel array 1 . The peripheral circuit unit 5 includes read-out circuits 9 . The transistor M 41 in each of the pixel cells 3 is electrically connected to a capacitor element Ci through a vertical signal line 6 . A current source Ib supplies current to the transistor M 31 through the vertical signal line 6 and the transistor M 41 . Thus, the current source Ib, the transistor M 31 , and a voltage source configured to supply voltage to the transistor M 31 constitute a source follower circuit.

Each of the read-out circuits 9 includes an amplifier GA, a buffer circuit AN, the buffer circuit AP, the capacitor element Ci, a capacitor element Cf, a capacitor element CN 1 , a capacitor element CP 1 , a capacitor element CN 2 , and a capacitor element CP 2 . Each of the read-out circuits 9 further includes a switch SG, a switch SN 1 , a switch SP 1 , a switch SBN, a switch SBP, a switch SSN, a switch SSP, a switch SN 2 , a switch SP 2 , a switch SN 31 , and a switch SP 31 . The amplifier GA is an amplification unit configured to output an amplified signal obtained by amplifying a signal output from the output unit of the pixel cells 3 . The buffer circuit AP is a buffer unit configured to buffer an amplified signal output from the amplification unit. The buffer circuit AN is a second buffer unit configured to buffer an amplified signal output from the amplification unit. The switch SP 2 is a switching unit configured to switch the state of an electrical path between the buffer circuit AP as a buffer unit and the capacitor element CP 2 between the conductive state and the non-conductive state. The buffer unit is a circuit configured to convert impedance of the electrical path between the amplification unit and the buffer unit, and impedance of the electrical path between the buffer unit and the following switching unit. The amplification factor of the buffer unit is set to 1. The switch SP 1 is a second switching unit configured to switch the state of an electrical path between the amplifier GA as an amplification unit and the capacitor element CP 1 between the conductive state and the non-conductive state. The switch SN 1 is a third switching unit configured to switch the state of an electrical path between the amplifier GA as an amplification unit and the capacitor element CN 1 between the conductive state and the non-conductive state. The switch SN 2 is a fourth switching unit configured to switch the state of an electrical path between the buffer circuit AN as a second buffer unit and the capacitor element CN 2 between the conductive state and the non-conductive state. The capacitor element CP 1 is a second capacitor element to which the amplifier GA outputs an amplified signal when the switch SP 1 is in the conductive state. The capacitor element CN 1 is a third capacitor element to which the amplifier GA outputs an amplified signal when the switch SN 1 is in the conductive state. The capacitor element CN 2 is a fourth capacitor element to which the buffer circuit AN outputs a buffer signal when the switch SN 2 is in the conductive state.

The capacitor element CP 2 and the capacitor element CN 2 of the read-out circuits 9 respectively output signals held respectively by the capacitor element CP 2 and the capacitor element CN 2 to an output amplifier MA respectively through an output line 7 and an output line 8 .

FIG. 2 is a timing diagram illustrating operation of the imaging device illustrated in FIG. 1 .

The signals φSEL 1 , φRES 1 , φTX 1 , and φTX 2 in FIG. 2 respectively correspond to signals indicated by the reference signs that are identical to those assigned in FIG. 1 . The signals φSEL 2 and φRES 2 are signals for controlling pixel cells 3 in a row adjacent to the pixel cells 3 to which the signal φSEL 1 is input.

The signals φSEL 1 , φRES 1 , φSEL 2 , φRES 2 , φTX 1 , and φTX 2 are signals output from a vertical scan circuit, which is not illustrated. In FIG. 2 , the signals for controlling the respective switches included in the read-out circuits 9 in FIG. 1 are indicated by φ followed with the respective reference signs of the switches assigned in FIG. 1 . The signal φSG is a signal for controlling the switch SG by a timing generator, which is not illustrated in FIG. 1 . When the signal φSG is the High level (hereinafter, referred to as H level), the switch SG is in the conductive state. When the signal φSG is Low level (hereinafter, referred to as L level), the switch SG is in the non-conductive state. When other signals: signal φSN 1 , signal φSP 1 , signal φSBP, signal φSSP, signal φSN 2 , signal φSP 2 , signal φSN 31 , signal φSP 31 , signal φSN 32 , and signal φSP 32 are the H level, the corresponding switches are in the conductive state, and when the signals are the L level, the corresponding switches are in the non-conductive state. Note that the signal φSN 2 and the signal φSP 2 are in phase with each other. The signal φSN 31 and the signal φSP 31 are also in phase with each other. The signal φSN 32 and the signal φSP 32 are also in phase with each other.

At time t 1 , the vertical scan circuit sets the signal φRES 1 to the L level. Thus, the transistors M 21 are turned off and the reset of the nodes NF is released. The release of the reset of the nodes NF causes the transistors M 31 to output signals to the vertical signal lines 6 through the transistors M 41 . The signals are referred to as noise signals. The timing generator also sets the signal φSN 1 and the signal φSP 1 to the L level. Thus, the electrical path between the amplifiers GA and the capacitor elements CN 1 , and the electrical path between the amplifiers GA and the capacitor elements CP 1 respectively become non-conductive. Note that, the vertical scan circuit sets the signal φSEL 1 and the signal φRES 2 to the H level at time t 1 . The vertical scan circuit also sets the signal φSEL 2 , the signal φTX 1 , and the signal φTX 2 to the L level at time t 1 . The timing generator also sets the signal φSG, the signal φSSN, and the signal φSSP to the H level at time t 1 . The timing generator also sets the signal φSBN, the signal φSBP, the signal φSN 2 , the signal φSP 2 , the signal φSN 31 , the signal φSP 31 , the signal φSN 32 , and the signal φSP 32 to the L level at time t 1 .

The timing generator sets the signal φSG to the L level at time t 2 . Thus, the switches SG become non-conductive. Each of the amplifiers GA outputs a signal obtained by multiplying an input signal by the amplification factor Ci/Cf where Cf is the capacitance value of the capacitor element Cf and Ci is the capacitance value of the capacitor element Ci. Specifically, the amplifier GA outputs a signal obtained by amplifying a noise signal output to the vertical signal line 6 from the pixel cell 3 (hereinafter, referred to as an amplified noise signal).

At time t 3 , the timing generator sets the signal φSN 1 to the H level. Thus, the switches SN 1 become conductive. At the same time, the amplifier GA outputs the amplified noise signal. When the switches SN 1 become conductive, a period, in which the amplifiers GA output the amplified noise signals to the capacitor elements CN 1 , starts.

At time t 4 , the timing generator sets to the signal φSN 1 to L level. Thus, the switches SN 1 become non-conductive. Therefore, the capacitor elements CN 1 hold the amplified noise signals at this time.

At time t 5 , the vertical scan circuit sets the signal φTX to the H level. Thus, the transistors M 1 start to transfer the electric charges accumulated in the photodiodes D 1 to the nodes NF. The timing generator also sets the signal φSP 1 to the H level. Thus, a period, in which the amplifiers GA output signals to the capacitor elements CP 1 , starts.

At time t 6 , the vertical scan circuit sets the signal φTX to the L level. Thus, the transistors M 1 finish transferring the accumulated electric charges in the photodiodes D 1 to the nodes NF. The signals output at this time from the transistors M 31 to the vertical signal lines 6 through the transistors M 41 are referred to as signals A. The signals A are first optical signals based on the electric charges accumulated in the first photoelectric conversion units. Each of the amplifiers GA amplifies the signal A and outputs a signal obtained by the amplification. The obtained signal is referred to as an amplified signal A. The amplified signal A is a first amplified signal obtained by amplifying the first optical signal and output by the amplifier GA.

At time t 7 , the timing generator sets the signal φSP 1 to the L level. Thus, the capacitor elements CP 1 hold the amplified signals A at this time.

At time t 8 , the timing generator sets the signal φSBN to the H level and sets the signal φSSN to the L level. Thus, the switches SBN become conductive and the switches SSN become non-conductive. Therefore, the buffer circuits AN output the amplified noise signals held by the capacitor elements CN 1 to the switches SN 2 . The timing generator also sets the signal φSBP to the H level and sets the signal φSSP to the L level at the same time. Thus, the switches SBP become conductive and the switches SSP become non-conductive. Therefore, the buffer circuits AP output the amplified signals A held by the capacitor elements CP 1 to the switches SP 2 . The signal output from each of the buffer circuits AP is a first buffer signal obtained by buffering the amplified signal A, which is the first amplified signal.

At time t 9 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the H level. Thus, a period, in which the buffer circuits AN output the amplified noise signals to the capacitor elements CN 2 , starts. In addition, a period, in which the buffer circuits AP output the amplified signals A to the capacitor elements CP 2 , starts.

At time t 10 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the L level. Thus, the capacitor elements CN 2 hold the amplified noise signals, and the capacitor elements CP 2 hold the amplified signals A, which are the first buffer signals.

Then, a horizontal scanning circuit, which is not illustrated, sets the signal φSN 31 and the signal φSP 31 to the H level. Thus, the capacitor element CN 2 included in the read-out circuit 9 related to the pixel cell 3 in the first column in FIG. 1 outputs the amplified noise signal based on the noise signal to the output amplifier MA. In addition, the capacitor element CP 2 included in the read-out circuit 9 related to the pixel cell 3 in the first column outputs the amplified signal A based on the electric charges accumulated in the photodiode D 1 to the output amplifier MA. The output amplifier MA outputs a difference signal between the amplified signal A and the amplified noise signal to a terminal OUTN and a terminal OUTS. The horizontal scanning circuit then sets the signal φSN 32 and the signal φSP 32 to the H level. Thus, the read-out circuit 9 in each column outputs the amplified signal A and the amplified noise signal to the output amplifier MA. A period, in which the read-out circuit 9 in each column outputs the amplified signal A and the amplified noise signal to the output amplifier MA, is referred to as a horizontal scanning period A. In FIG. 2 , the horizontal scanning period A is from time t 11 to time t 15 .

On the other hand, the vertical scan circuit sets the signal φTX 2 to the H level at time t 10 . The transistors M 2 of the pixel cells 3 in a first row start to transfer the electric charges accumulated in the photodiodes D 2 to the nodes NF. The nodes NF hold the electric charges accumulated in the photodiodes D 1 through the operation described above. The vertical scan circuit sets the signal φTX 2 to the L level at time t 11 , whereby the nodes NF of the pixel cells 3 in the first row hold electric charges obtained by adding the electric charges accumulated in the photodiodes D 1 and the electric charges accumulated in the photodiodes D 2 . The signal output from each of the transistors M 31 to the vertical signal line 6 through each of the transistors M 41 is referred to as a signal A+B. Meanwhile, the difference signal between the signal A+B and the signal A is a signal B. The signal B is assumed to be obtained when the transistor M 31 outputs to the vertical signal line 6 through the transistor M 41 based only on the electric charges accumulated in the corresponding photodiode D 2 . The corresponding amplifier GA amplifies the signal A+B and outputs a signal obtained by the amplification. The obtained signal is referred to as an amplified signal A+B. The amplified signal A+B is a second amplified signal obtained by amplifying the signal A+B.

The timing generator also sets the signal φSBP to the L level and the signal SSP to the H level at time t 11 . Thus, the capacitor elements CP 1 are ready again to hold signals output from the amplifiers GA.

The timing generator sets the signal φSP 1 to the H level at time t 12 , and the timing generator then sets the signal φSP 1 to the L level at time t 13 . This operation causes the capacitor elements CP 1 to hold the amplified signals A+B.

The timing generator sets the signal φSBP to the H level and the signal φSSP to the L level at time t 14 . Thus, the buffer circuits AP output the amplified signals A+B to the switches SP 2 . The signals output from the buffer circuits AP are second buffer signals obtained by buffering the amplified signals A+B, which are the second amplified signals. Meanwhile, the signal output from each of the buffer circuits AN is a third buffer signal obtained by buffering the amplified noise signal.

The timing generator sets the signal φSN 2 and the signal φSP 2 to the H level at time t 16 after the horizontal scanning period A. Thus, the capacitor elements CN 2 hold the amplified noise signals having been held by the capacitor elements CN 1 . The capacitor elements CP 2 also hold the amplified signals A+B.

The horizontal scanning circuit then sets the signal φSN 31 and the signal φSP 31 to the H level. Thus, the corresponding capacitor element CN 1 outputs the amplified noise signal to the output amplifier MA. The corresponding capacitor element CP 1 outputs the amplified signal A+B to the output amplifier MA. The output amplifier MA outputs the difference signal between the amplified signal A+B and the amplified noise signal to the terminal OUTS and the terminal OUTN. A period, in which the read-out circuit 9 in each column outputs the amplified signal A+B and the amplified noise signal to the output amplifier MA, is referred to as a horizontal scanning period A+B. In FIG. 2 , the A+B horizontal scanning period is from time t 18 to time t 19 .

From time t 18 , the vertical scan circuit and the timing generator perform operation for obtaining the amplified noise signals, the amplified signals A, and the amplified signals A+B based on the pixel cells 3 in the second row similarly to the period from time t 0 to time t 18 .

In the present exemplary embodiment, a period, in which the signal φSP 2 is kept at the H level for the amplified signals A+B, is a period from time t 16 to time t 17 . Meanwhile, a period, in which the signal φSP 2 is kept at the H level for the amplified signals A, is a period from time t 9 to time t 10 , which is less than the period from time t 16 to time t 17 . This is because an amplitude range available for the amplified signals A is less than that for the amplified signals A+B. A settling period from the time when each of the buffer circuits AP starts to output a signal to the capacitor elements CP 2 to the time when the signal is converged is shorter for the amplified signal A than the amplified signal A+B. Therefore, the output of the buffer circuit AP is settled until the corresponding switch SP 2 is switched to the non-conductive state even when the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A, is set shorter than the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A+B. Thus, the signal accuracy of the amplified signals A held by the capacitor elements CP 2 is hardly deteriorated. In addition, since the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A, is set shorter than the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signal A+B, the horizontal scanning period A can be started earlier. Thus, speed-up of the imaging device can be realized while suppressing deterioration of the accuracy of signals output from the imaging device.

In the imaging device of the present exemplary embodiment, the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A, is set to a half or less of the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A+B. This is because the signal amplitude available for the amplified signals A is about a half of the amplitude of the amplified signals A+B. Meanwhile, an example in which two photodiodes are included in each of the pixel cells 3 has been described as the present exemplary embodiment. In an alternate exemplary embodiment, more photodiodes may be included in each of the pixel cells 3 . The number of photodiodes included in each of the pixel cells 3 is assumed to be L. Each of the pixel cells 3 outputs a signal based on electric charges obtained by adding electric charges accumulated in respective M photodiodes out of L photodiodes (hereinafter, referred to as a signal M) as a signal corresponding to the signal A described above, where M is less than L. The pixel cell 3 outputs a signal based on electric charges obtained by adding electric charges accumulated in respective L photodiodes (hereinafter, referred to as a signal L) as a signal corresponding to the signal A+B. In such a case, in the imaging device of the present exemplary embodiment, the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the signals based on the signals M, is set to M/L or less of the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the signals based on the signals L.

In the imaging device of the present exemplary embodiment, the period, in which the switches SP 1 are kept in the conductive state to cause the capacitor elements CP 1 to hold the amplified signals A, may be set shorter than the period, in which the switches SP 1 are kept in the conductive state to cause the capacitor elements CP 1 to hold the amplified signals A+B. Thus, the imaging device of the present exemplary embodiment can achieve further speed-up of the imaging device.

The imaging device of the present exemplary embodiment may be provided with a microlens common to the photodiode D 1 and the photodiode D 2 . In this case, the imaging device of the present exemplary embodiment can output a focus detecting signal for detecting focus through phase difference detection and an image signal for generating an image. Specifically, in the present exemplary embodiment, the signal for detecting focus is the amplified signal A and the image signal is the amplified signal A+B. An output signal processing unit provided outside the imaging device generates a signal corresponding to the amplified signal B, which is a difference signal between the amplified signal A and the amplified signal A+B input from the imaging device. The output signal processing unit then detects phase difference using the signal corresponding to the amplified signal B and the amplified signal A. The output signal processing unit can detect whether the imaging device is focused based on the detected phase difference. The output signal processing unit also generates an image using the amplified signal A+B.

Since the signal accuracy required for the focus detecting signal is a signal accuracy enough to allow for focus detection, the focus detecting signal can allow more deterioration of signal accuracy compared to the image signal. Thus, even if the signal accuracy of the amplified signal A is deteriorated by setting the period, in which the switch SP 2 is kept in the conductive state to cause the capacitor element CP 2 to hold the amplified signal A, short as the present exemplary embodiment, the accuracy of focus detection is hardly affected. Therefore, speed-up of the imaging device can be realized while suppressing deterioration of the accuracy of focus detection.

Meanwhile, the imaging device of the present exemplary embodiment includes the amplifiers GA configured to amplify signals output from the pixel cells 3 . The imaging device of the present exemplary embodiment does not necessarily include the amplifiers GA as long as each of the read-out circuits 9 includes the buffer circuit AP configured to buffer the signal output from the pixel cell 3 , the switch SP 2 , and the capacitor element CP 2 .

(Second Exemplary Embodiment)

An imaging device of the present exemplary embodiment will be described especially focusing on a difference from the first exemplary embodiment with reference to the drawings.

FIG. 3 illustrates the structure of the imaging device of the present exemplary embodiment. In FIG. 3 , elements having functions similar to those illustrated in FIG. 1 are indicated by reference signs identical to those provided in FIG. 1 . Each of the pixel cells 3 includes four photodiodes: a photodiode Da 1 , a photodiode Db 1 , a photodiode Da 2 , and a photodiode Db 2 . The photodiode Da 1 is electrically connected to the node NF through a transistor Ma 1 . Similarly, the photodiode Db 1 , the photodiode Da 2 , and the photodiode Db 2 are electrically connected to the node NF respectively through a transistor Mb 1 , a transistor Ma 2 , and a transistor Mb 2 .

In the imaging device of the present exemplary embodiment, amplified noise signals output to the output line 7 from the capacitor elements CN 2 of the respective columns are input to a first output amplifier BR. The first output amplifier BR outputs the input amplified noise signals to the terminal OUTN. Meanwhile, signals output to the output line 8 from the capacitor elements CP 2 of the respective columns are input to a second output amplifier BV. The second output amplifier BV outputs the input signals to the terminal OUTS.

FIG. 4 is a timing diagram illustrating operation of the imaging device illustrated in FIG. 3 . In FIG. 4 , signals for driving elements that are identical to those in FIG. 2 are indicated by the reference signs that are identical to those assigned in FIG. 2 .

A signal φTXa 1 , a signal φTXb 1 , a signal φTXa 2 , and a signal φTXb 2 illustrated in FIG. 4 respectively correspond to signals indicated by the reference signs in FIG. 3 .

At time t 5 , the vertical scan circuit sets the signal φTXa 1 to the H level. Thus, the transistors Ma 1 start to transfer the electric charges accumulated in the photodiodes Da 1 to the nodes NF. At the same time, the timing generator sets the signal φSP 1 to the H level. Thus, the capacitor elements CP 1 start to hold the signals output from the amplifiers GA.

At time t 6 , the vertical scan circuit sets the signal φTXa 1 to the L level. Thus, the transistors Ma 1 finish transferring the accumulated electric charges in the photodiodes Da 1 to the nodes NF. The signals output at this time from the transistors M 31 to the vertical signal lines 6 are the signals A. The amplifiers GA output the amplified signals A obtained by amplifying the signals A to the capacitor elements CP 1 .

At time t 7 , the timing generator sets the signal φSP 1 to the L level. Thus, the capacitor elements CP 1 hold the amplified signals A.

At time t 9 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the H level. Thus, a period, in which the buffer circuits AN output the amplified noise signals to the capacitor elements CN 2 , starts. In addition, a period, in which the buffer circuits AP output the amplified signals A to the capacitor elements CP 2 , starts.

At time t 10 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the L level. Thus, the capacitor elements CN 2 hold the amplified noise signals. The capacitor elements CP 2 hold the amplified signals A.

At time t 10 , the vertical scan circuit sets the signal φTXa 1 and the signal φTXb 1 to the H level. Thus, the transistors Mb 1 start to transfer the electric charges accumulated in the photodiodes Db 1 to the nodes NF. The transistors Ma 1 start to transfer the electric charges accumulated in the photodiodes Da 1 from time t 6 to the nodes NF.

At time t 11 , the vertical scan circuit sets the signal φTXa 1 and the signal φTXb 1 to the L level. Thus, the nodes NF hold electric charges obtained by adding the electric charges accumulated in the photodiodes Da 1 and the electric charges accumulated in the photodiodes Db 1 . Signals output from the transistors M 31 to the vertical signal lines 6 through the transistors M 41 are the signals A+B. The amplifiers GA outputs the amplified signals A+B obtained by amplifying the signal A+B to the switches SP 1 .

At time t 12 , the timing generator sets the signal φSP 1 to the H level. Thus, a period, in which the amplifiers GA output the amplified signals A+B to the capacitor elements CP 1 , starts.

At time t 13 , the timing generator sets the signal φSP 1 to the L level. Thus, the capacitor elements CP 1 hold the amplified signals A+B.

At time t 15 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the H level. Thus, a period, in which, the buffer circuits AN output the amplified noise signals to the capacitor elements CN 2 , starts. In addition, a period, in which the buffer circuits AP output the amplified signals A+B to the capacitor elements CP 2 , starts.

At time t 16 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the L level. Thus, the capacitor elements CN 2 hold the amplified noise signals. The capacitor elements CP 2 hold the amplified signals A+B.

From time t 18 , the vertical scan circuit and the timing generator perform operation for outputting the amplified signals A based on the electric charges accumulated in the photodiodes Da 2 outside the imaging device. The vertical scan circuit and the timing generator also perform operation for outputting the amplified signals A+B based on the electric charges obtained by adding the electric charges accumulated in the photodiodes Da 2 and the electric charges accumulated in the photodiodes Db 2 outside the imaging device. The vertical scan circuit and the timing generator also perform operation for outputting the amplified noise signals based on the noise signals of the pixel cells 3 to the outside of the imaging device.

In the imaging device of the present exemplary embodiment, similarly to the first exemplary embodiment, a period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A, is set shorter than the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A+B. Thus, speed-up of the imaging device can be realized while suppressing deterioration of the accuracy of signals output from the imaging device.

The imaging device of the present exemplary embodiment may be provided with a microlens common to the photodiode Da 1 and the photodiode Db 1 . The imaging device of the present exemplary embodiment may be provided with a microlens common to the photodiode Da 2 and the photodiode Db 2 . Thus, focus detection through phase difference detecting and image generation are possible using the amplified signal A based on the electric charges accumulated in the photodiode Da 1 and the amplified signal A+B based on the sum of the electric charges accumulated in the photodiode Da 1 and the electric charges accumulated in the photodiode Db 1 .

The imaging device of the present exemplary embodiment may be provided with a microlens common to the photodiode Da 1 , the photodiode Db 1 , the photodiode Da 2 , and the photodiode Db 2 . In this case, the imaging device outputs a first amplified signal A+B based on the electric charges obtained by adding the electric charges accumulated respectively in the photodiode Da 1 and the photodiode Db 1 to the output signal processing unit outside the imaging device. The imaging device then outputs a second amplified signal A+B based on the electric charges obtained by adding the electric charges accumulated respectively in the photodiode Da 2 and the photodiode Db 2 to the output signal processing unit. The output signal processing unit generates an image based on a signal obtained by adding the first amplified signal A+B and the second amplified signal A+B. Meanwhile, focus detection through phase difference detection can be performed using any of the combinations (1) to (6) described below, for example. Note that the amplified signal B described below is a signal obtained by the output signal processing unit by subtracting the amplified signal A from the amplified signal A+B.

(1) The amplified signal A based on the electric charges in the photodiode Da 1 and the amplified signal B based on the electric charges in the photodiode Db 1

(2) The amplified signal A based on the electric charges in the photodiode Da 1 and the amplified signal B based on the electric charges in the photodiode Db 2

(3) The amplified signal A based on the electric charges in the photodiode Da 1 and the amplified signal A based on the electric charges in the photodiode Da 2

(4) The amplified signal A based on the electric charges in the photodiode Da 2 and the amplified signal B based on the electric charges in the photodiode Db 1

(5) A signal obtained by adding the amplified signal A based on the electric charges in the photodiode Da 1 and the amplified signal A based on the electric charges in the photodiode Da 2 , and a signal obtained by adding the amplified signal B based on the electric charges in the photodiode Db 1 and the amplified signal B based on the electric charges in the photodiode Db 2

(6) A signal obtained by adding the amplified signal A based on the electric charges in the photodiode Da 1 and the amplified signal B based on the electric charges in the photodiode Db 1 , and a signal obtained by adding the amplified signal A based on the electric charges in the photodiode Da 2 and the amplified signal B based on the electric charges in the photodiode Db 2

(7) The amplified signal B based on the electric charges in the photodiode Db 1 and the amplified signal B based on the electric charges in the photodiode Db 2

(8) The amplified signal A based on the electric charges in the photodiode Da 2 and the amplified signal B based on the electric charges in the photodiode Db 2

(9) The first amplified signal A+B and the second amplified signal A+B

In addition, in the imaging device of the present exemplary embodiment, the period, in which the switches SP 1 are kept in the conductive state to cause the capacitor elements CP 1 to hold the amplified signals A, may be set shorter than the period, in which the switches SP 1 are kept in the conductive state to cause the capacitor elements CP 1 to hold the amplified signal A+B. Thus, the imaging device of the present exemplary embodiment can achieve further speed-up of the imaging device while suppressing deterioration of the accuracy of signals output from the imaging device.

Depending on imaging scenes, focus may be detected using a focus detecting signals of pixels of a part of columns in the pixel array 1 . In this case, the read-out circuits 9 in the part of columns of the pixel array 1 output the amplified signals A. In addition, the read-out circuits 9 including the read-out circuits 9 of the part of columns output the amplified signals A+B. In this case, the horizontal scanning period A may be set shorter than the horizontal scanning period A+B. Thus, the imaging device of the present exemplary embodiment can achieve further speed-up of the imaging device.

(Third Exemplary Embodiment)

An imaging device of the present exemplary embodiment will be described especially focusing on the differences from the second exemplary embodiment. The structure of the imaging device of the present exemplary embodiment is identical to that of the second exemplary embodiment illustrated in FIG. 3 . The imaging device of the present exemplary embodiment is different from the second exemplary embodiment in that the period, in which the switches SP 1 are kept in the conductive state to cause the capacitor elements CP 1 to hold the amplified signals A+B, is set equal to or shorter than the period, in which the switches SP 1 are kept in the conductive state to cause the capacitor elements CP 1 to hold the amplified signals A.

FIG. 5 is a timing diagram illustrating operation of the imaging device of the present exemplary embodiment.

The timing generator keeps the signal φSP 1 at the H level from time t 5 to time t 7 . The timing generator sets the signal φSP 1 to the L level at time t 7 , which causes the capacitor elements CP 1 to hold the amplified signals A.

Thereafter, the timing generator keeps the signal φSBP at the H level during a period from time t 8 to time t 11 and keeps the signal φSBP at the L level during a period from time t 11 to time t 14 . The timing generator also keeps the signal φSSP at the L level during the period from time t 8 to time t 11 and at the H level during the period from time t 11 to time t 14 .

The timing generator keeps the signal φSP 1 at the H level during a period from time t 12 to time t 13 , which is within the period, in which the signal φSBP is kept at the L level and the signal φSSP is kept at the H level. The period from time t 12 to time t 13 is shorter than the period from time t 5 to time t 7 .

The amplitude range of the amplified signals A+B is larger than the amplitude range of the amplified signals A. However, the capacitor elements CP 1 already hold the amplified signals A at time t 7 . In the imaging device of the present exemplary embodiment, the capacitor elements CP 1 hold the amplified signals A+B without resetting the amplified signals A having been held in the capacitor elements CP 1 . Thus, a period, in which the switches SP 1 are kept in the conductive state to cause the capacitor elements CP 1 to hold the amplified signals A+B, can be set to a period enough for the capacitor elements CP 1 to hold difference signals between the amplified signals A+B and the amplified signals A. Therefore, the period from time t 12 to time t 13 can be set equal to or shorter than the period from time t 5 to time t 7 .

Thus, in the imaging device of the present exemplary embodiment, a period necessary for the capacitor elements CP 1 to hold the amplified signals A+B can be shorter than the imaging device of the second exemplary embodiment. Thus, the imaging device can achieve further speed-up.

(Fourth Exemplary Embodiment)

An imaging device of the present exemplary embodiment will be described especially focusing on a difference from the first exemplary embodiment. In the imaging device of the present exemplary embodiment, the structure and operation of the read-out circuits 9 differs from those of the first exemplary embodiment.

FIG. 6 illustrates the structure of the imaging device of the present exemplary embodiment. In FIG. 6 , elements having functions similar to those illustrated in FIG. 1 are indicated by reference signs identical to those provided in FIG. 1 . In the imaging device of the present exemplary embodiment, the peripheral circuit unit 5 is on both sides interposing the pixel array 1 .

Each of the read-out circuits 9 of the present exemplary embodiment includes a buffer circuit APa in addition to the buffer circuit AP and the buffer circuit AN. The read-out circuit 9 of the present exemplary embodiment includes a capacitor element CPg 1 instead of the capacitor element CP 1 . The read-out circuit 9 of the present exemplary embodiment also includes a capacitor element CNg 1 instead of the capacitor element CN 1 . The read-out circuit 9 of the present exemplary embodiment further includes a capacitor element CPag 1 and a switch SPa 2 .

FIG. 7 is a timing diagram illustrating operation of the imaging device illustrated in FIG. 6 . A signal φSPa 1 illustrated in FIG. 7 is for controlling switches SPa 1 , and a signal φSPa 2 is for controlling switches SPa 2 .

At time t 5 , the timing generator sets the signal φSPa 1 to the H level. Thus, a period, in which the amplifiers GA output the amplified signals A to the capacitor elements CPag 1 , starts. The timing generator then sets the signal φSPa 1 to the L level at time t 6 . Thus, the capacitor elements CPag 1 hold the amplified signals A.

The timing generator sets the signal φSN 2 and the signal φSPa 2 to the H level at time t 9 . Thus, a period, in which the buffer circuits AN outputs the amplified noise signals to the capacitor elements CN 2 , starts. In addition, a period, in which the buffer circuits AP output the amplified signals A to the capacitor elements CP 2 , starts.

At time t 10 , the timing generator sets the signal φSN 2 and the signal φSPa 2 to the L level. Thus, the capacitor elements CN 2 hold the amplified noise signals. The capacitor elements CP 2 hold the amplified signals A.

At time t 12 , the timing generator sets the signal φSP 1 to the H level. Thus, a period, in which the amplifiers GA output the amplified signals A+B to the capacitor elements CPg 1 , starts.

At time t 13 , the timing generator sets the signal φSP 1 to the L level. Thus, the capacitor elements CPg 1 hold the amplified signals A+B.

At time t 15 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the H level. Thus, a period, in which the buffer circuits AN output the amplified noise signals to the capacitor elements CN 2 , starts. In addition, a period, in which, the buffer circuits AP output the amplified signals A+B to the capacitor elements CP 2 , starts.

At time t 16 , the timing generator sets the signal φSN 2 and the signal φSP 2 to the L level. Thus, the capacitor elements CN 2 hold the amplified noise signals. The capacitor elements CP 2 hold the amplified signals A+B.

A period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A, is from time t 9 to time t 10 . A period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A+B, is from time t 15 to time t 16 . In the imaging device of the present exemplary embodiment, a period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A, is set shorter than the period, in which the switches SP 2 are kept in the conductive state to cause the capacitor elements CP 2 to hold the amplified signals A+B. Thus, the imaging device of the present exemplary embodiment can provide an effect similar to that of the first exemplary embodiment.

(Fifth Exemplary Embodiment)

An exemplary embodiment of an imaging system to which any of the imaging devices described in the first to fourth exemplary embodiments is applied will be described. Examples of an imaging system include a digital still camera, a digital camcorder, and a monitoring camera. FIG. 8 is a schematic diagram of a digital still camera to which an imaging device is applied is described as an example of an imaging system.

The imaging system illustrated in FIG. 8 includes a barrier 151 for protecting a lens, a lens 152 for focusing an optical image of an object on the imaging device 154 , and a diaphragm 153 for changing an amount of light passing through the lens 152 . The lens 152 and the diaphragm 153 constitute an optical system configured to condense light to the imaging device 154 . The imaging system illustrated in FIG. 8 also includes an output signal processing unit 155 configured to process output signals output from the imaging device 154 .

The output signal processing unit 155 converts the signals output from the imaging device 154 into digital signals, i.e. performs AD conversion. The imaging device 154 of any of the first exemplary embodiment, the third exemplary embodiment, and the fourth exemplary embodiment outputs a difference signal between the amplified signal A and the amplified noise signal (hereinafter, referred to as an amplified signal A−N) and a difference signal between the amplified signal A+B and the amplified noise signal (hereinafter, referred to as an amplified signal A+B−N). In this case, the output signal processing unit 155 converts the amplified signal A−N and the amplified signal A+B−N respectively to digital signals. Hereinafter, the amplified signal A−N after digitalization is referred to as a digital signal A, and the amplified signal A+B−N after digitalization is referred to as a digital signal A+B.

The imaging device 154 of the second exemplary embodiment outputs the amplified signal A, the amplified signal A+B, and the amplified noise signal. The output signal processing unit 155 converts the amplified signal A, the amplified signal A+B, and the amplified noise signal respectively to digital signals. The output signal processing unit 155 then obtains a difference signal between the digitalized amplified signal A and the digitalized amplified noise signal. The difference signal corresponds to the digital signal A described above. The output signal processing unit 155 generates a difference signal between the digitalized amplified signal A+B and the digitalized amplified noise signal. The difference signal corresponds to the digital signal A+B described above. The digital signal A is obtained by reducing noise component included in the amplified signal A. The digital signal A+B is obtained by reducing noise component included in the amplified signal A+B.

In addition, the output signal processing unit 155 outputs the signal after performing various corrections and compressions as necessary.

The imaging system illustrated in FIG. 8 also includes a buffer memory unit 156 configured to store image data temporarily, and an external interface unit 157 configured to communicate with an external computer or the like. The imaging system also includes a recording medium 159 , which is detachably mounted, such as a semiconductor memory to/from which imaging data is stored/read, and a recording medium control interface unit 158 configured to store/read imaging data to/from the recording medium 159 . A solid-state image sensing system further includes an overall control/calculation unit 1510 configured to perform various calculation and control overall digital still camera, and a timing generation unit 1511 configured to output various timing signals to the imaging device 154 and the output signal processing unit 155 . Note that, timing signals and the like may be input from the outside, and the imaging system is to include at least the imaging device 154 and the output signal processing unit 155 configured to process output signals output from the imaging device 154 .

The output signal processing unit 155 generates a signal obtained by subtracting the digital signal A from the digital signal A+B. The signal to be generated corresponds to a digitalized signal of a signal obtained by subtracting the amplified signal A from the amplified signal A+B. The signal to be generated is hereinafter referred to as a digital signal B. The subtraction of the digital the signal A from the digital signal A+B is performed between signals based on photodiodes provided with a common microlens. The output signal processing unit 155 performs focus detection of a phase difference detection using the digital signal A and the digital signal B. The output signal processing unit 155 generates an image using the digital signal A+B.

As described above, the imaging system of the present exemplary embodiment can perform focus detecting operation and imaging operation by applying the imaging device 154 .

The output signal processing unit 155 of the present exemplary embodiment generates a digital signal based on the signal B through digital subtraction for subtracting the digital signal A from the digital signal A+B. In another example, the output signal processing unit 155 generates the amplified signal B by subtracting the amplified signal A from the amplified signal A+B. The output signal processing unit 155 then converts the amplified signal B to a digital signal so as to obtain the digital signal B.

The above-described exemplary embodiments merely provides examples for embodying the present invention and the technical scope of the present invention should not be restrictively interpreted based on the exemplary embodiments. Specifically, the present invention can be embodied in various forms without departing from the technical idea or the main feature of the present invention. In addition, the exemplary embodiments described above can be embodied in various combinations.

The present invention can realize speed-up of signal output of an imaging device.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application No. 2014-016023, filed Jan. 30, 2014, which is hereby incorporated by reference herein in its entirety.