Input signal amplifier

This application claims priority to Japanese Patent Application No. 2014-019205, filed on Feb. 4, 2014, the contents of which are hereby incorporated by reference.

1. Technical Field

The present disclosure relates to an input signal amplifier.

2. Description of the Related Art

In. an input amplifier disclosed in Japanese Patent No. 4625732, as illustrated in FIG. 1A , a bias voltage generating circuit for quick start-up and a pre-charge switch SW 6 are added to an input IN 1 of an inverting amplifier A 1 to enable an input voltage of the inverting amplifier A 1 to quickly start up. In the input amplifier in FIG. 1A , on/off states of switches SW 4 to SW 6 are controlled in accordance with the state of the circuit as indicated in an on/off control logic table in FIG. 1B .

In the input amplifying circuit disclosed in Japanese Patent No. 4625732, the input voltage of the inverting amplifier can quickly start up when the state of the circuit is switched from an off state to an on state. However, in the input amplifying circuit disclosed in Japanese Patent No. 4625732, power consumption and circuit scale may increase in the bias voltage generating circuit for quick start-up.

Thus, a non-limiting and exemplary embodiment of the present disclosure provides an. input signal amplifier capable of quick start-up of the input voltage without causing increase in circuit scale and power consumption.

Additional benefits and advantages of the disclosed embodiments will be apparent from the specification and Figures. The benefits and/or advantages may be individually provided by the various embodiments and features of the specification and drawings disclosure, and need not all be provided in order to obtain one or more of the same.

In one general aspect, the techniques disclosed here feature: an input, signal amplifier including an inverting amplifier that outputs an input signal, a logic of which is inverted; a first switch that switches an input terminal of the inverting amplifier to be grounded or not; and a feedback resistor connected in parallel with the inverting amplifier and including a plurality of resistors with different values of resistance. The feedback resistor includes both a second switch that shorts or opens the feedback resistor via at least one of the resistors and a third switch that shorts or opens the feedback resistor via another of the resistors.

These general and specific aspects may be implemented using a device, a system, a method, and a computer program, and any combination of devices, systems, methods, and computer programs.

According to the one general aspect, the input voltage can quickly start up without causing increase in circuit scale and power consumption.

FIGS. 1A and 1B illustrate a configuration of an input amplifier disclosed in Japanese Patent No. 4625732;

FIG. 2 illustrates a configuration. of an input signal amplifier according to Embodiment 1 of the present disclosure;

FIG. 3 illustrates an internal configuration of an inverting amplifier illustrated in FIG. 2 ;

FIG. 4 illustrates an internal configuration of the inverting amplifier illustrated in FIG. 2 ;

FIG. 5 illustrates an on/off control logic table;

FIG. 6 illustrates another on/off control logic table;

FIGS. 7A and 7B illustrate changes in current consumption in intermittent reception by a wireless communication device equipped with the input signal amplifier illustrated in FIG. 2 ; and

FIG. 8 illustrates a configuration of a crystal oscillator according to Embodiment 2 of the present disclosure.

Embodiments of the present disclosure will be described below in detail with reference to the drawings. In the embodiments, the same reference characters are assigned to the components having the same function and duplicated descriptions will be omitted.

(Embodiment 1)

FIG. 2 illustrates a configuration of an input signal amplifier 10 according no Embodiment 1 of the present disclosure. The configuration of the input signal amplifier 10 will be described below using FIG. 2 .

Any amplifier may be used for an inverting amplifier 11 as long as an input and an output are logically inverted. Examples of such an amplifier include ones of an inverter type illustrated in FIG. 3 and of an N-channel constant current injection type illustrated in FIG. 4 . A switch (SW) for a constant current source or intermittent operation may be added to a portion between a VDD terminal of the inverting amplifier 11 and a power supply in which VDD is supplied and a portion between a VSS terminal of the inverting amplifier 11 and GND.

A feedback resistor 12 is connected between an output terminal OUT 1 and an input terminal IN 1 of the inverting amplifier 11 . The feedback resistor 12 has a plurality of resistance values including a value of high resistance obtained by connecting in series a resistor R 1 (corresponding to a first resistor) and a switch SW 2 and a resistor P 2 (corresponding to a second resistor) and a value of low resistance obtained by connecting a switch SW 3 .

A switch SW 1 is added in order to reduce standby power in an off state of a circuit of the inverting amplifier 11 . In the off state, the input terminal IN 1 of the inverting amplifier 11 is pulled down to the GND or pulled up to the VDD ( FIG. 2 illustrates a configuration of the input terminal IN 1 pulled down to the VSS).

Typically, a MOS transistor-type or a transfer gate-type switch is used for the switches SW 1 to SW 3 . The switch SW 2 is connected between the resistor R 1 and the resistor R 2 . During AC operation of the input signal amplifier 10 , an internal on-resistance of the switch SW 2 less changes when both terminals of the switch SW 2 undergo a small potential change and therefore degradation in phase noise of an AC signal can be alleviated. Accordingly, the resistance values of the resistors R 1 and R 2 are made equal, for example.

An input signal source 13 , which is a reference signal source represented by a temperature compensated crystal oscillator (TCXO), is connected. to the input terminal IN 1 of the inverting amplifier 11 through. an AC coupling capacitor C 3 .

The on/off control of the switches SW 1 to SW 3 is implemented by a signal generated in an on/off control signal unit 14 . The on/off control signal unit 14 is constituted by inverters INV 1 and INV 2 , a delay circuit D 1 , AND 1 , and NAND 1 .

Any configuration may be adopted for the delay circuit D 1 as long as the delay time period corresponds to a period for quick start-up of the input signal amplifier 10 and a certain delay time is provided. Typically, the delay circuit D 1 includes an RC delay circuit composed of a resistor and a capacitor, a delay circuit composed of a multiple-stage inverter, or a combination thereof.

The on/off control signal unit 14 is a circuit that is on when the control signal input is “H” and is off when the control signal input is “L”. The switches SW 1 to SW 3 are on when respective control signal nodes a, b, and c are “H” and off when the nodes a, b, and c are “L”.

An operation of the input signal amplifier 10 illustrated in FIG. 2 will be described using an on/off control, logic table in FIG. 5 .

When the input signal amplifier 10 is in the off state, an on signal for the switch SW 1 is output from “a” in the on/off control signal unit 14 and off signals for the switch SW 2 and the switch SW 3 are respectively output from “b” and “c” in the on/off control signal unit 14 . As a result, the states of the switches SW 2 and SW 3 turn into off and the feedback resistor 12 is opened, thereby causing an inverter operation of the inverting amplifier 11 . In this state, the switch SW 1 is in the on state and pulled down to the GND. Accordingly, no current consumption occurs unless leak current is generated during the off state of a transistor constituting the circuit.

When the circuit state of the input, signal amplifier 10 switches from off to quick start-up, an off signal for the switch SW 1 is output from “a” in the on/off control signal unit 14 and on signals for the switch SW 2 and the switch SW 3 are respectively output from “b” and “c”. As a result, the states of the switches SW 2 and SW 3 turn into on, the resistance value of the feedback resistor 12 comes into low, the switch SW 1 is opened, and then the inverting amplifier 11 receives feedback through the resistors with a low value of resistance in the feedback resistor 12 . As a consequence, the voltage of the input terminal IN 1 quickly starts up. In this case, quick start-up of the input voltage can be achieved without consuming additional current, because no bias voltage generating circuit or the like for quick start-up is used. This period for quick start-up is determined by the delay time of the delay circuit D 1 .

When the input signal amplifier 10 is in the on state, an off signal for the switch SW 1 is output from “a” in the on/off control signal unit 14 , an on signal for the switch SW 2 is output from “b”, and an off signal for the switch SW 3 is output. from “c”. As a result, the state of the switch SW 3 turns into off from quick start-up, the resistance value of the feedback resistor 12 comes into high, and consequently, the input signal amplifier 10 operates with high gain. The input signal amplifier 10 repeats the off-circuit state, quick start-up, and the on-circuit state, thereby achieving the input signal amplifier capable of quick start-up and suitable for intermittent operation with low power consumption.

Changes in current consumption in intermittent reception by a wireless communication device equipped with the input signal amplifier 10 illustrated in FIG. 2 will be described using FIGS. 7A and 7B . FIG. 7A illustrates changes in current consumption when the related-art input amplifier illustrated in FIG. 1 is used, while FIG. 7B illustrates changes in current consumption when the input signal amplifier 10 illustrated in FIG. 2 is used. As can be seen from FIGS. 7A and 7B , in FIG. 7B , the current of the bias voltage generating circuit for quick start-up is able to be reduced as compared to the case of FIG. 7A .

As described above, the input signal amplifier according to Embodiment 1 includes the switch SW 1 that switches the input signal of the inverting amplifier between being grounded and not grounded and the feedback resistor connected in parallel with the inverting amplifier and including a plurality of resistors with different values of resistance. The feedback resistor includes both the switch SW 2 that shorts or opens the feedback resistor via one of the resistors and the switch SW 3 that shorts or ovens the feedback resistor via another of the resistors. The on/off control signal unit appropriately switches the on/off states of the switches SW 1 to SW 3 in accordance with the state of the circuit. Consequently, the resistance values of the feedback resistor are low at the time of quick start-up while the switch SW 1 is opened to quickly start up the input voltage of the inverting amplifier without causing increase in circuit scale and power consumption.

The feedback resistor 12 of the present embodiment may include, a plurality of resistors with different values of resistance in parallel. The on/off control signal unit 14 may be a circuit other than the circuit illustrated in FIG. 2 as long as the circuit is a logic circuit that, satisfies the states corresponding to the on/off control logic table illustrated in FIG. 5 or FIG. 6 .

A difference of the on/off control logic tables in FIG. 5 and FIG. 6 is that the switch SW 2 is in the off state at the time of quick start-up in FIG. 6 . At the time of quick start-up, the switch SW 3 turns into the on state and the value of resistance between the input terminal IN 1 and the output terminal OUT 1 of the inverting amplifier 11 is sufficiently low, so that the state of the switch SW 2 may be off.

(Embodiment 2)

FIG. 8 illustrates a configuration of a crystal oscillator 20 according to Embodiment 2 of the present disclosure. The configuration of the crystal oscillator 20 will be described below using FIG. 8 .

Typically, a MOS transistor-type or a transfer gate-type switch is used for the switches SW 1 to SW 3 . The switch SW 2 is connected between the resistor R 1 and the resistor R 2 . During oscillation of the crystal oscillator 20 , an internal on-resistance of the switch SW 2 less changes when both terminals of the switch SW 2 undergo a small potential change and therefore degradation in phase noise of an oscillation signal can be alleviated. Accordingly, the resistance values of the resistors R 1 and R 2 are desirably equal to each other.

A. crystal oscillator element X 1 is connected. between the input terminal IN 1 and the output terminal OUT 1 of the inverting amplifier 11 . Load capacitors C 1 corresponding to an oscillating frequency of the crystal oscillator 20 are connected between the input terminal IN 1 and the GND and between the output terminal OUT 1 and the GND. The components within the dashed line in FIG. 3 constitute an integrated circuit, in general. The crystal oscillator element X 1 is externally connected between. the input terminal IN 1 and the output terminal OUT 1 in the integrated circuit.

An operation of the crystal oscillator 20 illustrated in FIG. 8 will be described using the on/off control logic table of FIG. 5 .

When the crystal oscillator 20 is in the off state, an on signal for the switch SW 1 is output from “a” in the on/off control signal unit 14 and off signals for the switch SW 2 and the switch SW 3 are respectively output from “b” and “c” in the on/off control signal unit 14 . As a result, the states of the switches SW 2 and SW 3 turn into off and the feedback resistor 12 is opened, thereby causing an inverter operation of the inverting amplifier 11 . In this state, the switch SW 1 is in the on state and pulled down to the GND. Accordingly, no current consumption occurs unless leak current is generated during the off state of a transistor constituting the circuit.

When the circuit state of the crystal oscillator 20 switches from off to quick start-up, an off signal for the switch SW 1 is output from “a” in the on/off control signal unit 14 and on signals for the switch SW 2 and the switch SW 3 are respectively output from “b” and “c”. As a result, the states of the switches SW 2 and SW 3 turn into on, the resistance value of the feedback resistor 12 comes into low, the switch SW 1 is opened, and then the inverting amplifier 11 receives feedback through the resistors with a low value of resistance in the feedback resistor 12 . As a consequence, the voltage of the input terminal IN 1 quickly starts up. In this case, the input voltage of the inverting amplifier 11 can quickly start up without consuming additional current, because no bias voltage generating circuit or the like for quick start-up is used. This period for quick start-up is determined by the delay time of the delay circuit D 1 .

When the crystal oscillator 20 is in the on state, an off signal for the switch SW 1 is output from “a” in the on/off control signal unit 14 , an on signal for the switch SW 2 is output from “b”, and an off signal for the switch SW 3 is output from “c”. As a result, the state of the switch SW 3 turns into off from quick start-up, the resistance value of the feedback resistor 12 comes into high, and consequently, the crystal oscillator 20 operates with high gain. The crystal oscillator 20 repeats the off-circuit state, quick start-up, and the on-circuit state, thereby achieving the crystal oscillator capable of quick start-up and suitable for intermittent operation with low power consumption.

As described above, the crystal oscillator according to Embodiment 2 includes the switch SW 1 that switches the input signal of the inverting amplifier between being grounded and not grounded and the feedback resistor connected in parallel, with the inverting amplifier and including a plurality of resistors with different values of resistance. The feedback resistor includes both the switch SW 2 that shorts or opens the feedback resistor via one of the resistors and the switch SW 3 that shorts or opens the feedback resistor vi a another of the resistors. The on/off control signal unit appropriately switches the on/off states of the switches SW 1 to SW 3 in accordance with the state of the circuit. Consequently, the resistance values of the feedback resistor is low at the time of quick start-up while the switch SW 1 is opened to quickly start up the input voltage of the inverting amplifier without causing increase in circuit scale and power consumption.

The feedback resistor 12 of the present embodiment may include a plurality of resistors with different values of resistance in parallel. The on/off control signal unit 14 may be a circuit other than the circuit illustrated in FIG. 8 as long as the circuit is a logic circuit satisfying the states corresponding to the on/off control logic table in FIG. 5 or FIG. 6 .

The input signal amplifier according to the present disclosure can be applied to a crystal oscillator, a semiconductor integrated circuit, a wireless communication device, an electronic apparatus, and the like.