Level shifter

The present disclosure relates generally to circuits, and more particularly, level shifters.

An electronic system often includes circuitry having different supply voltages. The electronic system typically has a core supply voltage for powering the circuitry, where the core supply voltage is kept low to conserve power. The circuitry, however, may require supply voltages higher than the core supply voltage. For example, one circuit component may need to drive another circuit component with a voltage level higher than the core supply voltage. In such applications, a level shifter can be implemented as an interface between the circuit components operating in different voltage domains, where the level shifter can shift a signal from one voltage level to another voltage level. For example, the level shifter can take an input signal from one circuit component having a first voltage domain that ranges from 0 V to the core supply voltage and generate an output signal for another circuit component that has a second voltage domain ranging from 0 V to a voltage higher than the core supply voltage. Although existing level shifters have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimension of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic block diagram of an exemplary pipeline analog-to-digital converter according to various aspects of the present disclosure.

FIG. 2 is a schematic circuit diagram of an exemplary level shifter according to various aspects of the present disclosure.

FIG. 3 is an exemplary timing diagram for the level shifter of FIG. 2 according to various aspects of the present disclosure.

FIG. 4 is a schematic circuit diagram of another exemplary level shifter according to various aspects of the present disclosure.

FIG. 5 is an exemplary timing diagram for the level shifter of FIG. 4 according to various aspects of the present disclosure.

FIG. 6 is a schematic circuit diagram of yet another exemplary level shifter according to various aspects of the present disclosure.

FIG. 7 is an exemplary timing diagram for the level shifter of FIG. 6 according to various aspects of the present disclosure.

Various level shifters are described herein implement data signal controlled steering of a level shifted clock signal for level shifting signals. An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal. The clock level shifter can include a charge capacitor configured to provide the level shifted clock signal from the input clock signal, and a capacitor configured to provide a complementary level shifted clock signal from a complementary input clock signal. In various implementations, a single charge capacitor is used to charge a differential capacitive load. In various implementations, the clock level shifter and the switched capacitor logic controller are configured to generate the level shifted version of the data signal operating solely on a core supply voltage.

In some embodiments, the switched capacitor logic controller includes a negated AND (NAND) gate configured to generate a NAND logic gate signal based on the data signal and the input clock signal; a switch circuit coupled to the NAND gate and the clock level shifter, wherein the switch circuit steers the level shifted clock signal based on the NAND logic gate signal; and a capacitor coupled to the clock level shifter and the switch circuit, wherein the capacitor is configured to provide another level shifted input clock signal. The switch circuit can include a first switch having a gate coupled to a control voltage, a source coupled to the NAND gate, and a drain coupled to a first node charged by the another level shifted input clock signal; a second switch having a gate coupled to the first node, a source coupled to a second node charged by the level shifted clock signal from the clock level shifter, and a drain coupled with an output node; and a third switch having a gate coupled to the complementary level shifted clock signal, a source coupled to the first node, and drain coupled to the control voltage. The first switch, the second switch, and the third switch are configured such that the second switch pulls the level shifted clock signal from the second node to the output node when the first switch pulls a voltage level down at the first node. In various embodiments, the second switch is a p-type metal-oxide-semiconductor transistor and the first switch and the third switch are n-type metal-oxide-semiconductor transistors.

In some embodiments, the switched capacitor logic controller includes a NOR gate that generates a NOR logic gate signal based on the data signal and the complementary input clock signal; a switch circuit coupled to the NOR gate and the clock level shifter, wherein the switch circuit steers the level shifted clock signal based on the NOR logic gate signal; and a capacitor coupled to the NOR gate and the switch circuit, wherein the capacitor is configured to generate a level-shifted NOR logic gate signal. The switch circuit can include a first switch having a gate coupled to a first node charged by the level-shifted NOR logic gate signal, a source coupled with a second node charged by the level shifted clock signal from the clock level shifter, and a drain coupled with an output node; and a second switch having a gate coupled with the complementary level shifted clock signal, a source coupled with the first node, and a drain coupled with a control voltage. The first switch is configured to pull the level shifted clock signal to the output node when the NOR gate pulls a voltage level down at the first node. In various embodiments, the first switch is a p-type metal-oxide-semiconductor transistor and the second switch is an n-type metal-oxide-semiconductor transistor.

An exemplary method for shifting a data signal from a first voltage domain to a second voltage domain can include generating a level shifted clock signal from an input clock signal; and steering the level shifted clock signal based on the data signal and the input clock signal to provide a level shifted version of the data signal.

In some embodiments, steering the level shifted clock signal includes generating a logic gate signal based on the data signal and the input clock signal, where the logic gate signal drives a switch circuit for steering the level shifted clock signal. The logic gate signal has a low state and a high state, and the steering can further include outputting the level shifted version of the data signal when the logic gate signal is in the low state. In various embodiments, where the switch circuit includes a switch, the method further includes applying the level shifted clock signal to a first node coupled with a gate of the switch and a second node coupled with a source of the switch, and pulling a voltage level down at the first node when the logic gate signal is in a low state and the input clock signal is in a high state, such that the switch conducts the level shifted clock signal at the second node to a load.

In some embodiments, steering the level shifted clock signal includes generating a logic gate signal based on the data signal and a complementary input clock signal, wherein the logic gate signal drives a switch circuit for steering the level shifted clock signal. The logic gate signal has a low state and a high state, and the steering can further include outputting the level shifted version of the data signal when the logic gate signal is in the low state. In various embodiments, where the switch circuit includes a switch, the method further includes applying a level shifted logic gate signal to a first node coupled with a gate of a switch of the switch circuit; applying the level shifted clock signal to a second node coupled with a source of the switch; and pulling a voltage level down at the first node when the logic gate signal is in a low state and the input clock signal is in a high state, such that the switch conducts the level shifted clock signal at the second node to a load.

FIG. 1 is a schematic block diagram of an exemplary pipeline analog-to-digital converter (ADC) 10 according to various aspects of the present disclosure. Pipeline ADC 10 is an electronic device (including an electronic circuit and/or one or more electronic components) configured to receive and convert an analog input signal V IN into a corresponding digital output signal D OUT . Digital output signal D OUT represents an n-bit digital code, where n is any number depending on design requirements of pipeline ADC 10 . FIG. 1 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in pipeline ADC 10 , and some of the features described can be replaced or eliminated in other embodiments of pipeline ADC 10 .

Pipeline ADC 10 includes cascaded stages that process analog input signal V IN into digital output signal D OUT . In the depicted embodiment, pipeline ADC 10 includes stage 20 (Stage 1 ), stage 22 (Stage 2 ), and stage 24 (Stage N, where N is a total number of stages). In operation, each stage processes (for example, quantizes) an analog input signal to generate a digital output signal and an analog residue signal for a next stage of pipeline ADC 10 for further processing. In the depicted embodiment, Stage 1 processes analog input signal V IN to generate a digital signal D 1 and an analog residue signal V RES1 ; Stage 2 processes analog residue signal V RES1 to generate a digital signal D 2 and an analog residue signal V RES2 ; and Stage N processes analog residue signal V RES N-1 to generate a digital signal D N . Digital signals D 1 , D 2 , . . . , and DN each represent n-bit digital code, where n is any number depending on design requirements of pipeline ADC 10 . The n-bit digital code can be a same number or different number of bits for each digital signal D 1 , D 2 , . . . , and DN. Pipeline ADC 10 further includes an alignment/correction module 26 that receives digital signals D 1 , D 2 , . . . , and DN and assembles these digital signals into digital output signal D OUT . In various implementations, the various digital signals D 1 , D 2 , . . . , and DN are received sequentially through a series of clock cycles (not shown). Alignment/correction module 26 can insert appropriate delays, insert bit shifts, correct conversion errors, perform other alignment/correction, or a combination thereof to digital signals D 1 , D 2 , . . . , and DN to generate digital output signal D OUT .

An exemplary configuration for stages of pipeline ADC 10 is depicted for Stage 1 , which includes a sampler 32 , an ADC 34 (in the depicted embodiment, a flash ADC), and a multiplying digital-to-analog converter (MDAC) 36 . Sampler 32 can provide samples of an analog input signal (such as analog input signal V IN ) at a rate given by a system clock signal (CDs). In various implementations, sampler 32 can be a sample-and-hold amplifier (SHA). Flash ADC 34 converts a respective analog input signal (such as analog input signal V IN ) to a corresponding digital signal (such as digital signal D 1 ). As noted, digital signal D 1 can represent n-bit digital code. For example, digital signal D 1 includes bits b 0 , b 1 , . . . through bn- 1 , where n is a total number of bits. In various implementations, flash ADC 34 includes an array of comparators, each comparing analog input signal V IN to a unique reference voltage. Flash ADC 34 can further include a voltage ladder (constructed from resistors and/or capacitors, for example) for providing the unique reference voltages to the comparator array. MDAC 36 converts the corresponding digital signal, such as digital signal D 1 , into a residual analog signal, such as residue analog signal V RES1 . MDAC 36 can include a DAC, a difference operation module, and a gain module (such as an amplifier). For example, in the depicted embodiment, a DAC can convert corresponding digital signal D 1 to a corresponding analog signal that is received by the difference operation module, which generates a difference signal by subtracting corresponding analog signal from analog input signal V IN . An amplifier can process (for example, amplify and/or level shift) difference signal to generate residue analog signal V RES1 , which can be processed by a succeeding stage of pipeline ADC 10 , such as Stage 2 .

Oftentimes, higher than normal operating signal levels are needed to drive MDAC 36 . For example, one or more switches controlling MDAC 36 , such as amplifier gain levels and/or offset levels of MDAC 36 , may require voltage control signals higher than a core supply voltage of pipeline ADC 10 (in other words, outside a normal operating voltage range, such as 0 V to core supply voltage (V DD ) of pipeline ADC 10 ), such that signal levels from flash ADC 34 need shifting to a higher, appropriate voltage range that can drive switches of MDAC 36 . To supply the appropriate signal levels, a level shifter (also referred to as a booster or boost circuit) can be implemented at an interface of flash ADC 34 and MDAC 36 to shift signals from one voltage level to another voltage level. In various implementations, a level shifter can multiply a capacitive load on the comparator array of flash ADC 34 to increase signal levels from the flash ADC 34 . For example, in the depicted embodiment, Stage 1 includes a level shifter 40 configured between flash ADC 34 and MDAC 36 that boosts digital signal D 1 to levels suitable for driving MDAC 36 . Level shifter 40 includes a booster 42 for boosting signals associated with each bit of digital signal D 1 (such as bits b 0 , b 1 , . . . through bn- 1 ). In various implementations, an n-bit flash ADC 34 boosts 2*n signals, such that each booster 42 boosts two signals associated with each bit of digital signal D 1

Pipeline ADC 10 can sample only as fast as flash ADC 34 in its first stage (Stage 1 ) can provide control signals, such as digital signal D 1 , to MDAC 36 . More specifically, MDAC 36 waits for a decision to propagate through flash ADC 34 , depicted as Flash Delay in FIG. 1 , and level shifter 40 , depicted as Boost Delay in FIG. 1 , before providing residue analog signal V RES1 . Similarly, each successive stage has an associated propagation delay. Pipeline ADC 10 is thus configured to minimize overall propagation delay (depicted as Total Delay) in each stage to optimize operations, for example, by maximizing sample rates. The following discussion describes various level shifter configurations for level shifter 40 that can be implemented in pipeline ADC 10 to optimize performance. The level shifter configurations described herein can exhibit minimal propagation delay (for example, minimal boost delay) and sufficient boost levels for driving MDAC 36 while using a core supply voltage (V DD ).

FIG. 2 is a schematic circuit diagram of an exemplary level shifter 100 according to various aspects of the present disclosure. Level shifter 100 is an electronic device (including an electronic circuit and/or one or more electronic components) that shifts a signal from one voltage level to another voltage level. In various implementations, level shifter 100 can connect one digital circuit that uses one logic level to another digital circuit that uses another logic level. For purposes of the following discussion, level shifter 100 can be implemented in pipeline ADC 10 , for example in Stage 1 , as level shifter 40 at an interface of flash ADC 34 and MDAC 36 . FIG. 2 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in level shifter 100 , and some of the features described can be replaced or eliminated in other embodiments of level shifter 100 .

Level shifter 100 includes a booster 105 has differential inputs (such as IN+ and IN−) arranged to receive differential input signals and differential outputs (such as OUT+ and OUT−) arranged to provide differential output signals. In the depicted embodiment, booster 105 is configured to receive a data signal SIG and a data signal SIGN and generate a digital output signal V OUT and a digital output signal V OUTN . Data signal SIG and data signal SIGN can transition between a low voltage level represented by a digital 0 and a high voltage level represented by a digital 1 . In various implementations, booster 105 boosts data signal SIG and data signal SIGN from flash ADC 34 (for example, from a latched comparator of flash ADC 34 ) sufficiently for driving MDAC 36 , represented by output signal V OUT and output signal V OUTN . Output signal V OUT and output signal V OUTN transition between a low voltage level (such as 0 V) and a high voltage level (V HI ) that is greater than control voltage V CTL (for example, V HI =V CTL +ΔV). Level shifter 100 can include more than one booster 105 , such that a booster is provided for boosting signals associated with each bit of a digital signal received from flash ADC 34 , such as bits b 0 , b 1 , . . . through bn- 1 .

Booster 105 can boost data signals (for example, digital signals received from flash ADC 34 ) by implementing a clock level shifter 110 and a switched capacitor logic controller 112 . Switched capacitor logic controller 112 level-shifts data signals for driving a load, where clock level shifter 110 generates a level shifted clock signal for driving switches of switched capacitor logic controller 112 . In various implementations, switched capacitor logic controller 112 is AC coupled to flash ADC 34 . For example, as described further below, booster 105 includes a charge capacitor placed in series between flash ADC 34 (in particular, a comparator of flash ADC 34 ) and MDAC 36 , such that the charge capacitor level-shifts data signals received from flash ADC 34 for sufficiently driving MDAC 36 , such as various switches of MDAC 36 . Such configuration can minimize propagation delay while using a supply voltage less than or equal to the core supply voltage.

Clock level shifter 110 receives an input clock φ 1 that transitions between a low voltage level and a high voltage level of an input clock voltage domain. For example, input clock φ 1 may transition between 0 V and a control voltage V CTL (such as a core supply voltage). From input clock φ 1 , clock level shifter 110 generates a level-shifted output clock φ 1S and a complementary level-shifted output clock φ 2S , which can be used to drive switched capacitor logic controller 112 . Level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S transition between a low voltage level and a high voltage level in an output clock voltage domain, which is different than the input clock voltage domain for input clock φ 1 . Clock level shifter 110 can be configured to up shift input clock φ 1 to generate level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S , where the input clock voltage domain's high voltage level can be used to set the low voltage level for the output clock voltage level domain. For example, level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S may transition between control voltage V CTL and a voltage greater than control voltage V CTL (such as V HI =V CTL +ΔV). Note that level-shifted output clock φ 1S has the output clock voltage domain's high voltage level when complementary level-shifted output clock φ 2S has the output clock voltage domain's low voltage level, and vice versa.

In FIG. 2 , clock level shifter 110 includes a pair of capacitors C X1 and C X2 , a pair of switches 114 A and 114 B, and an inverter 116 . In the depicted embodiment, switch 114 A and switch 114 B are cross-coupled transistors, such as cross-coupled p-type metal-oxide-semiconductor (PMOS) transistors. Each switch has a gate (G), a source (S), and a drain (D). Each switch 114 A and 114 B has its source coupled to control voltage V CTL . Switch 114 A has its gate coupled to the drain of switch 114 B, and switch 114 B has its gate coupled to the drain of switch 114 A. Capacitor C X1 has a first terminal coupled to a node N 1 (such that capacitor C X1 is also coupled to the drain of switch 114 B) and a second terminal coupled to an input node for receiving input clock φ 1 . Capacitor C X2 has a first terminal coupled to a node N 2 (such that capacitor C X2 is also coupled to the drain of switch 114 A) and a second terminal coupled to the input node for receiving a complement of input clock φ 1 . For example, capacitor C X2 has a second terminal coupled to inverter 116 , which provides a complementary input clock φ 1′ to capacitor C X2 . Capacitor C X1 and capacitor C X2 respectively provide level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S , which represent up-shifted versions of input clock φ 1 that may be taken respectively from node N 1 or node N 2 to drive switch capacitor logic controller 112 . During operation, switch 114 A and switch 114 B can be activated in an alternating manner to charge capacitors C X1 and C X2 , such that level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S can transition from the output clock domain's low voltage level (such as control voltage V CTL ) to the output clock domain's high voltage level (such as V HI =V CTL +ΔV). Capacitor sizes for capacitor C X1 and capacitor C X2 may be adjusted according to operating requirements for clock level shifter 110 , switched capacitor logic controller 112 , and/or level shifter 100 , such as desired output clock voltage domain levels.

Switched capacitor logic controller 112 drives (charges) a load, represented by a load capacitor C LOAD1 and a load capacitor C LOAD2 , using charge capacitors, such as a charge capacitor Cq 1 and a charge capacitor Cq 2 . In various implementations, charge capacitor Cq 1 and charge capacitor Cq 2 are placed in series between flash ADC 34 and MDAC 36 , where one plate (ADC side) of the charge capacitor is driven by a data signal from flash ADC 34 (data signal SIG or data signal SIGN) and one plate (MDAC side) is driven by a switched capacitor operation. In the depicted embodiment, a switched capacitor logic controller portion 112 A includes charge capacitor Cq 1 , an AND gate 120 A, and switch circuitry (a switch 122 A, a switch 124 A, and a switch 126 A); and a switched capacitor logic controller portion 112 B includes charge capacitor Cq 2 , an AND gate 122 B, and switch circuitry (a switch 122 B, a switch 124 B, and a switch 126 B). Charge capacitor Cq 1 has a terminal coupled to AND gate 112 A and another terminal coupled to switch 122 A. Charge capacitor Cq 2 has a terminal coupled to AND gate 120 B and another terminal coupled to switch 122 B.

AND gate 120 A and AND gate 120 B generate logic gate signals, a logic gate signal AND and a logic gate signal ANDB, for respectively powering (charging) load capacitor C LOAD1 and ad capacitor C LOAD2 , where charge capacitor Cq 1 and charge capacitor Cq 2 boost signal levels of logic gate signal AND and logic gate signal ANDB, and the switch circuitry respectively steers the boosted logic gate signals appropriately. In the depicted embodiment, a clock signal CLK gates decisions of switched capacitor logic controller 112 , where active rising edges of AND gate 120 A and AND gate 120 B provide logic gate signals for charging load capacitor C LOAD1 and load capacitor C LOAD2 , which are boosted respectively by charge capacitor Cq 1 and charge capacitor Cq 2 . The active rising edges of AND gate 120 A and AND gate 120 B can further control the switch circuitry that steers the boosted logic gate signals. Typically, a latched comparator of flash ADC 34 provides data signal SIG and data signal SIGN to booster 105 , where data signal SIG and data signal SIGN can have three possible output states when a clock signal of the flash ADC 34 is high, provided in Table 1 below.

When input voltage V IN is greater than its associated reference voltage V REF , latched comparator of flash ADC 34 outputs data signal SIG in a high state (such as a digital 1 ) and data signal SIGN in a low state (such as a digital 0 ). When input voltage V IN is less than its associated reference voltage V REF , latched comparator outputs data signal SIG in a low state and data signal SIGN in a high state. When latched comparator does not make a decision, latched comparator outputs data signal SIG and data signal SIGN in a low state. AND gate 120 A receives data signal SIG and clock signal CLK (in some implementations, associated with a system clock, such as a clock associated with pipeline ADC 10 ), and compares data signal SIG with clock signal CLK to generate logic gate signal AND. Similarly, AND gate 120 B receives data signal SIGN and clock signal CLK, and compares data signal SIGN with clock signal CLK to generate logic gate signal ANDB. In various implementations, AND gate 120 A outputs logic gate signal AND in a high state when data signal SIG and clock signal CLK are both in a high state, and outputs logic gate signal AND in a low state otherwise; and AND gate 120 B outputs logic gate signal ANDB in a high state when data signal SIGN and clock signal CLK are both in a high state, and outputs logic gate signal ANDB in a low state otherwise. For example, logic gate signal AND and logic gate signal ANDB can transition between a low voltage represented by a digital zero and a high voltage represented by a digital one. Table 2 depicts possible inputs and associated outputs for AND gate 120 A, and Table 3 depicts possible inputs and associated outputs for AND gate 120 B.

Accordingly, one of AND gate 120 A and AND gate 120 B will output a logic gate signal in a high state, such that only logic gate signal AND or logic gate signal ANDB is in a high state at a time. Such result can be referred to as a one-hot type output (result), meaning that at most, one load (either load capacitor C LOAD1 or load capacitor C LOAD2 ) is driven to a high state during a decision cycle. Therefore, only one of the two charge capacitors—charge capacitor Cq 1 or charge capacitor Cq 2 —is used during a decision cycle. Furthermore, it is noted that charge is delivered to load capacitor C LOAD1 or load capacitor C LOAD2 only upon flash ADC 34 generating a high output (in other words, either data signal SIG or data signal SIGN is a digital one).

Switches 122 A, 122 B, 124 A, 124 B, 126 A, and 126 B are transistors that include a gate (G) interposed by a source (S) and a drain (D), such as field effect transistors (FETs). Switch 122 A has a source coupled to charge capacitor Cq 1 (which is also coupled to a node X), a drain coupled to control voltage V CTL , and a gate coupled to complementary level-shifted output clock φ 2S ; and switch 122 B has a source coupled to charge capacitor Cq 2 (which is also coupled to a node XB), a drain coupled to control voltage V CTL , and a gate coupled to complementary level-shifted output clock φ 2S . Both switch 122 A and switch 122 B are driven by complementary level-shifted output clock φ 2S , which is generated by clock level shifter 110 , such that switch 122 A and switch 122 B transition to an on state when complementary level-shifted output clock φ 2S is in a high state. Switch 124 A has a gate coupled to control voltage V CTL , a drain coupled to differential output OUT+, and a source coupled to node X; and switch 124 B has a gate coupled to control voltage V CTL , a drain coupled to differential output OUT−, and a source coupled to node XB. Switch 126 A has a gate coupled to control voltage V CTL , a source coupled to AND gate 120 A, and a drain coupled to an output node O (which is coupled to differential output OUT+); and switch 126 B has a gate coupled to control voltage V CTL , a source coupled to AND gate 120 B, and a drain coupled to an output node OB (which is coupled to differential output OUT−). In the depicted embodiment, switch 122 A and switch 122 B are NMOS transistors, switch 124 A and switch 124 B are PMOS transistors, and switch 126 A and switch 126 B are NMOS transistors, though the present disclosure contemplates various configurations of NMOS and PMOS transistors for switched capacitor logic controller 112 .

In operation, when switch 122 A and switch 122 B are in an on state, a load side (such as the MDAC side) of charge capacitor Cq 1 and charge capacitor Cq 2 is charged to some voltage, for example, to control voltage V CTL . Switch 124 A and switch 124 B are source driven, such that switch 124 A and switch 124 B respectively conduct charge to load capacitor C LOAD1 and load capacitor C LOAD2 when a voltage of the source rises above a fixed voltage applied to the gate (here, control voltage V CTL ). For example, in an on state, switch 124 A conducts charge from node X to load capacitor C LOAD1 , where node X represents a level-shifted version of logic gate signal AND, thus providing output signal V OUT in a boosted state (for example, having high voltage level V HI ). Similarly, in an on state, switch 124 B conducts charge from node XB to load capacitor C LOAD2 , where node XB represents a level-shifted version of logic gate signal ANDB, thus providing output signal V OUTN in a boosted state (for example, having high voltage level V HI ). Since a phase of clock signal CLK gates AND gate 120 A and AND gate 120 B decisions, a voltage at the sources of switch 124 A and switch 124 B can be reset to control voltage V CTL when clock signal CLK is in a low state. For example, when complementary level-shifted clock signal φ 2S is in a high state, switch 122 A and switch 122 A initialize node X (and thus a voltage seen by sources of switch 124 A and switch 124 B) to control voltage V CTL providing refresh switch control for switch 124 A and switch 124 B on the complementary clock phase. Switch 126 A and switch 126 B can respectively keep output node O and output node OB in a low state, thus keeping output signal V OUT and output signal V OUTN set to the low state (such as 0 V) when neither gate decision is in a high state.

FIG. 3 is an exemplary timing diagram 150 associated with operation of level shifter 100 according to various aspects of the present disclosure. Here, timing diagram 150 is associated with switched capacitor logic controller portion 105 A, where AND gate 120 A drives a load, delivering charge to load capacitor C LOAD1 . In a simplistic example, for purposes of the following discussion, a signal having a voltage level of 0 V is represented by 0, a voltage level of control voltage V CTL is represented by 1, and a voltage level of high voltage V HI , (V HI =control voltage V CTL +ΔV) is represented by 2.

At time t 1 , input clock signal CLK is in a low state (0). Accordingly, clock level shifter 110 generates complementary level-shifted output clock φ 2S in a high state (2), transitioning switch 122 A to an on state for charging charge capacitor C q1 to control voltage V CTL , which also initializes node X to its associated low state, control voltage V CTL . AND gate 120 A generates logic gate signal AND in a low state (0), where both data signal SIG and input clock signal CLK are in a low state (0). Since a same voltage is applied to the gate and source of switch 124 A (for example, a voltage seen at the gate is control voltage V CTL and a voltage seen at the source is control voltage V CTL (the voltage at node X)), switch 124 A is in an off state, such that output signal V OUT is in a low state (0). Switch 126 A is also in an off state, again keeping node O in a low state.

At time t 2 , input clock signal CLK is in a high state (1). Accordingly, clock level shifter 110 generates complementary level-shifted output clock φ 2S in a low state (1), setting switch 122 A to an off state. AND gate 120 A generates logic gate signal AND in a low state (0), where data signal SIG is in a low state (0) and clock signal CLK is in the high state. Node X remains at its low state, control voltage V CTL . Again, since a same voltage is applied to the gate and source of switch 124 A (for example, a voltage seen at the gate is control voltage V CTL and a voltage seen at the source is control voltage V CTL (the voltage at node X)), switch 124 A is in an off state, such that output signal V OUT is in a low state (0). Switch 126 A is also in an off state, keeping node O in a low state.

At time t 3 , input clock signal CLK is in a low state (0). Accordingly, complementary level-shifted output clock φ 2S in a low state (1), transitioning switch 122 A to an off state. AND gate 120 A generates logic gate signal AND in a high state (1), where data signal SIG and clock signal CLK are both in a high state (1), increasing a voltage stored on charge capacitor C q1 from control voltage V CTL to some additional voltage. In a simplistic example, when charge capacitor C q1 receives logic gate signal AND in the high state, charge capacitor C q1 essentially adds voltage to the stored voltage, transitioning from the control voltage V CTL to some additional voltage to provide a level-shifted logic gate signal AND. For example, a voltage associated with a load side (or MDAC side) of charge capacitor C q1 rises from an initial level (such as control voltage V CTL ) to some additional voltage level (V HI =control voltage V CTL +ΔV). In various implementations, the additional voltage is a function of a ratio of the level-shifted capacitance (a capacitance of charge capacitor C q1 ) and the load capacitance (a capacitance of load capacitor C LOAD1 ). Charge capacitor C q1 thus provides the level-shifted logic gate signal AND to node X, transitioning node X to its high state, high voltage V HI . Since a different voltage is now applied to the gate and source of switch 124 A (for example, a voltage seen at the gate is control voltage V CTL and a voltage seen at the source is high voltage V HI (the voltage at node X)), switch 124 A transitions to an on state. Switch 124 A then pulls the level-shifted logic gate signal AND at node X to output node O, providing logic output signal V OUT in a boosted state (for example, having the high voltage V HI ). Further, switch 126 A transitions to an on state. In various implementations, boosted logic output signal V OUT exhibits signal levels that can sufficiently drive the load, such as MDAC 36 . It is understood that switched capacitor logic controller portion 112 B operates similarly, noting that only switched capacitor logic controller portion 112 A or switched capacitor logic controller portion 112 B will provide boosted signal levels at any one time. FIG. 3 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in timing diagram 150 , and some of the features described can be replaced or eliminated in other embodiments of timing diagram 150 .

In the depicted embodiment, keeping in mind that a charge (Q) between plates of a capacitor is given by:

where C is a capacitance of the capacitor and V is a voltage across plates of the capacitor, a maximum output voltage delivered to the load is a function of load capacitance (C LOAD ) (such as that associated with load capacitor C LOAD1 or load capacitor C LOAD2 ) to charge capacitance (C q ) (such as that associated with charge capacitor C q1 or charge capacitor C q2 ). In the present example, when the AND gate output transitions to a high state (for example, logic gate signal AND or logic gate signal ANDB transitions voltage from 0 V to control voltage V CTL ), the load (for example, output signal V OUT or output signal V OUTN ) rises from 0 V to:

where F is a fraction of V CTL represented by:

F = C q C q + C LOAD .

To achieve a desired fraction of control voltage swing to boost the voltage level by ΔV, a size of C q can be determined:

C q = F 1 - F × C LOAD .

Since C q is in series with C LOAD , the logic gate generating the boosted signal (here, AND gate 120 A or AND gate 120 B) sees an effective capacitance much lower than C q . Though this allows relatively small gates to deliver high slew rates, to produce a substantial increase in voltage and achieve desired voltage swings, level shifter 100 must typically implement a charge capacitor C q much larger than a load capacitor C LOAD . Such large charge capacitor C q can consume more than desirable area and power, particularly in the depicted embodiment, where two charge capacitors (charge capacitor C q1 and charge capacitor C q2 ) are needed for providing boosted signal levels. Charge capacitor C q may also heavily load the logic gate driver (here, the AND gate), necessitating that the logic gate driver generating the signal for boosting be sized up to increase drive strength to supply sufficient charge for the load capacitance. When implemented for level shifting signals from a flash ADC, an entire comparator will also likely consume more area and more power to compensate for the aforementioned issues. For example, since level shifters typically multiply the capacitive load on the flash ADC comparators, flash ADC area in its entirety must be increased to maintain very low propagation delay, increasing power and area of the entire signal path. Since ADCs typically implement many comparators in each pipeline stage, any additional area and power consumed will be multiplied by a total number of comparators used in the ADC.

As noted, level shifter 100 boosts signals using a one-hot type output (result), meaning that at most, one capacitor load (either load capacitor C LOAD1 or load capacitor C LOAD2 ) is driven to a high state during each decision cycle. Therefore, only one of the two charge capacitors—charge capacitor Cq 1 or charge capacitor Cq 2 —is used during a decision cycle. The present disclosure recognizes that the charge needed to drive both loads can be generated using a same charge capacitor (C q ), significantly decreasing a level shifter's power and area consumption. In particular, to boost N total signals, level shifter 100 needs 2*N charge capacitors (charge capacitor Cq 1 or charge capacitor Cq 2 ), dominating a significant area of booster 105 . By using a same charge capacitor for each signal, N charge capacitors can be implemented to provide significant area savings, for both the level shifter and the entire signal path when implemented in a pipeline ADC. Such level shifter configurations can be achieved by removing a burden of driving a capacitive load off the switched capacitor logic controller (and, more generally, a data signal buffer), instead placing this burden on circuitry that can more efficiently do such, particularly the clock level shifter.

The following describes various level shifter configurations that implement data signal controlled steering of a level shifted clock signal for charging the load. Instead of using the data signals to charge the load (such as logic gate signals from the AND gates), the level shifter configurations described herein charge the load with a clock buffer, where it is more efficiently handled by steering a level-shifted clock signal to generate a level-shifted (amplified) version of a non-periodic data signal. By using the data signals to merely steer the level shifted clock signal, significant power and area savings can be realized by the level shifter configurations described herein, along with the various components of the data path (such as the flash ADC). Essentially, the level shifter configurations described below can charge the load with a boosted supply, instead of a boosted data signal. Different embodiments may have different advantages, and no particular advantage is necessarily required of any of the embodiments described herein.

FIG. 4 is a schematic circuit diagram of an exemplary level shifter 200 according to various aspects of the present disclosure. Level shifter 200 is an electronic device (including an electronic circuit and/or one or more electronic components) that shifts a signal from one voltage level to another voltage level. In various implementations, level shifter 200 can connect one digital circuit that uses one logic level to another digital circuit that uses another logic level. For purposes of the following discussion, level shifter 200 can be implemented in pipeline ADC 10 , for example in Stage 1 , as booster 40 at an interface of flash ADC 34 and MDAC 36 . The embodiment of FIG. 4 is similar in many respects to the embodiment of FIG. 2 . Accordingly, similar features in FIG. 2 and FIG. 4 are identified by the same reference numerals for clarity and simplicity. FIG. 4 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in level shifter 200 , and some of the features described can be replaced or eliminated in other embodiments of level shifter 200 .

Level shifter 200 includes a booster 205 having differential inputs (such as IN+ and IN−) arranged to receive differential input signals and differential outputs (such as OUT+ and OUT−) arranged to provide differential output signals. In the depicted embodiment, booster 205 is configured to receive a data signal SIG and a data signal SIGN and generate a digital output signal V OUT and a digital output signal V OUTN —Data signal SIG and data signal SIGN can transition between a low voltage level represented by a digital 0 and a high voltage level represented by a digital 1 . In various implementations, booster 205 boosts data signal SIG and data signal SIGN from flash ADC 34 (for example, from a latched comparator of flash ADC 34 ) sufficiently for driving MDAC 36 , represented by output signal V OUT and output signal V OUTN —Output signal V OUT and output signal V OUTN transition between a low voltage level (such as 0 V) and a high voltage level (V HI ) that is greater than control voltage V CTL (for example, V HI =V CTL +ΔV). Level shifter 200 can include more than one booster 205 , such that a booster is provided for boosting signals associated with each bit of a digital signal received from flash ADC 34 , such as bits b 0 , b 1 , . . . through bn- 1 .

Booster 205 can also boost data signals (for example, digital signals received from flash ADC 34 ) by implementing a clock level shifter 210 and a switched capacitor logic controller 212 . In FIG. 4 , in contrast to level shifter 100 , booster 205 uses a level shifted clock signal for charging the load, instead of a level shifted data signal. More specifically, clock level shifter 210 generates a level-shifted clock signal for delivering charge to the load, and switched capacitor logic controller 212 steers the level-shifted clock signal appropriately. The switched capacitor logic controller 212 (data path) thus drives a fraction of the load, compared to the switched capacitor logic controller 112 of level shifter 100 , such that it can be much smaller, consuming less power and less area and further simplifying a data signal chain. Such configuration can also minimize propagation delay while using a supply voltage less than or equal to the core supply voltage.

Clock level shifter 210 receives an input clock signal CLK that transitions between a low voltage level and a high voltage level of an input clock voltage domain. For example, input clock signal CLK may transition between 0 V and a control voltage V CTL (such as a core supply voltage). From input clock signal CLK, clock level shifter 210 generates a level-shifted output clock φ 1S and a complementary level-shifted output clock φ 2S , where level-shifted output clock φ 1S can be used to charge the load (here, a load capacitor C LOAD1 and a load capacitor C LOAD2 ) and complementary level-shifted output clock φ 2S can be used to drive switch capacitor logic controller 212 . Level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S transition between a low voltage level and a high voltage level in an output clock voltage domain, which is different than the input clock voltage domain for input clock φ 1 . Clock level shifter 210 can be configured to up shift input clock φ 1 to generate level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S , where the input clock voltage domain's high voltage level can be used to set the low voltage level for the output clock voltage level domain. For example, level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S may transition between control voltage V CTL and a voltage greater than control voltage V CTL (such as V HI =V CTL +ΔV). Note that level-shifted output clock φ 1S has the output clock voltage domain's high voltage level when complementary level-shifted output clock φ 2S has the output clock voltage domain's low voltage level, and vice versa.

Clock level shifter 210 can include a pair of capacitors C X1 and C X2 , a pair of switches 214 A and 214 B, and an inverter 216 . In the depicted embodiment, switch 214 A and switch 214 B are cross-coupled transistors, such as cross-coupled p-type metal-oxide-semiconductor (PMOS) transistors. Each switch has a gate (G), a source (S), and a drain (D). Each switch 214 A and 214 B has its source coupled to control voltage V CTL . Switch 214 B has its gate coupled to the drain of switch 214 A, and switch 214 A has its gate coupled to the drain of switch 214 B. Capacitor C X1 has a first terminal coupled to node N 1 (such that capacitor C X1 is also coupled to the drain of switch 2146 ) and a second terminal coupled to an input node for receiving input clock signal CLK. Capacitor C X2 has a first terminal coupled to node N 2 (such that capacitor C X2 is also coupled to the drain of switch 214 A) and a second terminal coupled to the input node for receiving a complement of input clock signal CLK. For example, capacitor C X2 has a second terminal coupled to inverter 216 , which provides a complementary input clock signal CLK′ to capacitor C X2 . Capacitor C X1 and capacitor C X2 respectively provide level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S , which represent up-shifted versions of input clock φ 1 that may be taken respectively from node N 1 or node N 2 to charge the load and drive switch capacitor logic controller 112 .

In operation, clock level shifter 210 drives (charges) a load, represented by load capacitor C LOAD1 and load capacitor C LOAD2 . In the depicted embodiment, capacitor C X1 serves as a charge capacitor C q for charging both load capacitor C LOAD and load capacitor C LOAD2 , where charge capacitor C q provides level-shifted output clock φ 1S for charging the load. Node N 3 represents the level-shifted version of input clock signal CLK, which is coupled to switched capacitor logic controller 212 . Further, complementary level-shifted output clock φ 2S can be used to drive switch circuitry of switch capacitor logic controller 212 . Switch 214 A and switch 214 B can be activated in an alternating manner for charging charge capacitor C q and capacitor C X2 , such that level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S can transition from the output clock domain's low voltage level (control voltage V CTL ) to the output clock domain's high voltage level (V HI =V CTL +ΔV). Capacitor sizes for capacitor C X1 and capacitor C X2 may be adjusted according to operating requirements for clock level shifter 210 , switched capacitor logic controller 212 , and/or level shifter 200 , such as desired output clock voltage domain levels.

Switched capacitor logic controller 212 is AC coupled to clock level shifter 210 . Switched capacitor logic controller 212 steers level-shifted output clock φ 1S to appropriately charge load capacitor C LOAD1 and load capacitor C LOAD2 . In level shifter 200 , switched capacitor logic controller 212 implements a negated AND (NAND) logic gate and switch circuitry for steering. For example, in the depicted embodiment, a switched capacitor logic controller portion 212 A includes capacitor C X3A , an NAND gate 220 A, and switch circuitry (a switch 222 A, a switch 224 A, a switch 226 A, and a switch 228 A); and a switched capacitor logic controller portion 212 B includes capacitor C X3B , an NAND gate 220 B, and switch circuitry (a switch 222 B, a switch 224 B, a switch 226 B, and a switch 228 B). Capacitor C X3A has a terminal coupled to an input node for receiving input clock signal CLK and another terminal coupled to switch 222 A, such that capacitor C X3A can provide and up-shifted version of input clock signal CLK at node X. Similarly, capacitor C X3B also has a terminal coupled to the input node for receiving input clock signal CLK and another terminal coupled to switch 222 B, such that capacitor C X3B can provide and up-shifted version of input clock signal CLK at node XB.

NAND gate 220 A and NAND gate 220 B generate logic gate signals, a logic gate signal NAND and a logic gate signal NANDB, for respectively steering level-shifted output clock φ 1S for charging the load—here, load capacitor C LOAD1 and load capacitor C LOAD2 . In the depicted embodiment, input clock signal CLK for clock level shifter 210 also gates decisions of switched capacitor logic controller 212 , where active falling edges of NAND gate 220 A and NAND gate 220 B provide logic gate signals for controlling the switch circuitry that steers charge associated with level-shifted output clock φ 1S to load capacitor C LOAD1 and load capacitor C LOAD . Typically, a latched comparator of flash ADC 34 can provide data signal SIG and data signal SIGN to booster 205 , where the various output states for data signal SIG and data signal SIGN are depicted in Table 1 above. In the depicted embodiment, NAND gate 220 A receives data signal SIG and input clock signal CLK, and compares data signal SIG with input clock signal CLK to generate logic gate signal NAND. Similarly, NAND gate 220 B receives data signal SIGN and input clock signal CLK, and compares data signal SIGN with input clock signal CLK to generate logic gate signal NANDB. In various implementations, NAND gate 220 A outputs logic gate signal NAND in a low state when data signal SIG and input clock signal CLK are both in a high state, and outputs logic gate signal NAND in a high state otherwise; and NAND gate 220 B outputs logic gate signal NANDB in a low state when data signal SIGN and input clock signal CLK are both in a high state, and outputs logic gate signal NANDB in a high state otherwise. For example, logic gate signal NAND and logic gate signal NANDB can transition between a low voltage represented by a digital zero and a high voltage represented by a digital one. Table 4 depicts possible inputs and associated outputs for NAND gate 220 A, and Table 5 depicts possible inputs and associated outputs for NAND gate 220 B.

Accordingly, one of NAND gate 220 A and NAND gate 220 B will output a logic gate signal in a high state. Since switched capacitor logic controller 212 exhibits a one-hot type output (result), meaning that either NAND gate 220 A or NAND gate 220 B will be driven to a low state, level shifter 200 can implement a single charge capacitor—charge capacitor C q —for delivering charge to load capacitor C LOAD1 or load capacitor C LOAD2 when flash ADC 34 generates a high output (in other words, either data signal SIG or data signal SIGN is a digital one).

Switches 222 A, 222 B, 224 A, 224 B, 226 A, 226 B, 228 A, and 228 B are transistors that include a gate (G) interposed by a source (S) and a drain (D), such as field effect transistors (FETs). Switch 222 A is coupled to a terminal of capacitor C X3A (which is also coupled to a Node X) and control voltage V CTL ; and switch 222 B is coupled to a terminal of capacitor C X3B (which is also coupled to a Node XB) and control voltage V CTL . Both switch 222 A and switch 222 B are driven by complementary level-shifted output clock φ 2S , which is generated by clock level shifter 210 , such that switch 222 A and switch 222 B transition to an on state when complementary level-shifted output clock φ 2S is in a high state. Switch 224 A has a gate coupled to node X, a drain coupled to differential output OUT+, and a source coupled to node N 3 ; and switch 224 B has a gate coupled to node XB, a drain coupled to differential output OUT−, and a source coupled to node N 3 . Switch 226 A has a gate coupled to control voltage V CTL a source coupled to NAND gate 220 A, and a drain coupled to node X; and switch 226 B has a gate coupled to control voltage V CTL a source coupled to NAND gate 220 B, and a drain coupled to node X. Switch 228 A has a gate coupled to NAND gate 220 A, a source coupled to ground, and a drain coupled to an output node O (which is coupled to differential output OUT+); and switch 228 B has a gate coupled to NAND gage 220 B, a source coupled to ground, and a drain coupled to an output node OB (which is coupled to differential output OUT−). In the depicted embodiment, switch 222 A and switch 222 B are NMOS transistors, switch 224 A and switch 224 B are PMOS transistors, switch 226 A and switch 226 B are NMOS transistors, and switch 228 A and switch 228 B are NMOS transistors, though the present disclosure contemplates various configurations.

In operation, when switch 222 A and switch 222 B are in an on state, capacitor C X3A and capacitor C X3B are charged to control voltage V CTL such that node X and node XB are respectively initialized to control voltage C X1 Clock level shifter 210 drives voltages for operating switch 224 A and switch 224 B, particularly a voltage seen at node X and a voltage seen at node N 3 . In the depicted embodiment, a clock phase of input clock signal CLK drives the voltage seen at node X and node N 3 from control voltage V CTL to a high voltage V HI (where V HI =control voltage V CTL =ΔV). When a same voltage is applied to sources and gates of switch 224 A and switch 224 B, switch 224 A and switch 224 B remain in an off state, holding a voltage seen by the load to 0 V. Switch 224 A and switch 224 B are source driven, such that switch 224 A and switch 224 B respectively conduct charge to load capacitor C LOAD and load capacitor C LOAD2 when a voltage applied to the source rises above a voltage applied to the gate. In various implementations, a voltage applied to gates of switch 224 A and switch 224 B changes when its respective NAND gate (NAND gate 220 A or NAND gate 220 B) transitions to a low state, causing node X to transition to a low state. When in an on state, switch 224 A conducts charge from node N 3 to load capacitor C LOAD1 , where node N 3 represents level-shifted output clock φ 1S , thus providing output signal V OUT in a boosted state. Similarly, in an on state, switch 224 B conducts charge from node N 3 to load capacitor C LOAD2 , thus providing output signal V OUTN in a boosted state. Note that both switch 224 A and switch 224 B conduct charge from charge capacitor C q . Switch 226 A and switch 226 B are also source driven, such that switch 226 A pulls some voltage (ΔV dn ) when in an on state, causing the voltage applied to the gate of switch 224 A to drop below the voltage applied to the source of switch 224 A, and switch 226 B pulls some voltage (ΔV dn ) when in an on state, causing the voltage applied to the gate of switch 224 B to drop below the voltage applied to the source of switch 224 B. Further, since switch 228 A and switch 228 B remain off until its respective NAND gate 220 A and NAND gate 220 B transitions to a low state, switch 228 A and switch 228 B can respectively keep output node O and output node OB in a low state, and thus keeping output signal V OUT and output signal V OUTN set to the low state (such as 0 V) when neither gate decision is in a low state. In various implementations, if flash ADC 34 outputs data signal SIG or data signal SIGN in a high state (1), switched capacitor logic controller 212 will steer level-shifted output clock φ 1S to MDAC 36 , such that corresponding MDAC switches transition to an on state. If neither data signal transitions to the high state, then no level-shifted signals (and thus no level-shifted voltages) are connected to MDAC 36 , such that MDAC switches remain in the off state.

FIG. 5 is an exemplary timing diagram 250 associated with operation of level shifter 200 according to various aspects of the present disclosure. Here, timing diagram 250 is associated with switched capacitor logic controller portion 205 A, where clock level shifter 210 generates charge for the load, such as load capacitor C LOAD1 , and switched capacitor logic controller 212 steers the charge to load capacitor C LOAD1 . In a simplistic example, for purposes of the following discussion, a signal having a voltage level of 0 V is represented by 0, a voltage level of control voltage V CTL is represented by 1, and a voltage level of high voltage V HI (V HI =control voltage V CTL +ΔV) is represented by 2.

At time t 1 , input clock signal CLK is in a low state (0). Accordingly, clock level shifter 210 generates level shifted output clock φ 1S in a low state (1) and complementary level-shifted output clock φ 2S in a high state (2). Complementary level-shifted output clock φ 2S transitions switch 222 A to an on state, charging capacitor C X3A to control voltage V CTL , thus initializing node X at a low state, such as control voltage V CTL . Node N 3 is also initialized (set) to the low state, such as control voltage V CTL by level shifted output clock φ 1S in the low state. Since node X and node N 3 are in a low state, a same voltage is applied to the gate and source of switch 224 A, keeping switch 224 A in an off state, such that output signal V OUT is in a low state (0). Further, NAND gate 220 A generates logic gate signal NAND in a high state (1), where data signal SIG is in a low state (0) and input CLK is in the low state (0). Switch 226 A remains off since a voltage applied to its gate (control voltage V CTL ) is the same as a voltage applied to its source (for example, logic gate signal NAND's high state corresponds with control voltage V CTL ), ensuring that node X remains in the low state. Switch 228 A also remains in an off state, keeping node O in the low state.

At time t 2 , input clock signal CLK is in a high state (1), and clock level shifter 210 generates level-shifted output clock φ 1S in a high state (2) and complementary level-shifted output clock φ 2S in a low state (1), transitioning switch 222 A to an off state. Capacitor C X3A can generate an up-shifted input clock signal CLK for charging node X to a high state (for example, V HI =V CTL +ΔV), and charge capacitor C q generates level-shifted output clock φ 1S for charging node N 3 to the high state. Since node X and node N 3 are both in the high state, a same voltage is still applied to the gate and source of switch 224 A, keeping switch 224 A in an off state, such that output signal V OUT remains in the low state (0). Further, NAND gate 220 A generates logic gate signal NAND in a high state (1), where data signal SIG is in a low state (0) and input CLK is in the high state (1). Switch 226 A remains off since the voltage applied to its gate is still the same as the voltage applied to its source, ensuring that node X remains in the low state. Switch 228 A also remains in an off state, keeping node O in the low state.

At time t 3 , input clock signal CLK is again in a high state (1), and clock level shifter 210 generates level-shifted output clock φ 1S in a high state (2) and complementary level-shifted output clock φ 2S in a low state (1), transitioning switch 222 A to an off state. Capacitor C X3A generates the up-shifted input clock signal CLK for charging node X to a high state (for example, V HI =V CTL +ΔV), and charge capacitor C q generates level-shifted output clock φ 1S for charging node N 3 to the high state. In contrast to time t 2 , at time t 3 , NAND gate 220 A generates logic gate signal NAND in a low state (0), where data signal SIG is in a high state (1) and input CLK is in the high state (1). Switch 226 A thus transitions on since the voltage applied to its gate (for example, control voltage V CTL ) is now different than the voltage applied to its source (for example, logic gate signal NAND's low state corresponds with 0 V), pulling node X to the low state (0) and transitioning switch 224 A to an on state (since a voltage seen by the source at node N 3 (V HI =control voltage V CTL +ΔV) is now greater than the voltage seen by the gate at node X (control voltage V CTL )). Switch 224 A then pulls the level-shifted clock signal φ 1S at node N 3 to output node O, providing logic output signal V OUT in a boosted state, a high voltage V HI (represented as a 2 in FIG. 5 ). Switch 228 A also transitions to an on state. In level shifter 200 , NAND gate 220 A and NAND gate 220 B thus discharge node X and node XB respectively when data signal SIG or data signal SIG is in a high state, steering the boosted output at node N 3 . In various implementations, boosted logic output signal V OUT exhibits signal levels that can sufficiently drive the load, such as MDAC 36 . It is understood that switched capacitor logic controller portion 212 B operates similarly, noting that only switched capacitor logic controller portion 212 A or switched capacitor logic controller portion 212 B will provide boosted signal levels at any one time. FIG. 5 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in timing diagram 250 , and some of the features described can be replaced or eliminated in other embodiments of timing diagram 250 .

FIG. 6 is a schematic circuit diagram of an exemplary level shifter 300 according to various aspects of the present disclosure. Level shifter 300 is an electronic device (including an electronic circuit and/or one or more electronic components) that shifts a signal from one voltage level to another voltage level. In various implementations, level shifter 300 can connect one digital circuit that uses one logic level to another digital circuit that uses another logic level. For purposes of the following discussion, level shifter 300 can be implemented in pipeline ADC 10 , for example in Stage 1 , as booster 40 at an interface of flash ADC 34 and MDAC 36 . The embodiment of FIG. 6 is similar in many respects to the embodiment of FIG. 4 . Accordingly, similar features in FIG. 4 and FIG. 6 are identified by the same reference numerals for clarity and simplicity. FIG. 6 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in level shifter 300 , and some of the features described can be replaced or eliminated in other embodiments of level shifter 300 .

Level shifter 300 includes a booster 305 having differential inputs (such as IN+ and IN−) arranged to receive differential input signals and differential outputs (such as OUT+ and OUT−) arranged to provide differential output signals. In the depicted embodiment, booster 305 is configured to receive a data signal SIG and a data signal SIGN and generate a digital output signal V OUT and a digital output signal V OUTN − Data signal SIG and data signal SIGN can transition between a low voltage level represented by a digital 0 and a high voltage level represented by a digital 1 . In various implementations, booster 305 boosts data signal SIG and data signal SIGN from flash ADC 34 (for example, from a latched comparator of flash ADC 34 ) sufficiently for driving MDAC 36 , represented by output signal V OUT and output signal V OUTN −Output signal V OUT and output signal V OUTN transition between a low voltage level (such as 0 V) and a high voltage level (V HI ) that is greater than control voltage V HI =V CTL +ΔV). Level shifter 300 can include more than one booster 305 , such that a booster is provided for boosting signals associated with each bit of a digital signal received from flash ADC 34 , such as bits b 0 , b 1 , . . . through bn- 1 .

Booster 305 can also boost data signals (for example, digital signals received from flash ADC 34 ) by implementing clock level shifter 210 and a switched capacitor logic controller 312 . In FIG. 6 , in contrast to level shifter 100 and similar to level shifter 200 , booster 305 uses a level shifted clock signal for charging the load, instead of a level shifted data signal. More specifically, clock level shifter 210 generates a level-shifted clock signal for delivering charge to the load, and switched capacitor logic controller 312 steers the level-shifted clock signal appropriately. The switched capacitor logic controller 312 (data path) thus drives a fraction of the load, such that it can be much smaller, consuming less power and less area and further simplifying a data signal chain. Such configuration can also minimize propagation delay while using a supply voltage less than or equal to the core supply voltage.

Level shifter 300 implements clock level shifter 210 as configured and operated as described above with reference to level shifter 200 depicted in FIG. 4 . For example, in operation, clock level shifter 210 drives (charges) a load, represented by load capacitor C LOAD1 and load capacitor C LOAD2 . In the depicted embodiment, capacitor C X1 serves as a charge capacitor C q for charging both load capacitor C LOAD1 and load capacitor C LOAD2 , where charge capacitor C q provides level-shifted output clock φ 1S for charging the load. Node N 3 thus represents a level-shifted version of input clock signal CLK. In furtherance of the depicted embodiment, complementary level-shifted output clock φ 2S , generated from complementary input clock signal CLK′, can be used to drive switch circuitry of switch capacitor logic controller 312 . Switch 214 A and switch 214 B can be activated in an alternating manner for charging charge capacitor C q and capacitor C X2 , such that level-shifted output clock φ 1S and complementary level-shifted output clock φ 2S can transition from the output clock domain's low voltage level (such as V CTL ) to the output clock domain's high voltage level (such as V H1 =V CTL +ΔV). Capacitor sizes for capacitor C X1 and capacitor C X2 may be adjusted according to operating requirements for clock level shifter 210 , switched capacitor logic controller 312 , and/or level shifter 300 , such as desired output clock voltage domain levels.

Switched capacitor logic controller 312 steers (pulls) level-shifted output clock φ 1S to appropriately charge load capacitor C LOAD1 and load capacitor C LOAD2 . In level shifter 300 , switched capacitor logic controller 312 implements a NOR logic gate and switch circuitry for steering level-shifted output clock φ 1S . For example, in the depicted embodiment, a switched capacitor logic controller portion 312 A includes capacitor C X3A , a NOR gate 320 A, and switch circuitry (a switch 322 A, a switch 324 A, and a switch 326 A); and a switched capacitor logic controller portion 312 B includes capacitor C X3B , a NOR gate 320 B, and switch circuitry (a switch 322 B, a switch 324 B, and a switch 326 B). NOR gate 320 A and NOR gate 320 B generate logic gate signals, a logic gate signal NOR and a logic gate signal NORB, for respectively steering level-shifted output clock φ 1S for charging the load—here, load capacitor C LOAD1 and load capacitor C LOAD2 . In contrast to level shifter 200 , level shifter 300 uses complementary input clock signal CLK′ of clock level shifter 210 for gating decisions of switched capacitor logic controller 312 , where active falling edges of NOR gate 320 A and NOR gate 320 B provide logic gate signals for controlling the switch circuitry that steers charge associated with level-shifted output clock φ 1S to load capacitor C LOAD1 and load capacitor C LOAD2 . As noted above, a latched comparator of flash ADC 34 can provide data signal SIG and data signal SIGN to booster 305 , where the various output states for data signal SIG and data signal SIGN are depicted in Table 1 above. In the depicted embodiment, NOR gate 320 A receives data signal SIG and complementary input clock signal CLK′, and compares data signal SIG with complementary input clock signal CLK′ to generate logic gate signal NOR. Similarly, NOR gate 320 B receives data signal SIGN and complementary input clock signal CLK′, and compares data signal SIGN with complementary input clock signal CLK′ to generate logic gate signal NORB. In various implementations, NOR gate 320 A outputs logic gate signal NOR in a high state when data signal SIG and complementary input clock signal CLK′ are both in a low state, and outputs logic gate signal NOR in a low state otherwise; and NOR gate 320 B outputs logic gate signal NORB in a high state when data signal SIGN and complementary input clock signal CLK′ are both in a low state, and outputs logic gate signal NORB in a low state otherwise. For example, logic gate signal NOR and logic gate signal NORB can transition between a low voltage represented by a digital zero and a high voltage represented by a digital one. Table 6 depicts possible inputs and associated outputs for NOR gate 320 A, and Table 7 depicts possible inputs and associated outputs for NOR gate 320 B.

Accordingly, one of NOR gate 320 A and NOR gate 320 B will output a logic gate signal in a high state. Since switched capacitor logic controller 312 exhibits a one-hot type output (result), meaning that either NOR gate 320 A or NOR gate 320 B will be driven to a high state, level shifter 300 can implement a single charge capacitor—charge capacitor C q —for delivering charge to load capacitor C LOAD1 or load capacitor C LOAD2 when flash ADC 34 generates a low output (in other words, either data signal SIG or data signal SIGN is a digital one).

Switches 322 A, 322 B, 324 A, 324 B, 326 A, and 326 B are transistors that include a gate (G) interposed by a source (S) and a drain (D), such as field effect transistors (FETs). Switch 322 A is coupled to a terminal of capacitor C X3A (which is also coupled to a node X) and control voltage V CTL ; and switch 322 B is coupled to a terminal of capacitor C X3B (which is also coupled to a node XB) and control voltage V CTL . Both switch 322 A and switch 322 B are driven by complementary level-shifted output clock φ 2S , which is generated by clock level shifter 210 , such that switch 322 A and switch 322 B transition to an on state when complementary level-shifted output clock φ 2S is in a high state. Capacitor C X3A has a terminal coupled to NOR gate 320 A and another terminal coupled to switch 322 A, such that capacitor C X3A can provide and up-shifted version of logic gate signal NOR at node X, depending on a phase of complementary input clock signal CLK′ and data signal SIG. Capacitor C X3B has a terminal coupled to NOR gate 320 B and another terminal coupled to switch 322 B, such that capacitor C X3B can provide and up-shifted version of logic gate signal NORB at node XB, depending on a phase of complementary input clock signal CLK′ and data signal SIGN. Switch 324 A has a gate coupled to node X, a drain coupled to differential output OUT+, and a source coupled to node N 3 ; and switch 324 B has a gate coupled to node XB, a drain coupled to differential output OUT−, and a source coupled to node N 3 . Switch 326 A has a gate coupled to NOR gate 320 A, a source coupled to ground, and a drain coupled to an output node O (which is coupled to differential output OUT+); and switch 326 B has a gate coupled to NOR gate 320 B, a source coupled to ground, and a drain coupled to an output node OB (which is coupled to differential output OUT−). In the depicted embodiment, switch 322 A and switch 322 B are NMOS transistors, switch 324 A and switch 324 B are PMOS transistors, and switch 326 A and switch 326 B are NMOS transistors, though the present disclosure contemplates various configurations.

In operation, when switch 322 A and switch 322 B are in an on state, capacitor C X3A and capacitor C X3B are charged to control voltage V CTL such that node X and node XB are also respectively initialized to control voltage V CTL . Clock level shifter 210 drives voltages for operating switch 324 A and switch 324 B, particularly a voltage seen at node N 3 . In the depicted embodiment, a clock phase of input clock signal CLK drives the voltage seen at node N 3 from control voltage V CTL to a high voltage V HI (where V HI =control voltage V CTL +ΔV). When a same voltage is applied to sources and gates of switch 324 A and switch 324 B, switch 324 A and switch 324 B remain in an off state, holding a voltage seen by the load to 0 V. Switch 324 A and switch 324 B are source driven, such that switch 324 A and switch 324 B respectively conduct charge to load capacitor C LOAD1 and load capacitor C LOAD2 when a voltage applied to the source rises above a voltage applied to the gate. In various implementations, a voltage applied to gates of switch 324 A and switch 324 B changes when its respective NOR gate (NOR gate 320 A or NOR gate 320 B) transitions to a high state, causing node X to transition to a low state. When in an on state, switch 324 A conducts charge from node N 3 to load capacitor C LOAD where node N 3 represents level-shifted output clock φ 1S , thus providing output signal V OUT in a boosted state. Similarly, in an on state, switch 324 B conducts charge from node N 3 to load capacitor C LOAD2 , thus providing output signal V OUTN in a boosted state. Note that both switch 324 A and switch 324 B conduct charge from charge capacitor C q . Since switch 326 A and switch 326 B remain off until its respective NOR gate 320 A and NOR gate 320 B transitions to a high state, switch 326 A and switch 326 B can respectively keep output node O and output node OB in a low state, and thus keep output signal V OUT and output signal V OUTN set to the low state (such as 0 V) when neither gate decision is in a high state. In various implementations, if flash ADC 34 outputs data signal SIG or data signal SIGN in a low state (0) while complementary input clock signal CLK′ is also in a low state (0), switched capacitor logic controller 312 will steer level-shifted output clock φ 1S to MDAC 36 , such that corresponding MDAC switches can transition to an on state. If neither data signal SIG or data signal SIGN transitions to the low state, then no level-shifted signals (and thus no level-shifted voltages) are connected to MDAC 36 , such that MDAC switches remain in the off state.

FIG. 7 is an exemplary timing diagram 350 associated with operation of level shifter 300 according to various aspects of the present disclosure. Here, timing diagram 350 is associated with switched capacitor logic controller portion 312 A, where clock level shifter 210 generates charge for the load, such as load capacitor C LOAD and switched capacitor logic controller 312 steers the charge to load capacitor C LOAD . In a simplistic example, for purposes of the following discussion, a signal having a voltage level of 0 V is represented by 0, a voltage level of control voltage V CTL is represented by 1, and a voltage level of high voltage V HI (V HI =control voltage V CTL +ΔV) is represented by 2.

At time t 1 , input clock signal CLK is in a low state (0), and complementary input clock signal CLK′ is in a high state (1). Accordingly, clock level shifter 210 generates level-shifted output clock φ 1S in a low state (1) and complementary level-shifted output clock φ 2S in a high state (2). Complementary level-shifted output clock φ 2S transitions switch 322 A to an on state, charging capacitor C X3A to control voltage V CTL . Further, since data signal SIG is in a low state (0) and complementary input clock signal CLK′ is in the high state, NOR gate 320 A generates logic gate signal NOR in a low state (0). Node N 3 and node X are thus initialized (set) to a low state, such as control voltage V CTL . Since node X and node N 3 are in a low state, a same voltage is applied to the gate and source of switch 324 A, keeping switch 324 A in an off state, such that output signal V OUT is in a low state (0). Switch 326 A also remains in an off state, keeping node O in the low state.

At time t 2 , input clock signal CLK is in a high state (1), and complementary input clock signal CLK′ is in a low state (0). Accordingly, clock level shifter 210 generates level-shifted output clock φ 1S in a high state (2) and complementary level-shifted output clock φ 2S in a low state (1), transitioning switch 322 A to an off state. Further, since data signal SIG is in a low state (0) and complementary input clock signal CLK′ is in the low state, NOR gate 320 A generates logic gate signal NOR in a high state (1). Capacitor C X3A can generate an up-shifted logic gate signal NOR for charging node X to a high state (for example, V HI =V CTL +ΔV), and charge capacitor C q generates level-shifted output clock φ 1S for charging node N 3 to the high state. Since node X and node N 3 are both in the high state, a same voltage is still applied to the gate and source of switch 324 A, keeping switch 324 A in an off state, such that output signal V OUT remains in the low state (0). Switch 326 A transitions to an on state, keeping node O in the low state.

At time t 3 , input clock signal CLK is again in a high state (1), and complementary input clock signal CLK′ is in a low state (0). Accordingly, clock level shifter 210 generates level-shifted output clock φ 1S in a high state (2) and complementary level-shifted output clock φ 2S in a low state (1), transitioning switch 322 A to an off state. Further, since data signal SIG is in a high state (1) and complementary input clock signal CLK′ is in the low state, NOR gate 320 A generates logic gate signal NOR in a low state (0), which pulls node X from the high state (V HI =control voltage V CTL +ΔV) to the low state (control voltage V CTL ). Since a voltage seen by the source at node N 3 (V HI =control voltage V CTL +ΔV) is now greater than the voltage seen by the gate at node X (control voltage V CTL ), switch 324 A transitions to an on state, pulling the level-shifted clock signal φ 1S at node N 3 to output node 0 , providing logic output signal V OUT in a boosted state, a high voltage V HI (represented as a 2 in FIG. 7 ). Switch 326 A remains in an off state. Accordingly, in level shifter 300 , on falling edges of complementary input clock signal CLK′, NOR gate 320 A and NOR gate 320 B respectively keep switch 324 A and switch 324 B in an off state until one of data signal SIG or data signal SIGN are in a high state, enabling a gate of the respective switch 324 A or switch 324 B. NOR gate 320 A and NOR gate 320 B thus serve a dual purpose of respectively boosting node X and node XB, as well as steering boosted output at node N 3 with a data decision by discharging node X and node XB respectively. In various implementations, boosted logic output signal V OUT exhibits signal levels that can sufficiently drive the load, such as MDAC 36 . It is understood that switched capacitor logic controller portion 312 B operates similarly, noting that only switched capacitor logic controller portion 312 A or switched capacitor logic controller portion 312 B will provide boosted signal levels at any one time. FIG. 7 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in timing diagram 350 , and some of the features described can be replaced or eliminated in other embodiments of timing diagram 350 .

In various implementations, level shifters (for example, level shifter 100 , level shifter 200 , and level shifter 300 ) systems for implementing the level shifters (for example, pipeline ADC 10 ), and/or the various circuits and/or components of the FIGURES can be implemented on a board of an associated electronic device. The board can be a general circuit board that can hold various components of an internal electronic system of the electronic device and, further, provide connectors for other peripherals. The board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc. can be suitably coupled to the board based on particular configuration needs, processing demands, computer designs, other considerations, or a combination thereof. Other components, such as external storage, sensors, controllers for audio/video display, and peripheral devices may be attached to the board as plug-in cards, via cables, or integrated into the board itself. In various implementations, level shifters (for example, level shifter 100 , level shifter 200 , and level shifter 300 ) systems for implementing the level shifters (for example, pipeline ADC 10 ), and/or the various circuits and/or components of the FIGURES can be implemented as stand-alone modules (for example, a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices. Note that particular embodiments of the present disclosure may be readily included in a system-on-chip (SOC) package, either in part, or in whole. An SOC represents an integrated circuit that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of separate ICs located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the various functions described herein may be implemented in one or more semiconductor cores (such as silicon cores) in application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), other semiconductor chips, or combinations thereof.

Note that the activities discussed above with reference to the FIGURES are applicable to any integrated circuits that involve signal processing, particularly those that can execute specialized software programs or algorithms, some of which may be associated with processing digitized real-time data. Certain embodiments can relate to multi-DSP signal processing, floating point processing, signal/control processing, fixed-function processing, microcontroller applications, etc. In certain contexts, the features discussed herein can be applicable to medical systems, scientific instrumentation, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which can be highly precise), and other digital-processing-based systems. Moreover, certain embodiments discussed above can be provisioned in digital signal processing technologies for medical imaging, patient monitoring, medical instrumentation, and home healthcare. This could include pulmonary monitors, accelerometers, heart rate monitors, pacemakers, etc. Other applications can involve automotive technologies for safety systems (e.g., stability control systems, driver assistance systems, braking systems, infotainment and interior applications of any kind). Furthermore, powertrain systems (for example, in hybrid and electric vehicles) can use high-precision data conversion products in battery monitoring, control systems, reporting controls, maintenance activities, etc. In yet other example scenarios, the teachings of the present disclosure can be applicable in the industrial markets that include process control systems that help drive productivity, energy efficiency, and reliability. In consumer applications, the teachings of the signal processing circuits discussed above can be used for image processing, auto focus, and image stabilization (e.g., for digital still cameras, camcorders, etc.). Other consumer applications can include audio and video processors for home theater systems, DVD recorders, and high-definition televisions. Yet other consumer applications can involve advanced touch screen controllers (e.g., for any type of portable media device). Hence, such technologies could readily part of smartphones, tablets, security systems, PCs, gaming technologies, virtual reality, simulation training, etc.

The specifications, dimensions, and relationships outlined herein have only been offered for purposes of example and teaching only. Each of these may be varied considerably without departing from the spirit of the present disclosure, or the scope of the appended claims. The specifications apply only to non-limiting examples and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular processor and/or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Further the various circuitry configurations described above can be replaced, substituted, or otherwise modified to accommodate various design implementations that achieve the lock detection mechanisms described herein. Moreover, using complementary electronic devices, hardware, software, etc. can offer an equally viable option for implementing the teachings of the present disclosure.

Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, circuits, and elements of the FIGURES may be combined in various possible configurations, all of which are clearly within the broad scope of this Specification. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that the electrical circuits of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as potentially applied to a myriad of other architectures.

Further, note that references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment”, “example embodiment”, “an embodiment”, “another embodiment”, “some embodiments”, “various embodiments”, “other embodiments”, “alternative embodiment”, and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments. It is further noted that “coupled to” and “coupled with” are used interchangeably herein, and that references to a feature “coupled to” or “coupled with” another feature include any communicative coupling means, electrical coupling means, mechanical coupling means, other coupling means, or a combination thereof that facilitates the feature functionalities and operations described herein.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims. In order to assist the United States Patent and Trademark Office (USPTO) and, additionally, any readers of any patent issued on this application in interpreting the claims appended hereto, Applicant wishes to note that the Applicant: (a) does not intend any of the appended claims to invoke paragraph six (6) of 35 U.S.C. section 112 as it exists on the date of the filing hereof unless the words “means for” or “steps for” are specifically used in the particular claims; and (b) does not intend, by any statement in the specification, to limit this disclosure in any way that is not otherwise reflected in the appended claims.

In various implementations, a system is provided that can be part of any type of computer, which can further include a circuit board coupled to a plurality of electronic components. The system can include means for generating a level shifted clock signal, and means for steering the level shifted clock signal based on the data signal and the input clock signal to provide a level shifted version of the data signal. The ‘means for’ can also or alternatively include (but is not limited to) using any suitable component discussed herein, along with any suitable software, circuitry, hub, computer code, logic, algorithms, hardware, controller, interface, link, bus, communication pathway, etc. In various implementations, the system includes memory that includes instructions that when executed cause the system to perform any of the activities discussed herein. In various implementations, the various functions outlined herein may be implemented by logic encoded in one or more non-transitory and/or tangible media (for example, embedded logic provided in an application specific integrated circuit (ASIC), as digital signal processor (DSP) instructions, software (potentially inclusive of object code and source code) to be executed by a processor, or other similar machine, etc.).