Array substrate having integrated gate driver and method of fabricating the same

This application claims the benefit under 35 U.S.C. §119(a) of Korean Patent Application No. 10-2014-0096727, filed on Jul. 29, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

1. Technical Field

The present disclosure relates to an array substrate, and more particularly, to an array substrate having an integrated gate driver and a method of fabricating the same.

2. Discussion of the Related Art

Recently, liquid crystal display (LCD) devices have been in the spotlight as a next generation display device because the LCD device has high value added due to its low-power consumption and good portability.

The LCD device includes an array substrate where a plurality of thin film transistors (TFTs) are disposed, a color filter substrate and a liquid crystal layer between the array substrate and the color filter substrate. The LCD device displays an image using difference in refractive index according to optical anisotropy of the liquid crystal layer.

In recent years, an active-matrix LCD (AM-LCD) device where TFTs and pixel electrodes are arranged in matrix shapes has attracted much attention because of its high resolution and its high capability of embodying moving images.

Since amorphous silicon (a-Si) is formed through a low temperature process, an insulating substrate of a low cost may be adopted for amorphous silicon. As a result, the TFTs of the array substrate may be formed using amorphous silicon.

The LCD device includes a liquid crystal panel displaying an image, a backlight unit supplying a light to the liquid crystal panel and a driving unit supplying signals and power to the liquid crystal panel. The driving unit includes a printed circuit board (PCB). The PCB is classified into a gate PCB connected to a gate line of the liquid crystal panel and a data PCB connected to a data line of the liquid crystal panel. The gate PCB and the data PCB may be attached to a gate pad and a data pad, respectively, on the liquid crystal panel through a tape carrier package (TCP). The gate pad connected to the gate line is formed on an edge portion of the liquid crystal panel and the data pad connected to the data line is formed on another edge portion of the liquid crystal panel.

Since the driving unit includes the gate PCB and the data PCB attached to the gate pad and the data pad, respectively, a volume and a weight of the LCD device increase. To lessen the above drawbacks, a gate in panel (GIP) type LCD device where a gate driver is formed in the liquid crystal panel and a single PCB is attached to the liquid crystal panel has been suggested.

In the GIP type LCD device, the gate driver is formed together with the array substrate. In addition, the gate driver integrated in the array substrate includes a shift register and the shift register includes a plurality of stages connected in cascade.

FIG. 1 is a view showing an array substrate for a gate in panel type liquid crystal display device according to the related art.

In FIG. 1 , an array substrate for a gate in panel (GIP) type liquid crystal display (LCD) device includes an active area AA and a gate circuit area GCA. A plurality of gate lines GL 1 to GLn and a plurality of data lines DL 1 to DLm are formed in the active area AA, and a gate driver is formed in the gate circuit area GCA. The gate driver includes a shift register and the shift register includes a plurality of stages ST 1 to STn. The plurality of stages ST 1 to STn correspond to the plurality of gate lines GL 1 to GLn.

An output terminal of the present stage is connected to an input terminal of the next stage so that an output signal of the present stage can start operation of the next stage. In addition, the output terminal of each stage is connected to the gate line GL 1 to GLn to supply the output signal to the active area AA. Accordingly, the output signal of each stage is supplied to the gate line GL 1 to GLn and the next stage. Since the first stage ST 1 does not have the previous stage, a start pulse SP is supplied to the first stage ST 1 to start operation of the first stage ST 1 .

First and second clocks having a high level pulse are sequentially supplied to each stage through first and second clock lines CL 1 and CL 2 outside the gate driver. In addition, the output signals of the shift register are sequentially transmitted from the plurality of stages ST 1 to STn to the plurality of gate lines GL 1 to GLn.

Recently, it has been required to reduce a bezel area corresponding to a non-display region for a light weight and a thin profile with a slim design of the LCD device. In the GIP type LCD device according to the related art, since the plurality of clock lines are disposed outside the gate driver, there is a limit to obtain a narrow bezel.

Embodiments of the present disclosure relate to an array substrate having an integrated gate driver and a method of fabricating the array substrate. Accordingly, one exemplary embodiment is directed to an array substrate that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

One exemplary embodiment is an array substrate having an integrated gate driver, where a narrow bezel is obtained, and a method of fabricating the array substrate.

In addition, one exemplary embodiment is an array substrate having an integrated gate driver, where moisture penetrating into the gate driver is blocked so that deterioration can be is prevented, and a method of fabricating the array substrate.

Advantages and features of the disclosure will be set forth in part in the description, which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the disclosure. Other advantages and features of the embodiments herein may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve other advantages and features in accordance with the purpose according to one aspect of the disclosure, one exemplary embodiment is an array substrate including: a substrate including an active area and a gate circuit area; a gate connecting line on the substrate in the gate circuit area; a gate insulating layer on the gate connecting line; an active pattern on the gate insulating layer, the active pattern spaced apart from the gate connecting line; a source connecting line and a pixel pattern sequentially disposed on the active pattern; an interlayer insulating layer and an organic pattern sequentially disposed on the gate insulating layer, the interlayer insulating layer and the organic pattern spaced apart from the source connecting line; a first passivation layer on the organic pattern, the first passivation layer and the gate insulating layer having a first contact hole exposing the gate connecting line, and the first passivation layer having a second contact hole exposing the pixel pattern; and a conductive pattern on the first passivation layer, the conductive pattern connected to the gate connecting line through the first contact hole and connected to the pixel pattern through the second contact hole.

In another aspect, one exemplary embodiment is a method of fabricating an array substrate including: forming a gate connecting line on a substrate in a gate circuit area; forming a gate insulating layer on the gate connecting line; forming an active pattern on the gate insulating layer, the active pattern spaced apart from the gate connecting line; forming a source connecting line and a pixel pattern sequentially on the active pattern; forming an interlayer insulating layer and an organic pattern sequentially on the gate insulating layer, the interlayer insulating layer and the organic pattern spaced apart from the source connecting line; forming a first passivation layer on the organic pattern, the first passivation layer and the gate insulating layer having a first contact hole exposing the gate connecting line, and the first passivation layer having a second contact hole exposing the pixel pattern; and forming a conductive pattern on the first passivation layer, the conductive pattern connected to the gate connecting line through the first contact hole and connected to the pixel pattern through the second contact hole.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the embodiments as claimed.

The accompanying drawings, which are included to provide a further understanding of the disclosure, are incorporated in and constitute a part of this specification, illustrate implementations of the disclosure and together with the description serve to explain the principles of embodiments of the disclosure.

FIG. 1 is a view showing an array substrate for a gate in panel type liquid crystal display device according to the related art.

FIG. 2 is a view showing an array substrate for a gate in panel type liquid crystal display device according to a first embodiment of the present disclosure.

FIG. 3 is a cross-sectional view showing an array substrate for a gate in panel type liquid crystal display device according to a first embodiment of the present disclosure.

FIG. 4 is a cross-sectional view showing an array substrate for a gate in panel type liquid crystal display device according to a second embodiment of the present disclosure.

FIGS. 5A to 5F are cross-sectional views showing a method of fabricating an array substrate for a gate in panel type liquid crystal display device according to a second embodiment of the present disclosure.

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the following description, when a detailed description of well-known functions or configurations related to this document is determined to unnecessarily cloud a gist of an embodiment of the disclosure, the detailed description thereof will be omitted. The progression of processing steps and/or operations described is an example; however, the sequence of steps and/or operations is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps and/or operations necessarily occurring in a certain order. Like reference numerals designate like elements throughout. Names of the respective elements used in the following explanations are selected only for convenience of writing the specification and may be thus different from those used in actual products.

FIG. 2 is a view showing an array substrate for a gate in panel type liquid crystal display device according to a first embodiment of the present disclosure.

In FIG. 2 , an array substrate includes an active area AA at a central portion thereof and a gate circuit area GCA at an edge portion thereof. A plurality of gate lines GL 1 to GLn and a plurality of data lines DL 1 to DLm are formed in the active area AA to display an image, and a gate driver is formed in the gate circuit area GCA to generate a plurality of gate signals. The plurality of gate lines GL 1 to GLn cross the plurality of data lines DL 1 to DLm to define a pixel region. The gate driver integrated in the array substrate includes a shift register and the shift register includes a plurality of stages ST 1 to STn connected in cascade. Although not shown, each of the plurality of stages ST 1 to STn may include a plurality of driving thin film transistors (TFTs) and the pixel regions may include a plurality of pixel TFTs. The plurality of driving TFTs and the plurality of pixel TFTs are formed at the same time. The plurality of stages ST 1 to STn may correspond to the plurality of gate lines GL 1 to GLn.

An output terminal of the present stage is connected to an input terminal of the next stage so that an output signal of the present stage can start operation of the next stage. In addition, the output terminal of each stage ST 1 to STn is connected to the gate line GL 1 to GLn to supply the output signal to the active area AA of the array substrate. Accordingly, the output signal of each stage ST 1 to STn is supplied to the gate line GL 1 to GLn and the next stage. Since the first stage ST 1 does not have the previous stage, a start pulse SP is supplied to the first stage ST 1 to start operation of the first stage ST 1 .

First and second clocks having a high level pulse are sequentially supplied to each stage through first and second clock lines CL 1 and CL 2 over the gate driver. Although the first and second clocks are inputted to each stage ST 1 to STn in the first embodiment, three or more clocks may be inputted to each stage ST 1 to STn in another embodiment. Accordingly, the output signals are sequentially transmitted from the plurality of stages ST 1 to STn to the plurality of gate lines GL 1 to GLn.

In the array substrate according to a first embodiment, since the plurality of clock lines CL 1 and CL 2 for transmitting the plurality of clock signals are formed over the gate driver, a bezel area of a non-display region is reduced as compared with the array substrate according to the related art where the plurality of clock lines are formed outside the gate driver. As a result, an LCD having a light weight and a thin profile with a slim design is obtained.

FIG. 3 is a cross-sectional view showing an array substrate for a gate in panel type liquid crystal display device according to a first embodiment of the present disclosure.

In FIG. 3 , a substrate 101 includes an active area AA for displaying an image and a gate circuit area GCA for generating a plurality of gate signals. In the active area AA, a gate electrode 116 a and a gate line connected to the gate electrode 116 a are formed in each pixel region on the substrate 101 , and a gate insulating layer 120 is formed on the gate electrode 116 a and the gate line. An active layer 123 a is formed on the gate insulating layer 120 over the gate electrode 116 a , and source and drain electrodes 125 a and 125 b and a data line connected to the source electrode 125 a are formed on the active layer 123 a . The active layer 123 a may be formed of intrinsic amorphous silicon (a-Si:H). The source and drain electrodes 125 a and 125 b are spaced apart from each other to correspond to both sides of the active layer 123 a . The gate electrode 116 a , the gate insulating layer 120 , the active layer 123 a , the source electrode 125 a and the drain electrode 125 b constitute the pixel TFT. An interlayer insulating layer 130 is formed in each pixel region on the source and drain electrodes 125 a and 125 b , and a pixel electrode 145 a is formed on the interlayer insulating layer 130 . The pixel electrode 145 a may be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO). The interlayer insulating layer 130 has a drain contact hole exposing the drain electrode 125 b , and the pixel electrode 145 a is connected to the drain electrode 125 b through the drain contact hole. A first passivation layer 150 is formed on the pixel electrode 145 a.

In the gate circuit area GCA, a gate connecting line 116 b is formed on the substrate 101 , and the gate insulating layer 120 is formed on the gate connecting line 116 b . The gate connecting line 116 b may have the same layer and the same material as the gate electrode 116 a . An active pattern 123 b , a source connecting line 125 c and a pixel pattern 145 b are sequentially formed on the gate insulating layer 120 . The active pattern 123 b is spaced apart from the gate connecting line 116 b . The active pattern 123 b may have the same layer and the same material as the active layer 123 a . The source connecting line 125 c may have the same layer and the same material as the source and drain electrodes 125 a and 125 b . In addition, the pixel pattern 145 b may have the same layer and the same material as the pixel electrode 145 a . The source connecting line 125 c and the pixel pattern 145 b cover a top surface and a side surface of the active pattern 123 b.

The interlayer insulating layer 130 is formed on the gate insulating layer 120 and an organic insulating pattern 140 is formed on the interlayer insulating layer 130 . In addition, the first passivation layer 150 is formed on the organic insulating pattern 140 . Although not shown, a gate driver including a shift register may be formed under the organic insulating pattern 140 . The interlayer insulating layer 130 and the organic insulating pattern 140 have an opening exposing the source connecting line 125 c , and the pixel pattern 145 b is formed directly on the source connecting line 125 c through the opening. The organic insulating pattern 140 may be formed of an organic insulating material such as photo acryl and benzocyclobutene (BCB). The interlayer insulating layer 130 and the organic insulating pattern 140 are spaced apart from the source connecting line 125 b . A conductive pattern 155 is formed on the first passivation layer 150 over the organic insulating pattern 140 , and a second passivation layer 160 is formed on the conductive pattern 155 . The conductive pattern 155 may be formed of a metallic material such as aluminum (Al) and copper (Cu) to prevent a signal delay. Alternatively, the conductive pattern 155 may be formed of a transparent conductive material such as ITO and IZO. In addition, the conductive pattern 155 may be electrically separated from the gate driver due to the organic insulating pattern 140 . A common layer 170 is formed on the second passivation layer 160 . The common layer 170 may functions as a jumping line for connecting conducting lines of different layers such as the gate connecting line 116 b , the pixel pattern 145 b and the conductive pattern 155 .

The gate insulating layer 120 , the first passivation layer 150 and the second passivation layer 160 have a first contact hole CH 1 exposing the gate connecting line 116 b . In addition, the first passivation layer 150 and the second passivation layer 160 have a second contact hole CH 2 exposing the pixel pattern 145 b , and the second passivation layer 160 has a third contact hole CH 3 exposing the conductive pattern 155 . The common layer 170 is connected to the gate connecting line 116 b through the first contact hole CH 1 , to the pixel pattern 145 b through the second contact hole CH 2 and to the conductive pattern 155 through the third contact hole CH 3 .

In the array substrate according to the first embodiment, the conductive pattern 155 may function as the plurality of clock lines CL 1 and CL 2 (of FIG. 2 ) and the plurality of clock signals are applied to the conductive pattern 155 . Since the conductive pattern 155 is formed over the gate driver, an LCD device having a narrow bezel is obtained.

However, since the common layer 170 is formed as a top layer of the substrate 101 without a protecting layer, exterior moisture may penetrate into contact portions between the common layer 170 and the gate connecting line 116 b , between the pixel pattern 145 b and the source connecting line 125 c and between the common layer 170 and the conductive pattern 155 . For example, the exterior moisture may penetrate into the contact portions under high temperature and high humidity condition such as a temperature of about 60° C. and a humidity of about 90%. As a result, the contact portions may be deteriorated due to the moisture.

In addition, when the LCD device has an in-cell touch type where a plurality of touch scan lines and a plurality of touch sensing lines are formed on the array substrate, the conductive pattern 155 may function as the plurality of touch scan lines and a plurality of touch scan signals may be applied to the conductive pattern 155 . In the in-cell touch type LCD device, the exterior moisture may cause deterioration of the contact portions.

To solve the above problems, a second embodiment is suggested.

FIG. 4 is a cross-sectional view showing an array substrate for a gate in panel type liquid crystal display device according to a second embodiment of the present disclosure.

In FIG. 4 , a substrate 201 includes an active area AA for displaying an image and a gate circuit area GCA for generating a plurality of gate signals. In the active area AA, a gate electrode 216 a and a gate line connected to the gate electrode 216 a are formed in each pixel region on the substrate 201 , and a gate insulating layer 220 is formed on the gate electrode 216 a and the gate line. An active layer 223 a is formed on the gate insulating layer 220 over the gate electrode 216 a , and source and drain electrodes 225 a and 225 b and a data line connected to the source electrode 225 a are formed on the active layer 223 a . The active layer 223 a may be formed of intrinsic amorphous silicon (a-Si:H). The source and drain electrodes 225 a and 225 b are spaced apart from each other at opposite sides of the active layer 223 a . The gate electrode 216 a , the gate insulating layer 220 , the active layer 223 a , the source electrode 225 a and the drain electrode 225 b constitute the pixel TFT. An interlayer insulating layer 230 is formed in each pixel region on the source and drain electrodes 225 a and 225 b , and a pixel electrode 245 a is formed on the interlayer insulating layer 230 . The pixel electrode 245 a may be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO). The interlayer insulating layer 230 has a drain contact hole exposing the drain electrode 225 b , and the pixel electrode 245 a is connected to the drain electrode 225 b through the drain contact hole. A first passivation layer 250 is formed on the pixel electrode 245 a.

In the gate circuit area GCA, a gate connecting line 216 b is formed on the substrate 201 , and the gate insulating layer 220 is formed on the gate connecting line 216 b . The gate connecting line 216 b may have the same layer and the same material as the gate electrode 216 a . An active pattern 223 b , a source connecting line 225 c and a pixel pattern 245 b are sequentially formed on the gate insulating layer 220 . The active pattern 223 b is spaced apart from the gate connecting line 216 b . The active pattern 223 b may have the same layer and the same material as the active layer 223 a . The source connecting line 225 c may have the same layer and the same material as the source and drain electrodes 225 a and 225 b . In addition, the pixel pattern 245 b may have the same layer and the same material as the pixel electrode 245 a . The source connecting line 225 c and the pixel pattern 245 b cover a top surface and a side surface of the active pattern 223 b.

The interlayer insulating layer 230 is formed on the gate insulating layer 220 and an organic insulating pattern 240 is formed on the interlayer insulating layer 230 . In addition, the first passivation layer 250 is formed on the organic insulating pattern 240 . Although not shown, a gate driver including a shift register may be formed under the organic insulating pattern 240 . The interlayer insulating layer 230 and the organic insulating pattern 240 have an opening exposing the source connecting line 225 c , and the pixel pattern 245 b is formed directly on the source connecting line 225 c through the opening. The organic insulating pattern 240 may be formed of an organic insulating material such as photo acryl and benzocyclobutene (BCB). The interlayer insulating layer 230 and the organic insulating pattern 240 are spaced apart from the source connecting line 225 b . A conductive pattern 255 is formed on the first passivation layer 250 over the organic insulating pattern 240 , and a second passivation layer 260 is formed on the conductive pattern 255 . The conductive pattern 255 may be formed of a metallic material such as aluminum (Al) and copper (Cu) to prevent a signal delay. Alternatively, the conductive pattern 255 may be formed of a transparent conductive material such as ITO and IZO. In addition, the conductive pattern 255 may be electrically separated from the gate driver due to the organic insulating pattern 240 .

The gate insulating layer 220 and the first passivation layer 250 have a first contact hole CH 1 exposing the gate connecting line 216 b , and the first passivation layer 250 has a second contact hole CH 2 exposing the pixel pattern 245 b . The conductive pattern 255 is connected directly to the gate connecting line 216 b through the first contact hole CH 1 and directly to the pixel pattern 245 b through the second contact hole CH 2 .

In the array substrate according to the second embodiment, the conductive pattern 255 may function as the plurality of clock lines CL 1 and CL 2 (of FIG. 2 ) and the plurality of clock signals are applied to the conductive pattern 255 . In addition, the conductive pattern 255 may function as a jumping line for connecting conducting lines of different layers such as the gate connecting line 216 b , the pixel pattern 245 b and the conductive pattern 255 . Since the conductive pattern 255 is formed over the gate driver, an LCD device having a narrow bezel is obtained.

Further, since the second passivation layer 260 is formed on the conductive pattern 255 , exterior moisture may not penetrate into contact portions between the conductive pattern 255 and the gate connecting line 216 b , between the pixel pattern 245 b and the source connecting line 225 c and between the conductive pattern 255 and the conductive pattern 255 . For example, the exterior moisture may not penetrate into the contact portions even under high temperature and high humidity condition such as a temperature of about 60° C. and a humidity of about 90%. As a result, deterioration of the contact portions due to the moisture is reduced.

FIGS. 5A to 5F are cross-sectional views showing a method of fabricating an array substrate for a gate in panel type liquid crystal display device according to a second embodiment of the present disclosure.

In FIG. 5A , a gate electrode 216 a and a gate line connected to the gate electrode 216 a are formed a substrate 201 in an active area AA on and a gate connecting line 216 b is formed on the substrate 201 in a gate circuit area GCA by depositing and patterning a first metallic material through a photolithographic process. The first metallic material may include at least one of aluminum (Al), aluminum alloy, silver (Ag), silver alloy, molybdenum (Mo), molybdenum alloy, chromium (Cr), titanium (Ti) and tantalum (Ta). The gate electrode 216 a , the gate line and the gate connecting line 216 b may have a single-layered structure or a multiple-layered structure.

Next, a gate insulating layer 220 is formed on the gate electrode 216 a , the gate line and the gate connecting line 216 b by depositing a first insulating material. Next, an active layer 223 a is formed on the gate insulating layer 220 in the active area AA and an active pattern 223 b is formed on the gate insulating layer 220 in the gate circuit area GCA by depositing and patterning amorphous silicon through a photolithographic process. The active pattern 223 b is spaced apart from the gate connecting line 216 b.

Next, source and drain electrodes 225 a and 225 b are formed on the active layer 223 a in the active area AA and a source connecting line 225 c is formed on the gate insulating layer in the gate circuit area GCA by depositing and patterning a second metallic material through a photolithographic process. The source connecting line 225 c wraps a top surface and a side surface of the active pattern 223 b . The source and drain electrodes 225 a and 225 b are spaced apart from each other to correspond to both sides of the active layer 223 a . The second metallic material may include at least one of aluminum (Al), aluminum alloy, silver (Ag), silver alloy, molybdenum (Mo), molybdenum alloy, chromium (Cr), titanium (Ti) and tantalum (Ta). The source electrode 225 a , the drain electrode 225 b and the source connecting line 225 c may have a single-layered structure or a multiple-layered structure. The gate electrode 216 a , the gate insulating layer 220 , the active layer 223 a , the source electrode 225 a and the drain electrode 225 b constitute a pixel TFT.

In FIG. 5B , an interlayer insulating layer 230 is formed on the TFT in the active area AA and the interlayer insulating layer 230 and an organic insulating pattern 240 are sequentially formed on the gate insulating layer 220 in the gate circuit area GCA by depositing and patterning an inorganic insulating material and an organic insulating material through a photolithographic process. The interlayer insulating layer 230 and the organic insulating pattern 240 have a drain contact hole exposing the drain electrode 225 b in the active area AA, and the interlayer insulating layer 230 and the organic insulating pattern 240 have an opening exposing the source connecting line 225 c in the gate circuit area GCA. The inorganic insulating material may include one of silicon nitride (SiNx) and silicon oxide (SiO 2 ), and the organic insulating material may include one of photo acryl and benzocyclobutene (BCB).

In FIG. 5C , after the organic insulating pattern 240 of the active area AA is removed, a pixel electrode 245 a is formed on the interlayer insulating layer 230 in the active area AA and a pixel pattern 245 b is formed on the source connecting line 225 c by depositing and patterning a transparent conductive material through a photolithographic process. The pixel electrode 245 a is connected to the drain electrode 225 b through the drain contact hole, and the pixel pattern 245 b wraps a top surface and a side surface of the source connecting line 225 c through the opening. The transparent conductive material may include one of ITO and IZO.

In FIG. 5D , a first passivation layer 250 is formed on the pixel electrode 245 a in the active area AA and on the pixel pattern 245 b in the gate circuit area GCA by depositing and patterning a second insulating material through a photolithographic process. The gate insulating layer 220 and the first passivation layer 250 have a first contact hole CH 1 exposing the gate connecting line 216 b , and the first passivation layer 250 has a second contact hole CH 2 exposing the pixel pattern 245 b . The second insulating material may include one of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiO 2 ) and an organic insulating material such as photo acryl and benzocyclobutene (BCB).

In FIG. 5E , a conductive pattern 255 is formed on the first passivation layer 250 in the gate circuit area GCA by depositing and patterning a third metallic material through a photolithographic process. The conductive pattern 255 is connected directly to the gate connecting line 216 b through the first contact hole CH 1 and directly to the pixel pattern 245 b through the second contact hole CH 2 . The third metallic material may include one of a metallic material such as aluminum (Al) and copper (Cu) and a transparent conductive material such as ITO and IZO. Since the conductive pattern 255 functioning as a clock line and a jumping line is formed over the gate driver, an LCD device having a narrow bezel is obtained.

In FIG. 5F , a second passivation layer 260 is formed on the conductive pattern 255 in the gate circuit area GCA by depositing a third insulating material. The third insulating material may include one of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiO 2 ) and an organic insulating material such as photo acryl and benzocyclobutene (BCB). Since the second passivation layer 260 is formed on the conductive pattern 255 , exterior moisture may not penetrate into contact portions between the conductive pattern 255 and the gate connecting line 216 b , between the pixel pattern 245 b and the source connecting line 225 c and between the conductive pattern 255 and the conductive pattern 255 . For example, the exterior moisture may not penetrate into the contact portions even under high temperature and high humidity condition such as a temperature of about 60° C. and a humidity of about 90%. As a result, deterioration of the contact portions due to the moisture is reduced.

Consequently, in an array substrate having an integrated gate driver and a method of fabricating the array substrate according to the present disclosure, in which the conductive pattern 255 functioning as a clock line and a jumping line is formed over the gate driver, a liquid crystal display device having a narrow bezel is obtained. In addition, since the conductive pattern 255 is connected directly to the gate connecting line 216 b and the pixel pattern 245 b and the second passivation layer 260 is formed on the conductive pattern 255 , moisture penetrating into the contact portions is blocked and deterioration due to the moisture is reduced.

A number of examples have been described above. Nevertheless, it will be understood that various modifications may be made. For example, suitable results may be achieved if the described techniques are performed in a different order and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Accordingly, other implementations are within the scope of the following claims.