Power circuit and electronic device utilizing the same

The subject matter herein generally relates to a power circuit and an electronic device utilizing the power circuit.

Some electronic devices use a dual output power supply as the power source. However, the double output power supply has two similar power connectors, which is troublesome to operate for users.

Therefore, there is need for improvement in the art.

Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.

FIG. 1 is a circuit diagram of an example embodiment of a power circuit.

FIG. 2 is a block diagram of an embodiment of the power circuit of FIG. 1 , together with an electronic device.

It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.

Several definitions that apply throughout this disclosure will now be presented.

The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently coupled or releasably coupled. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.

The disclosure will now be described in relation to a power circuit.

FIGS. 1 and 2 illustrate a circuit diagram of an example embodiment of a power circuit 100 applied in an electronic device 200 . The electronic device 200 can be a power supply unit or a motherboard.

In the embodiment, the power circuit 100 includes a control unit 10 , a voltage transform unit 20 , an input terminal Vin, and an output terminal Vout. In this embodiment, the power circuit 100 receives a first voltage or a second voltage from a dual output power supply through the input terminal Vin, and outputs an output voltage for other electronic components.

The control unit 10 includes a voltage division unit 11 , a first switch unit 12 , a second switch unit 13 , and a third switch unit 14 . The voltage division unit 11 includes resistors R 1 , R 2 . The first switch unit 12 includes an electronic switch Q 1 and a resistor R 3 . The second switch unit 13 includes an electronic switch Q 2 and resistors R 4 , R 5 , R 6 . The third switch unit 14 includes electronic switches Q 3 , Q 4 , resistors R 7 , R 8 , R 9 , and a capacitor C 1 .

In this embodiment, the electronic switches Q 1 , Q 2 are n-channel metal oxide semiconductor field-effect transistors (MOSFETs). The electronic switch Q 3 is a NPN bipolar junction transistor (BJT) . The electronic switch Q 4 is a p-channel metal oxide semiconductor field-effect transistor (MOSFET). A first terminal of the resistor R 1 is coupled to the input terminal Vin. A second terminal of the resistor R 1 is coupled to a first terminal of the resistor R 2 . A second terminal of the resistor R 2 is grounded. A gate of the MOSFET Q 1 is coupled to a node A between the resistors R 1 and R 2 . A source of MOSFET Q 1 is grounded. A drain of the MOSFET Q 1 is coupled to the input terminal Vin through the resistor R 3 . The drain of the MOSFET Q 1 is also coupled to a gate of the MOSFET Q 2 through the resistor R 4 . A source of the MOSFET Q 2 is grounded. A drain of the MOSFET Q 2 is coupled to the input terminal Vin through the resistor R 5 . The drain of the MOSFET Q 2 is also grounded through the resistor R 6 . A base of the BJT Q 3 is coupled to the drain of the MOSFET Q 1 through the resistor R 7 . An emitter of the BJT Q 3 is grounded. A collector of the BJT Q 3 is coupled to a gate of MOSFET Q 4 through the resistor R 8 . The gate of the MOSFET Q 4 is also coupled to the input terminal Vin through the resistor R 9 . The capacitor C 1 is coupled to the resistors R 9 in parallel. A source of the MOSFET Q 4 is coupled to the input terminal Vin. A drain of the MOSFET Q 4 is coupled to the output terminal Vout.

The voltage transform unit 20 includes a pulse-width modulation (PWM) chip U 1 , electronic switches Q 5 , Q 6 , an inductor L, capacitors C 2 , C 3 , C 4 , resistors R 10 , R 11 , R 12 , and a diode D 1 . The electronic switches Q 5 , Q 6 are n-channel metal oxide semiconductor field-effect transistors (MOSFETs). A power pin VCC of the PWM chip U 1 is coupled to the input terminal Vin, and is coupled to a bootstrap pin BOOST of the PWM chip U 1 through the diode D 1 . An anode of the diode D 1 is coupled to the power pin VCC. A cathode of the diode D 1 is coupled to the bootstrap pin BOOST. The bootstrap pin BOOST is also coupled to a phase pin Phase of the PWM chip U 1 through the resistor R 10 and the capacitor C 2 . An enable pin EN of the PWM chip U 1 is coupled to the drain of the MOSFET Q 2 . A ground pin of the PWM chip U 1 is grounded. A high level driving pin Hgate of the PWM chip U 1 is coupled to a gate of the MOSFET Q 5 . A low level driving pin Lgate of the PWM chip U 1 is coupled to a gate of the MOSFET Q 6 . A drain of the MOSFET Q 5 is coupled to the input terminal Vin. A source of the MOSFET Q 5 is coupled to a drain of the MOSFET Q 6 . A source of the MOSFET Q 6 is grounded. The phase pin Phase is grounded through the inductor L, the resistors R 11 and R 12 . The phase pin Phase is also grounded through the inductor L and the capacitor C 4 . A node between the inductor L and the resistor R 11 is coupled to the output terminal Vout of the power circuit 100 . A feedback pin FB of the PWM chip U 1 is coupled to a node between the resistors R 11 and R 12 .

In this embodiment, the first and second voltages are 19 volts and 12Vs respectively, and the output voltage at the output terminal Vout is 12Vs. In other embodiments, the first voltage can be 24V.

In use, when the input terminal Vin receives the first voltage such as 19V, the node A between the resistors R 1 and R 2 outputs a divided voltage to the gate of the MOSFET Q 1 . The MOSFET Q 1 is turned on, and the MOSFET Q 2 is turned off. The enable pin EN of the PWM chip U 1 receives a digital high level signal. The PWM chip U 1 starts operating, and controls the MOSFETs Q 5 and Q 6 to turn on alternately. The output terminal Vout outputs 12V voltage.

When the input terminal Vin receives the second voltage (12Vs), the node A between the resistors R 1 and R 2 outputs a divided voltage to the gate of the MOSFET Q 1 . The MOSFET Q 1 is turned off. The MOSFETs Q 2 , Q 4 , and BJT Q 3 is turned on. The enable pin EN of the PWM chip U 1 receives a digital low level signal. The voltage transform unit 20 does not operate. The output terminal Vout receives and outputs the 12Vs voltage from the input terminal Vin through the MOSFET Q 4 .

Therefore, the power circuit 100 can receive the first voltage (19V) or the second voltage (12V) through the input terminal functioning as a power supply port of the electronic device, and outputs the output voltage (12V) to other electronic components. The power circuit 10 can not only save the power supply port of the electronic device, but also can prevent damage to the components due to improper connecting power connectors.

While the disclosure has been described by way of example and in terms of the embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.