Fault-tolerance through silicon via interface and controlling method thereof

This application claims the priority benefit of Taiwan application serial no. 103139200, filed on Nov. 12, 2014. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The present disclosure is related to a fault-tolerance through silicon via interface and the corresponding controlling method.

Three-dimensional (3-D) integration is one of important technologies for future integrated circuit design. Semiconductor chips are stacked together and their signals are connected vertically using through silicon vias (TSVs). Comparing with packaging technologies that rely on bond wires, such as system in package (SiP), TSVs provide shorter interconnections between stacked chips, with lower power consumption and higher signal transmission speed. Since TSVs have a much finer pitch than that of bond wires used in SiP, the limitation in available interconnections and the data transmission bottleneck in SiP can be alleviated.

Three-dimensional (3-D) integration technology has been widely used, especially in memory related designs to increase the storage capacity. Three-dimensional random access memory (3-D RAM), which vertically stacks a plurality of memory chips, could apply the TSV interface to access the data of its memory arrays from outside.

With high data bandwidth and large storage capacity targeting at high-performance computing, manufacturing yield becomes a critical issue to make the 3-D RAM practical and mass producible. Comparing with traditional two-dimensional random access memory (2-D RAM) design, the 3-D RAM requires more considerations to sustain a high yield rate. A large number of TSV paths connect the data, address, command, and control signals of the stacked chips from the bottom layer to the top. To guarantee the operations of 3-D RAM, not only each layer of the stacked chips should work properly, but also the TSV paths among layers should be fault-free.

In one of the exemplary embodiments, the present disclosure is directed to a fault-tolerance through silicon via (TSV) interface. The interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers includes K memory arrays, and each of the data access path sets includes a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in one of the data access path sets, the processing unit provides at least two different access configurations to tolerate the fault. In each of the access configurations, μ out of M data access path sets, where 0<μ<M, are enabled to access one of the corresponding memory layers with all K memory arrays.

In one of the exemplary embodiments, the present disclosure is directed to a fault-tolerance TSV interface controlling method. The method provides a 3-D RAM with N memory layers and M data access path sets, and each of the memory layers includes K memory arrays, and each of the data access path sets includes a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface is disposed on each of the memory layers. The method provides at least two different access configurations for the purpose of fault tolerance. In each of the access configurations, μ out of M data access path sets, where 0<μ<M, are enabled to access one of the corresponding memory layers with all K memory arrays.

In one of the exemplary embodiments, the present disclosure is directed to a fault-tolerance TSV interface controlling method. The method provides a 3-D RAM with N memory layers and M data access path sets, and each of the memory layers includes K memory arrays, and each of the data access path sets includes a plurality of TSV paths connecting to the memory layers. The method provides at least two different fault-tolerance access configurations, wherein the access of the memory layers is through a proper arrangement of the access configurations to avoid the fault.

In order to make the aforementioned features and advantages of the present disclosure comprehensible, exemplary embodiments accompanied with figures are described in detail below. It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the disclosure as claimed.

It should be understood, however, that this summary may not contain all of the aspect and embodiments of the present disclosure and is therefore not meant to be limiting or restrictive in any manner. Also the present disclosure would include improvements and modifications which are obvious to one skilled in the art.

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

FIG. 1 illustrates an exemplary embodiment of the three-dimensional random access memory and fault-tolerance through silicon via interface.

FIG. 2 illustrates an exemplary embodiment of the fault-tolerance through silicon via interface.

FIG. 3A and FIG. 3B are flow charts that illustrate exemplary embodiments of the fault-tolerance through silicon via interface controlling method.

FIG. 3C illustrates an exemplary embodiment of the fault-tolerance through silicon via interface providing two normal access configurations and six fault-tolerance access configurations.

FIG. 4 illustrates an exemplary embodiment of a 3-D RAM adopting two fault-tolerance access configurations when a fault occurs in one of the data access path sets.

FIG. 5 illustrates an exemplary embodiment of a 3-D RAM adopting four fault-tolerance access configurations when two faults occur in two of the data access path sets.

FIG. 6 illustrates an exemplary embodiment of a 3-D RAM adopting two fault-tolerance access configurations when two faults occur in two of the data access path sets.

FIG. 7 illustrates an exemplary embodiment of a 3-D RAM adopting two fault-tolerance access configurations in the other two memory layers when two faults occur in two of the data access path sets.

FIG. 1 illustrates an exemplary embodiment of a 3-D RAM, namely, RM, with a fault-tolerance TSV interface 100 . On the left, a cross-sectional view of the 3-D RAM is with M data access path sets which are labeled as DAPS 1 , DAPS 2 , . . . DAPS M . On the right, the 3-D RAM consists of N memory layers ML 1 , ML 2 , . . . , ML N and M data access path sets DAPS 1 , DAPS 2 , . . . , DAPS M . Each memory layer contains K memory arrays MA 1 , MA 2 , . . . , MA K . Each data access path set includes a plurality of TSV paths. The plurality of TSV paths connect to the memory layers ML 1 , ML 2 , . . . , ML N . When normal access configurations are adopted to access the 3-D RAM, all M data access path sets DAPS 1 , DAPS 2 , . . . , DAPS M are enabled to access the K memory arrays MA 1 , MA 2 , . . . , MA K in a single memory layer. For the other memory layers not being accessed, the data access path sets connecting to them are disabled. Because the TSVs paths connect to all memory layers, every memory array in each memory layer could be accessed. However, all TSV paths must be fault-free. As the number of the stacked chips or the access data width increases, maintaining all TSV paths fault-free becomes a severe issue. The yield of the 3-D RAM will drop drastically if we have no counterplot.

FIG. 2 illustrates an exemplary embodiment of a fault-tolerance TSV interface 100 . The interface 100 includes a path controlling unit 110 , a processing unit 120 , a memory controlling unit 130 , and a selection unit 140 . The path controlling unit 110 detects and controls the data access path sets DAPS 1 , DAPS 2 , . . . , DAPS M connecting to the corresponding memory layer according to the selected configuration. The processing unit 120 plans and executes the related setting of the configurations in the fault-tolerance TSV interface 100 . The memory controlling unit 130 controls the activation of the memory arrays MA 1 , MA 2 , . . . , MA K according to the selected configuration in the corresponding memory layer. The selection unit 140 selects the data access of each memory array according to the selected configuration in the corresponding memory layer. In an exemplary embodiment of a fault-tolerance TSV interface 100 , the function of the selection unit 140 could be incorporated into the memory controlling unit 130 . Furthermore, the function of the selection unit 140 could be chosen or modified according to the practical application. The path controlling unit 110 , the processing unit 120 , the memory controlling unit 130 , and the selection unit 140 could be a single chip, or an interposer, or a partial circuit in a chip.

When the path controlling unit 110 located in a memory layer detects is a fault among the data access path sets DAPS 1 , DAPS 2 , . . . , DAPS M , adopting normal access configurations fails to maintain a full robust data width to the memory array MA 1 , MA 2 , . . . , MA K in the memory layer of the 3-D RAM. In our exemplary embodiment, the processing unit 120 located in each memory layer provides a proper arrangement of fault-tolerance access configurations to access memory arrays MA 1 , MA 2 , . . . , MA K in memory layers ML 1 , ML 2 , . . . , ML N when a fault exists among the data access path sets DAPS 1 , DAPS 2 , . . . , DAPS M .

FIG. 3A and FIG. 3B are flow charts that illustrate two exemplary embodiments of the fault-tolerance TSV interface controlling methods. FIG. 3C assumes M=4 and K=4 of the 3-D RAM and illustrates an exemplary embodiment of a fault-tolerance TSV interface 100 providing two normal access configurations C 000 and C 001 , and six fault-tolerance access configurations C 010 , C 011 , C 100 , C 101 , C 110 and C 111 . The fault-tolerance TSV interface 100 in FIG. 2 could be operated with the controlling methods illustrated in FIG. 3A and FIG. 3B . A 3-D RAM as shown in FIG. 1 is provided in steps S 110 and S 210 . At least two fault-tolerance access configurations, as shown in FIG. 3C , are provided in steps S 120 and S 220 . In normal access configuration C 000 , all four data access path sets DAPS 1 , DAPS 2 , DAPS 3 , and DAPS 4 are disabled and the dashed cycles indicate their disconnections. In normal access configuration C 001 , all four data access path sets DAPS 1 , DAPS 2 , DAPS 3 , and DAPS 4 are enabled and the solid circles indicate their connections. The path controlling unit 110 and the memory controlling unit 130 is select data access path set DAPS 1 to access memory array MA 1 , data access path set DAPS 2 to access memory array MA 2 , data access path set DAPS 3 to access memory array MA 3 , and data access path set DAPS 4 to access memory array MA 4 , by the address sequence indexed by numbers 0, 1, 2, and 3. The same indices inside the memory arrays indicate the physical locations being accessed at the same time.

When the path controlling unit 110 detects any fault in the data access path sets DAPS 1 , DAPS 2 , DAPS 3 , and DAPS 4 , the processing unit 120 provides fault-tolerance access configurations C 010 , C 011 , C 100 , C 101 , C 110 and C 111 to support data access for the 3-D RAM. In FIG. 3C , we elaborate an exemplary embodiment of fault-tolerance TSV interface 100 providing six fault-tolerance access configurations C 010 , C 011 , C 100 , C 101 , C 110 , and C 111 . FIG. 4 assumes N=2, M=4, and K=4 of the 3-D RAM. We elaborate how the fault-tolerance access configurations C 010 and C 011 are adopted to access all memory arrays MA 1 , MA 2 , MA 3 , and MA 4 in memory layers ML 1 and ML 2 , and to maintain the access data width of the 3-D RAM in the presence of a fault in the data access path sets DAPS 1 , DAPS 2 , DAPS 3 , and DAPS 4 .

In fault-tolerance access configuration C 010 , the path controlling unit 110 enables two data access path sets DAPS 1 and DAPS 3 indicated by the solid circles and disables two data access path sets DAPS 2 and DAPS 4 indicated by the dashed circles. The path controlling unit 110 and the memory controlling unit 130 select DAPS 1 to access memory arrays MA 1 and MA 2 , and DAPS 3 to access memory arrays MA 3 and MA 4 , by the address sequence is indexed by numbers 0, 1, . . . , 7. The same indices inside the memory arrays indicate the physical locations being accessed at the same time.

In fault-tolerance access configuration C 011 , the path controlling unit 110 enables two data access path sets DAPS 2 and DAPS 4 indicated by the solid circles and disables two data access path sets DAPS 1 and DAPS 3 indicated by the dashed circles. The path controlling unit 110 and the memory controlling unit 130 select DAPS 2 to access memory arrays MA 2 and MA 1 , and DAPS 4 to access memory arrays MA 4 and MA 3 , by the address sequence indexed by numbers 0, 1, . . . , 7. The same indices inside the memory arrays indicate the physical locations being accessed at the same time.

In fault-tolerance access configuration C 100 , the path controlling unit 110 enables a data access path set DAPS 1 indicated by a solid circle and disables three data access path sets DAPS 2 , DAPS 3 , and DAPS 4 indicated by dashed circles. The path controlling unit 110 and the memory controlling unit 130 select DAPS 1 to access memory arrays MA 1 , MA 2 , MA 3 , and MA 4 , by the address sequence indexed by numbers 0, 1, . . . , 15.

In fault-tolerance access configuration C 101 , the path controlling unit 110 enables a data access path set DAPS 2 indicated by a solid circle and disables three data access path sets DAPS 1 , DAPS 3 , and DAPS 4 indicated by dashed circles. The path controlling unit 110 and the memory controlling unit 130 select DAPS 2 to access memory arrays MA 2 , MA 1 , MA 4 , and MA 3 , by the address sequence indexed by numbers 0, 1, . . . , 15.

In fault-tolerance access configuration C 110 , the path controlling unit 110 enables a data access path set DAPS 3 indicated by a solid circle and disables three data access path sets DAPS 1 , DAPS 2 , and DAPS 4 indicated by dashed circles. The path controlling unit 110 and the memory controlling unit 130 select DAPS 3 to access memory arrays MA 3 , MA 4 , MA 1 , and MA 2 , by the address sequence indexed by numbers 0, 1, . . . , 15.

In fault-tolerance access configuration C 111 , the path controlling unit 110 enables a data access path set DAPS 4 indicated by a solid circle and disables three data access path sets DAPS 1 , DAPS 2 , and DAPS 3 indicated by dashed circles. The path controlling unit 110 and the memory controlling unit 130 select DAPS 4 to access memory arrays MA 4 , MA 3 , MA 2 , and MA 1 , by the address sequence indexed by numbers 0, 1, . . . , 15.

In FIG. 2 , the above eight access configurations, composed of two normal access configurations C 000 and C 001 , and six fault-tolerance access configurations C 010 , C 011 , C 100 , C 101 , C 110 , and C 111 can be selected by a 3-bit control signal.

In FIG. 4 , a fault occurs in the data access path set DAPS 3 in the 3-D RAM. Fault-tolerance access configurations C 011 and C 010 are adopted in memory layers ML 1 and ML 2 , respectively, as normal access configuration C 001 fails to access ML 1 through DAPS 3 .

As shown on the right of FIG. 4 , memory layer ML 1 adopts the fault-tolerance access configuration C 011 to enable data access path sets DAPS 2 and DAPS 4 . The path controlling unit 110 and the memory controlling unit 130 select data access path set DAPS 2 to access memory arrays MA 2 and MA 1 , and data access path set DAPS 4 to access memory arrays MA 4 and MA 3 . Thus, all memory arrays MA 1 , MA 2 , MA 3 , and MA 4 of memory layer ML 1 can be accessed.

As shown on the left of FIG. 4 , memory layer ML 2 adopts the fault-tolerance access configuration C 010 to enable data access path sets DAPS 1 and DAPS 3 . The path controlling unit 110 and the memory controlling unit 130 select data access path set DAPS 1 to access memory arrays MA 1 and MA 2 , and data access path set DAPS 3 to access memory arrays MA 3 and MA 4 . Thus, all memory arrays MA 1 , MA 2 , MA 3 , and MA 4 of memory layer ML 2 can be accessed.

Through the above setting, the fault occurring in the data access path set DAPS 3 is avoided. There is no need to equip any redundant TSV for memory layers ML 1 and ML 2 , as ML 1 is accessed by DAPS 2 and DAPS 4 , while ML 2 is accessed by DAPS 1 and DAPS 3 . All data access path sets DAPS 1 , DAPS 2 , DAPS 3 , and DAPS 4 are active concurrently, and thus, a full data width of the 3-D RAM can still be maintained. If the fault occurs in the other data access path set, a similar setting can be operated accordingly.

FIG. 4 shows four memory arrays and four data access path sets. In one embodiment, the number of memory arrays can be K and the number of data access path sets can be M, where both K and M are natural numbers and are greater than one. In a fault-tolerance access configuration, μ data access path sets are enabled to access memory arrays, where μ is a natural number and 0<μ<M. The path controlling unit 110 and the memory controlling unit 130 select each data access path set to access K/μ memory arrays in each memory layer. The address sequence of the memory arrays or the physical locations in the memory arrays may be different from that in the embodiment of FIG. 3C .

In FIG. 5 , two faults occur in data access path sets DAPS 1 and DAPS 3 in the 3-D RAM. Fault-tolerance access configurations C 111 , C 101 , C 100 , and C 110 are adopted in memory layers ML 1 , ML 2 , ML 3 , and ML 4 , respectively, as normal access configuration C 001 fails to access ML 1 through DAPS 1 and to access ML 1 and ML 2 through DAPS 3 .

As shown on the upper right of FIG. 5 , memory layer ML 1 adopts fault-tolerance access configuration C 111 to enable data access path set DAPS 4 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 4 to access memory arrays on memory layer ML 1 , according to the address sequence MA 4 , MA 3 , MA 2 , and MA 1 .

As shown on the upper left of FIG. 5 , memory layer ML 2 adopts fault-tolerance access configuration C 101 to enable data access path set DAPS 2 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 2 to access memory arrays on memory layer ML 2 , according to is the address sequence MA 2 , MA 1 , MA 4 , and MA 3 .

As shown on the lower right of FIG. 5 , memory layer ML 3 adopts fault-tolerance access configuration C 100 to enable data access path set DAPS 1 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 1 to access memory arrays on memory layer ML 3 , according to the address sequence MA 1 , MA 2 , MA 3 , and MA 4 .

As shown on the lower left of FIG. 5 , memory layer ML 4 adopts fault-tolerance access configuration C 110 to enable data access path set DAPS 3 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 3 to access memory arrays on memory layer ML 4 , according to the address sequence MA 3 , MA 4 , MA 1 , and MA 2 .

Through the above setting, the two faults occurring in data access path sets DAPS 1 and DAPS 3 are avoided. There is no need to equip any redundant TSV for memory layers ML 1 , ML 2 , ML 3 , and ML 4 . The four memory layers ML 1 , ML 2 , ML 3 , and ML 4 are accessed at the same time, respectively, by data access path sets DAPS 4 , DAPS 2 , DAPS 1 , and DAPS 3 . Thus, a full data width of the 3-D RAM can still be maintained. If two faults occur in other pairs of data access path sets, such as DAPS 1 and DAPS 2 , a similar setting can be operated accordingly.

FIG. 5 shows four memory arrays and four data access path sets. In one embodiment, the number of memory arrays can be K and the number of data access path sets can be M, where both K and M are natural numbers and are greater than one. In a fault-tolerance access configuration, μ data access path sets are enabled to access memory arrays, where μ is a natural number and 0<μ<M. The path controlling unit 110 and the memory controlling unit 130 select each data access path set to access K/μ memory arrays in each memory layer. The address sequence of the memory arrays or the physical locations in the memory arrays may be different from that in the embodiment of FIG. 3C .

In FIG. 6 , two faults occur in data access path sets DAPS 1 and DAPS 3 in the 3-D RAM. Fault-tolerance access configurations C 011 and C 010 are adopted in memory layers ML 1 and ML 4 , respectively, as normal access configuration C 001 fails to access ML 1 through DAPS 1 and DAPS 3 .

As shown on the upper right of FIG. 6 , memory layer ML 1 adopts fault-tolerance access configuration C 011 to enable data access path sets DAPS 2 and DAPS 4 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 2 to access memory arrays MA 2 and MA 4 , and DAPS 4 to access memory arrays MA 4 and MA 3 , all on memory layer ML 1 , according to the prescribed address sequence.

As shown on the lower left of FIG. 6 , memory layer ML 4 adopts fault-tolerance access configuration C 010 to enable data access path sets DAPS 1 and DAPS 3 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 1 to access memory arrays MA 4 and MA 2 , and DAPS 3 to access memory arrays MA 3 and MA 4 , all on memory layer ML 4 , according to the prescribed address sequence.

Through the above setting, the two faults occurring in data access path sets DAPS 1 and DAPS 3 are avoided. There is no need to equip any redundant TSV for memory layers ML 1 and ML 4 . The two memory layers ML 1 and ML 4 are accessed at the same time, respectively, by data access path sets DAPS 2 , DAPS 4 and DAPS 1 , DAPS 3 . Thus, a full data width of the 3-D RAM can still be maintained.

In FIG. 7 , two faults occur in data access path sets DAPS 1 and DAPS 3 in the 3-D RAM. Fault-tolerance access configurations C 011 and C 010 are adopted in memory layers ML 2 and ML 3 , respectively, as normal access configuration C 001 fails to access ML 2 through DAPS 3 .

As shown on the upper left of FIG. 7 , memory layer ML 2 adopts fault-tolerance access configuration C 011 to enable data access path sets DAPS 2 and DAPS 4 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 2 to access memory arrays MA 2 and MA 1 , and DAPS 4 to access memory arrays MA 4 and MA 3 , all on memory layer ML 2 , according to the prescribed address sequence.

As shown on the lower right of FIG. 7 , memory layer ML 3 adopts fault-tolerance access configuration C 010 to enable data access path sets DAPS 1 and DAPS 3 . The path controlling unit 110 and the memory controlling unit 130 select DAPS 1 to access memory arrays MA 1 and MA 2 , and DAPS 3 to access memory arrays MA 3 and MA 4 , all on memory layer ML 3 , according to the prescribed address sequence.

Through the above setting, the two faults occurring in data access path sets DAPS 1 and DAPS 3 are avoided. There is no need to equip any redundant TSV for memory layers ML 2 and ML 3 . The two memory layers ML 2 and ML 3 are accessed at the same time, respectively, by data access path sets DAPS 2 , DAPS 4 and DAPS 1 , DAPS 3 . Thus, a full data width of the 3-D RAM can still be maintained.

In another embodiment, the settings of FIG. 6 and FIG. 7 can be interleaved in time. In one time, the setting of FIG. 6 is used to access memory layers ML 1 and ML 4 ; in another time, the setting of FIG. 7 is used to access memory layers ML 2 and ML 3 . Thus, all memory layers ML 1 , ML 2 , ML 3 , and ML 4 of the 3-D RAM are accessed.

The above embodiments show concurrent accesses of two memory layers (ML 1 and ML 4 or ML 2 and ML 3 ) or four memory layers (ML 1 , ML 2 , ML 3 , ML 4 ) in the 3-D RAM. In one embodiment, 2 b memory layers are concurrently accessed by data access path sets, where b is a natural number.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.

Moreover, the claims should not be read as limited to the described order or elements unless stated to that effect. In addition, use of the term “means” in any claim is intended to invoke 35 U.S.C. §112, ¶6, and any claim without the word “means” is not so intended.