Computer system and matching circuit thereof

The subject matter herein generally relates to computer systems, and particularly to a computer system with a matching circuit.

Power supply units (PSUs) supply power to motherboards of computers. However, if a timing sequence of a power-good signal of a PSU does not match a timing sequence of a power-good signal of a chip of a motherboard, or if a voltage of the power-good signal of the PSU does not match a voltage of the power-good signal of the chip of the motherboard, the motherboard would not operate.

Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.

FIG. 1 is a block diagram of a computer system comprising a matching circuit.

FIG. 2 is a circuit diagram of the computer system of FIG. 1 .

It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.

Several definitions that apply throughout this disclosure will now be presented.

The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.

FIG. 1 illustrates an embodiment of a computer system 100 . The computer system 100 can comprise a matching circuit 10 , a power supply unit (PSU) 12 , and a chip 19 . The matching circuit 10 is electrically coupled to the PSU 12 and the chip 19 , to match the PSU 12 with the chip 19 .

FIG. 2 illustrates an embodiment of the matching circuit 10 . The matching circuit 10 can comprise a voltage conversion unit 13 , a voltage-dividing unit 16 , a delay unit 18 , an electronic switch Q 1 , a comparator U 1 , and a diode D 1 .

The PSU 12 can comprise a first pin 1 and a second pin 2 . The electronic switch Q 1 can comprise a first terminal, a second terminal, and a third terminal. The comparator U 1 can comprise a non-inverting terminal, an inverting terminal, and an output terminal. The first pin 1 is electrically coupled to a power supply 5V_STBY through a resistor R 1 , electrically coupled to the non-inverting terminal of the comparator U 1 , electrically coupled to a ground through a capacitor C 4 , and electrically coupled to the ground through a resistor R 7 . The first terminal of the electronic switch Q 1 is electrically coupled to the second pin 2 . The second terminal of the electronic switch Q 1 is electrically coupled to the first pin 1 . The third terminal of the electronic switch Q 1 is grounded.

The voltage conversion unit 13 can comprise a low dropout (LDO) regulator 15 . The LDO regulator 15 can comprise a first input terminal VIN, a second input terminal ADJ, and an output terminal OUT. The first input terminal VIN is electrically coupled to the power supply 5V_STBY, and electrically coupled to the ground through a capacitor C 1 . The second input terminal ADJ is electrically coupled to the output terminal OUT through a resistor R 2 , and is electrically coupled to the ground through a resistor R 3 . The output terminal OUT is electrically coupled to the ground through a capacitor C 2 , and is electrically coupled to the inverting terminal of the comparator U 1 through the voltage-dividing unit 16 .

The voltage-dividing unit 16 can comprise two resistors R 4 and R 5 . The delay unit 18 can comprises a resistor R 6 and a capacitor C 3 . The chip 19 can comprise a power-good signal pin SB_PWROK. The inverting terminal of the comparator U 1 is electrically coupled to the output terminal OUT of the LDO regulator 15 through the resistor R 4 , and is electrically coupled to the ground through the resistor R 5 . The output terminal of the comparator U 1 is electrically coupled to a cathode of the diode D 1 . The power-good signal pin SB_PWROK of the chip 19 is electrically coupled to an anode of the diode D 1 , electrically coupled to a power supply 3.3V_SYS through the resistor R 6 , and electrically coupled to the ground through the capacitor C 3 .

When the PSU 12 is powered on, the first pin 1 of the PSU 12 outputs a power-good signal PWROK to the non-inverting terminal of the comparator U 1 , and the second pin 2 of the PSU 12 outputs a power on signal PS_ON at a low level to turn off the electronic switch Q 1 . The LDO regulator 15 converts a voltage of the power supply 5V_STBY received from the first input terminal VIN into a first voltage V 1 , and outputs the first voltage V 1 to the voltage-dividing unit 16 from the output terminal OUT. The first voltage V 1 is divided by the resistors R 4 and R 5 , and a voltage of the resistor R 5 functioning as a reference voltage Vref is output to the inverting terminal of the comparator U 1 . When a voltage of the power-good signal PWROK is greater than the reference voltage Vref, the output terminal OUT of the comparator U 1 outputs a high level signal, the diode D 1 is turned off, the power supply 3.3V_SYS is delayed by the delay unit 18 , and then is output to the power-good signal pin SB_PWROK of the chip 19 . Because of a voltage of the power supply 3.3V_SYS meets a voltage requirement of a power-good signal of the chip 19 , and the power supply 3.3V_SYS is delayed by the delay unit 18 to meet a timing sequence requirement of the power-good signal of the chip 19 , both a voltage and a timing sequence of a signal received by the power-good signal pin SB_PWROK of the chip 19 match the voltage and the timing sequence of the power-good signal of the chip 19 . Therefore, the PSU 12 is matched with the chip 19 by the matching circuit 10 .

When the computer system 100 is turned off, the second pin 2 of the PSU 12 outputs the power on signal PS_ON at a high level to turn on the electronic switch Q 1 . At the moment, the non-inverting terminal of the comparator U 1 receives a low level signal regardless the power-good signal PWROK output from the first pin 1 is at a high level or a low level. The output terminal of the comparator U 1 outputs a low level signal, the diode D 1 is turned on, and the power-good signal pin SB_PWROK of the chip 19 receives a low level signal. As detailed above, when the electronic switch Q 1 is turned on by the high level power on signal PS_ON, the power-good signal PWROK output from the first pin 1 is pulled to a low level. Therefore, malfunction caused by fluctuation of the power-good signal PWROK can be effectively prevented.

In at least one embodiment, the chip 19 can be a motherboard chip, such as a south bridge, a north bridge, and a central processing unit. The electronic switch Q 1 can be an re-channel metal-oxide semiconductor field-effect transistor (NMOSFET), and the first terminal, the second terminal, and the third terminal of the electronic switch Q 1 correspond to a gate, a drain, and a source of the NMOSFET, respectively. In other embodiments, the electronic switch Q 1 can be an npn-type bipolar junction transistor or other suitable switch having similar functions.

The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of the computer system. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size and arrangement of the parts within the principles of the present disclosure up to, and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.