Liquid crystal display and method of charging/discharging pixels of a liquid crystal display

This application is a divisional application of U.S. application Ser. No. 13/450,430 filed Apr. 18, 2012, now abandoned, which claims priority to Taiwan Patent Application No. 100117917, filed May 23, 2011, each of which is incorporated herein by reference in its entirety.

1. Field of the Invention

The present invention relates to liquid crystal displays and methods of charging pixels of liquid crystal displays, and particularly to a liquid crystal display and method of charging pixels thereof that utilize enable signals of two partially-overlapping consecutive gate lines and sequentially-enabled switch enable lines to extend pixel charging time.

2. Description of the Prior Art

Please refer to FIG. 1A and FIG. 1B . FIG. 1A is a diagram illustrating a liquid crystal display (LCD) 100 capable of reducing first data lines of a source driving circuit. FIG. 1B is a diagram illustrating timing of operating gate lines G 1 , G 2 , G 3 and switch enable lines SW 1 , SW 2 , SW 3 of the prior art. As shown in FIG. 1A , first data line FD 1 of source driving circuit corresponds to second data lines SD 11 , SD 12 , SD 13 , and first data line FD 2 of source driving circuit corresponds to second data lines SD 21 , SD 22 , SD 23 . Thus, liquid crystal display 100 uses switch enable lines SW 1 , SW 2 , SW 3 and a plurality of data line switches DS 11 , DS 12 , DS 13 , DS 21 , DS 22 , DS 23 to reduce number of first data lines of source driving circuit. As shown in FIG. 1B , when gate line G 1 is enabled and switch enable lines SW 1 are enabled, data voltage of first data line FD 1 charges second data line SD 11 through data line switches DS 11 , and second data line SD 11 charges pixel P 11 through pixel switch PW 11 . Likewise, when gate line G 1 is enabled and switch enable line SW 2 is also enabled, data voltage of first data line FD 1 charges second data line SD 12 through data line switch DS 12 , and second data line SD 12 charges pixel P 12 through pixel switch PW 12 . When gate line G 1 is enabled and switch enable line SW 3 is also enabled, data voltage of first data line FD 1 charges second data line SD 13 through data line switches DS 13 , and second data line SD 13 charges pixel P 13 through pixel switch PW 13 . As shown in FIG. 1B , because switch enable lines SW 1 , SW 2 , SW 3 are enabled sequentially, charge time of pixel P 11 is interval T1, charge time of pixel P 12 is interval T2, charge time of pixel P 13 is interval T3, where T1>T2>T3, which causes charge rates of pixel P 11 , pixel P 12 , and pixel P 13 to be different. Thus, liquid crystal display 100 exhibits color distortion.

According to an embodiment, a liquid crystal display (LCD) comprises an LCD panel, a source driving circuit, a gate driving circuit, and a timing controller. The LCD panel comprises a plurality of pixels. Each pixel of the plurality of pixels is coupled to a corresponding pixel switch. The source driving circuit is for converting image data into a plurality of data voltages and enabling M first data lines. M is a positive integer. Each first data line of the M first data lines corresponds to a plurality of data line switches, and the first data line charges/discharges according to a data voltage corresponding to the first data line. Each data line switch of the plurality of data line switches corresponds to one second data line and one switch enable line of a plurality of switch enable lines. The gate driving circuit is for enabling N gate lines, where N is a positive integer. The timing controller is for enabling the plurality of switch enable lines. Enable signals of a gate line and a next gate line corresponding to the gate line are partially overlapping.

According to an embodiment, a method of charging/discharging pixels of a liquid crystal display is provided. The liquid crystal display comprises an LCD panel, a plurality of switch enable lines, a source driving circuit and a gate driving circuit. The method comprises converting image data into a plurality of data voltages, charging/discharging a first data line corresponding to a data voltage of the plurality of data voltages according to the data voltage, enabling a gate line corresponding to the first data line of a plurality of gate lines, sequentially enabling all switch enable lines corresponding to the gate line of a plurality of switch enable lines, turning on a plurality of pixel switches corresponding to agate line that is asserted according to the gate line, turning on a data line switch corresponding to switch enable lines that are asserted according to the switch enable lines, the data voltage charging/discharging a second data line corresponding to a data line switch that is turned on through the data line switch, and the second data line that is being charged/discharged charging/discharging a pixel corresponding to a pixel switch that is turned on of the plurality of pixel switches through the pixel switch. Enable signals of the gate line and a next gate line corresponding to the gate line are partially overlapping.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1A is a diagram illustrating a liquid crystal display capable of reducing first data lines of a source driving circuit.

FIG. 1B is a diagram illustrating timing of operating gate lines and switch enable lines of the prior art.

FIG. 2A is a diagram illustrating liquid crystal display.

FIG. 2B is a diagram illustrating timing of operations of liquid crystal display.

FIG. 3A is a diagram illustrating a liquid crystal display according to an embodiment.

FIG. 3B is a diagram illustrating operation timings of liquid crystal display.

FIG. 4 is a diagram of liquid crystal display according to an embodiment.

FIG. 5 is a flowchart of a method of charging/discharging pixels of a liquid crystal display according to an embodiment.

Please refer to FIG. 2A and FIG. 2B . FIG. 2A is a diagram illustrating liquid crystal display 200 , and FIG. 2B is a diagram illustrating timing of operations of liquid crystal display 200 . Liquid crystal display 200 comprises LCD panel 202 , source driving circuit 204 , gate driving circuit 206 , and timing controller 208 . LCD panel 202 comprises a plurality of pixels, and each pixel of the plurality of pixels is coupled to a corresponding pixel switch, where each pixel switch is an N-type thin-film transistor or P-type thin-film transistor. Source driving circuit 204 is used for converting image data to a plurality of data voltages and enabling M first data lines FD 1 -FDM, where M is a positive integer. Each first data line of M first data lines FD 1 -FDM corresponds to a plurality of data line switches, and each first data line is charged/discharged according to a corresponding data voltage, where each data line switch corresponds to one second data line and one switch enable line of three switch enable lines SW 1 -SW 3 , and each data line switch is either an N-type thin-film transistor or P-type thin-film transistor. For example, first data line FD 1 corresponds to three data line switches DS 11 , DS 12 , DS 13 , first data line FD 2 corresponds to three data line switches DS 21 , DS 22 , DS 23 , data line switch DS 11 corresponds to second data line SD 11 and switch enable line SW 1 , data line switch DS 12 corresponds to second data line SD 12 and switch enable line SW 2 , and data line switch DS 13 corresponds to second data line SD 13 and switch enable line SW 3 . Gate driving circuit 206 is used for enabling N gate lines G 1 -GN, where N is a positive integer, and enable signals of two neighboring gate lines are partially overlapping. Timing controller 208 is for sequentially enabling a plurality of switch enable lines SW 1 -SW 3 .

As shown in FIG. 2B , while gate line G 1 is enabled, and source driving circuit 204 charges/discharges first data line FD 1 according to corresponding data voltage, gate line G 2 is pre-enabled, namely enable signal of gate line G 1 and enable signal of gate line G 2 partially overlap. Thus, when switch enable line SW 1 , gate line G 1 and gate line G 2 are both enabled (period T1 of FIG. 2B ), first data line FD 1 charges/discharges second data line SD 11 through turned on data line switches DS 11 according to corresponding data voltage, and second data line SD 11 charges/discharges pixel P 111 through turned on pixel switch PW 111 according to corresponding data voltage. At this time, because gate line G 2 is also enabled, second data line SD 11 also charges/discharges pixel P 211 through turned on pixel switch PW 211 according to corresponding data voltage. Likewise, in period T2 of FIG. 2B , first data line FD 1 charges/discharges second data line SD 12 through turned on data line switch DS 12 according to corresponding data voltage, and second data line SD 12 charges/discharges pixel P 112 through turned on pixel switch PW 112 according to corresponding data voltage. At this time, because gate line G 2 is also enabled, second data line SD 12 also charges/discharges pixel P 212 according to corresponding data voltage through turned on pixel switch PW 212 . Likewise, in period T3 of FIG. 2B , first data line FD 1 charges/discharges second data line SD 13 through turned on data line switch DS 13 according to corresponding data voltage, and second data line SD 13 charges/discharges pixel P 113 through turned on pixel switch PW 113 according to corresponding data voltage. At this time, because gate line G 2 is also enabled, second data line SD 13 also charges/discharges pixel P 213 through turned on pixel switch PW 213 according to corresponding data voltage. As shown in FIG. 2B , polarities of pixel P 111 and pixel P 211 are the same, polarities of pixel P 112 and pixel P 212 are the same, and polarities of pixel P 113 and pixel P 213 are the same. Thus, pixel P 211 , pixel P 212 and pixel P 213 have already been pre-charged/pre-discharged by data voltages corresponding to pixel P 111 , pixel P 112 , and pixel P 113 prior to being charged by corresponding data voltages. Thus, liquid crystal display 200 may increase charging rate of pixel P 211 , pixel P 212 and pixel P 213 . Additionally, operation timings of other gate lines liquid crystal display 200 are similar to those of gate line G 1 and gate line G 2 , and are not described again here.

Please refer to FIG. 3A and FIG. 3B . FIG. 3A is a diagram illustrating a liquid crystal display 300 according to an embodiment. FIG. 3B is a diagram illustrating operation timings of liquid crystal display 300 . Liquid crystal display 300 comprises LCD panel 302 , source driving circuit 304 , gate driving circuit 306 , timing controller 308 . LCD panel 302 comprises a plurality of pixels, where each pixel of the plurality of pixels is coupled to a corresponding pixel switch, and each pixel switch is an N-type thin-film transistor or a P-type thin-film transistor. Additionally, each pixel switch has a first terminal coupled to a corresponding pixel, a second terminal coupled to a corresponding gate line, and a third terminal coupled to a corresponding second data line. For example, pixel switch PW 111 has a first terminal coupled to pixel P 111 , a second terminal coupled to gate line G 1 , and a third terminal coupled to second data line SD 11 . Source driving circuit 304 is used for converting image data into a plurality of data voltages and enabling M first data lines FD 1 -FDM, where M is a positive integer, each first data line of the M first data lines FD 1 -FDM corresponds to a plurality of data line switches, and each first data line is charged/discharged according to corresponding data voltage, where each data line switch corresponds to a second data line and one of six switch enable lines SW 1 -SW 6 , and data line switches are N-type thin-film transistors or P-type thin-film transistors, but the present invention is not limited to six switch enable lines SW 1 -SW 6 . For example, first data line FD 1 corresponds to three data line switches DS 11 , DS 12 , DS 13 , first data line FD 2 corresponds to three data line switches DS 21 , DS 22 , DS 23 , data line switches DS 11 corresponds to second data line SD 11 and switch enable line SW 1 , data line switch DS 12 corresponds to second data line SD 12 and switch enable line SW 2 , data line switch DS 13 corresponds to second data line SD 13 and switch enable line SW 3 , data line switch DS 21 corresponds to second data line SD 21 and switch enable line SW 4 , data line switch DS 22 corresponds to second data line SD 22 and switch enable line SW 5 , and data line switch DS 23 corresponds to second data line SD 23 and switch enable line SW 6 . Additionally, each data line switch has a first terminal coupled to a corresponding first data line, a second terminal coupled to a corresponding switch enable line, and a third terminal coupled to a corresponding second data line. For example, data line switch DS 11 has a first terminal coupled to first data line FD 1 , a second terminal coupled to switch enable line SW 1 , and a third terminal coupled to second data line SD 11 . Gate driving circuit 306 is used for enabling N gate lines G 1 -GN, where N is a positive integer, two neighboring gate lines have partially overlapping enable signals, and two neighboring pixel switches of each row of pixels in LCD panel 302 turn on and turn off according to enable signals of two corresponding gate lines, respectively. For example, pixel switch PW 111 turns on and turns off according to enable signal of gate line G 1 , and pixel switch PW 221 turns on and turns off according to enable signal of gate line G 2 . Timing controller 308 is used for sequentially enabling a plurality of switch enable lines SW 1 -SW 6 .

As shown in FIG. 3B , in region T1, gate line G 1 is enabled and switch enable lines SW 1 , SW 2 , SW 3 are enabled sequentially, where enable signal of gate line G 1 is as long as the sum of lengths of enable signals of switch enable lines SW 1 , SW 2 , SW 3 . However, the present invention is not limited thereto, namely enable signal of gate line G 1 may have length longer than the sum of lengths of enable signals of switch enable lines SW 1 , SW 2 , SW 3 . Thus, when switch enable line SW 1 and gate line G 1 are both enabled, first data line FD 1 charges second data line SD 11 through turned on data line switch DS 11 according to corresponding data voltage, and second data line SD 11 charges pixel P 111 through turned on pixel switch PW 111 according to corresponding data voltage. When switch enable line SW 2 and gate line G 1 are both enabled, first data line FD 1 charges second data line SD 12 through turned on data line switch DS 12 according to corresponding data voltage, and second data line SD 12 charges pixel P 112 through turned on pixel switch PW 112 according to corresponding data voltage. When switch enable line SW 3 and gate line G 1 are both enabled, first data line FD 1 charges second data line SD 13 through turned on data line switch DS 13 according to corresponding data voltage, and second data line SD 13 charges pixel P 113 through turned on pixel switch PW 113 according to corresponding data voltage. Likewise, in region T2, operation of gate line G 2 , second data line FD 2 and switch enable lines SW 4 , SW 5 , SW 6 is similar to that of gate line G 1 , second data line FD 1 and switch enable lines SW 1 , SW 2 , SW, and is not described again here. As shown in FIG. 3B , enable signal of gate line G 1 continues to region T2, so that pixel P 111 , pixel P 112 and pixel P 113 are all charged continuously up to region T2, i.e. in the partially overlapping period (region T2) of enable signal of gate line G 1 and enable signal of gate line G 2 , pixel P 111 , pixel P 112 and pixel P 113 are charged continuously. In this way, liquid crystal display 300 may have increased pixel charging rate. Operation timings of remaining gate lines of liquid crystal display 300 are the same as those of gate line G 1 and gate line G 2 , and are not described again here.

Please refer to FIG. 4 , which is a diagram of liquid crystal display 400 . Liquid crystal display 400 comprises LCD panel 402 , source driving circuit 404 , gate driving circuit 406 , and timing controller 408 . Liquid crystal display 400 differs from liquid crystal display 300 in that each pixel switch of each row of pixels in LCD panel 402 turns on and turns off according to enable signal of gate line corresponding to each row of pixels, and each two neighboring pixels of each column of pixels in LCD panel 402 are charged/discharged according to corresponding data voltages of two second data lines corresponding to each row of pixels respectively. For example, pixel P 111 , pixel P 112 and pixel P 113 turn on and turn off according to enable signal of gate line G 1 , and pixel P 111 and pixel P 221 are charged/discharged according to data voltages of second data line SD 11 and second data line SD 21 . Operation principles and timings of liquid crystal display 400 are similar to those of liquid crystal display 300 , and are not described again here.

Please refer to FIG. 5 , which is a flowchart of a method of charging/discharging pixels of a liquid crystal display according to an embodiment. The method shown in FIG. 5 is illustrated with reference to liquid crystal display 300 of FIG. 3A , and comprises the following steps:

Step 502 : Source driving circuit 304 converts image data into a plurality of data voltages;

Step 504 : First data line FD 1 is charged/discharged according to a data voltage of a plurality of data voltages;

Step 506 : Gate driving circuit 306 enables gate line G 1 corresponding to first data line FD 1 of a plurality of gate lines G 1 -GN;

Step 508 : Timing controller 308 sequentially enables switch enable lines SW 1 -SW 3 of switch enable lines SW 1 -SW 6 corresponding to gate line G 1 ;

Step 510 : Turn on pixel switches PW 111 -PW 113 corresponding to gate line G 1 according to enabled gate line G 1 ;

Step 512 : Sequentially turn on corresponding data line switches DS 11 -DS 13 according to sequentially enabled switch enable lines SW 1 -SW 3 ;

Step 514 : Data voltages sequentially charge/discharge corresponding second data lines SD 11 -SD 13 through sequentially turned on data line switches DS 11 -DS 13 ;

Step 516 : Charged/discharged second data lines SD 11 -SD 13 charge corresponding pixels P 111 -P 113 through turned on pixel switches PW 111 -PW 113 .

In step 508 , enable signal of gate line G 1 is as long as the sum of lengths of enable signals of switch enable lines SW 1 , SW 2 , SW 3 . However, the present invention is not limited thereto, namely enable signal of gate line G 1 may be longer than the sum of lengths of enable signals of switch enable lines SW 1 , SW 2 , SW 3 . In step 514 , data voltage on first data line FD 1 sequentially charges/discharges second data lines SD 11 -SD 13 through sequentially turned on data line switches DS 11 -DS 13 . Thus, in step 516 , charged/discharged second data lines SD 11 -SD 13 sequentially charge/discharge pixels P 111 -P 113 through turned on pixel switches PW 111 -PW 113 . Likewise, as shown in FIG. 3A , data voltage on first data line FD 2 charges pixels P 221 -P 223 according to steps shown in FIG. 5 , where pixels P 221 -P 223 correspond to gate line G 2 . Thus, in the embodiment of FIG. 5 , pixels P 111 -P 113 charged/discharged during enable signal of gate line G 1 are on the same row as pixels P 221 -P 223 charged/discharged during enable signal of G 2 . Additionally, second data lines SD 11 -SD 13 continuously charge/discharge pixels P 111 -P 113 through turned on pixel switches PW 111 -PW 113 during partially overlapping period of enable signal of gate line G 1 and enable signal of gate line G 2 .

Additionally, in another embodiment of FIG. 5 (corresponding to liquid crystal display 400 of FIG. 4 ), data voltage on first data line FD 2 charges/discharges pixels P 221 -P 223 according to the steps of FIG. 5 , where pixels P 221 -P 223 correspond to gate line G 2 . Thus, in another embodiment of FIG. 5 , pixels P 111 -P 113 charged/discharged during enable signal of gate line G 1 and pixels P 221 -P 223 charged/discharged during enable signal of gate line G 2 are pixels of two neighboring rows.

In summary, liquid crystal displays and methods of charging/discharging pixels of liquid crystal displays disclosed above utilize two consecutive, partially overlapping gate line enable signals and sequentially enabled switch enable lines to extend charging/discharging time of pixels. Thus, the embodiments increase pixel charging rate to improve on the problem of the prior art of different charging rates between pixels corresponding to the same first data line.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.