Data writing system and method for DMA

The invention relates to a data writing system, and more particularly to a data writing method for direct memory access (DMA).

In a typical electronic system that comprises one or more processors, memories, and input/output (I/O) devices or interfaces, direct memory access (DMA) transfers are often used to transfer data between the I/O and the memory. When the processor uses programmed input/output without DMA, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other tasks for the processor. When the processor initiates a DMA transfer, the processor can do other operations while the DMA transfer is in progress, and it receives an interrupt when the DMA transfer is done. Many hardware systems use DMA, including disk-drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors. The electronic systems that have DMA channels can transfer data to and from devices with much less processor overhead than the electronic systems without DMA channels. Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.

A data writing system and a data writing method are provided. An embodiment of a data writing system is provided. The data writing system comprises a processing unit, a storage device, a dynamic random access memory (DRAM), and a bus arbiter coupled between the processing unit, the DRAM and the storage device. The processing unit comprises at least one core processor. The DRAM comprises a user buffer storing data to be written to the storage device, a buffer cache and a direct memory access (DMA) buffer. The processing unit executes a plurality of write transactions for moving a portion of the data from the user buffer of the DRAM to the storage device via a first write path, and the remainder of the data from the user buffer of the DRAM to the storage device via a second write path. The first write path passes through the buffer cache of the DRAM, and the second write path does not pass through the buffer cache of the DRAM.

Furthermore, an embodiment of a data writing method for a core processor is provided, wherein the core processor writes data from a dynamic random access memory (DRAM) to a storage device through a bus arbiter coupled between the DRAM, the storage device and the core processor. A plurality of first write transactions are executed to move a portion of the data from a user buffer of the DRAM to the storage device via a first write path, wherein the portion of data is accessed through the bus arbiter five times in the first write path when the first write transactions are completed. It is determined whether to perform a sequential write process according to the number of the first write transactions. A plurality of second write transactions are executed when the sequential write process is performed, so as to move the remainder of the data from the user buffer of the DRAM to the storage device via a second write path, wherein the remainder of the data is accessed through the bus arbiter three times in the second write path when the second write transactions are completed. The DRAM further comprises a buffer cache and a direct memory access (DMA) buffer.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows a data writing system according to an embodiment of the invention;

FIG. 2A and FIG. 2B respectively show the first and second phases P 1 and P 2 of the write operation according to an embodiment of the invention;

FIG. 3 shows a schematic illustrating the relationship between the data 138 of FIG. 1 and the first and second phases P 1 and P 2 of the write operation; and

FIG. 4 shows a data writing method for a core processor according to an embodiment of the invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 shows a data writing system 100 according to an embodiment of the invention. The data writing system 100 comprises a processing unit 110 , a dynamic random access memory (DRAM) 130 , a storage device 150 and a bus arbiter 170 . The bus arbiter 170 is coupled between the processing unit 110 , the DRAM 130 and the storage device 150 , and is capable of allocating access to the DRAM 130 and the storage device 150 . The processing unit 110 comprises two processor clusters 125 A and 125 B and a cache coherent interconnect (CCI) device 120 . Each of the processor clusters 125 A and 125 B comprises a plurality of core processors and the corresponding caches. For example, the processor cluster 125 A comprises a core processor 112 A, a core processor 112 B, a level 1 cache 114 A corresponding to the core processor 112 A, a level 1 cache 114 B corresponding to the core processor 112 B, and a level 2 cache 116 A corresponding to the core processors 112 A and 112 B. Furthermore, the processor cluster 125 B comprises a core processor 112 C, a core processor 112 D, a level 1 cache 114 C corresponding to the core processor 112 C, a level 1 cache 114 D corresponding to the core processor 112 D, and a level 2 cache 116 B corresponding to the core processors 112 C and 112 D. The DRAM 130 comprises a user buffer 135 for storing the mass data 138 , a buffer cache 140 and a direct memory access (DMA) buffer 145 , wherein the storage capacity of the buffer cache 140 is smaller than that of the user buffer 135 and the DMA buffer 145 in the DRAM 130 . In one embodiment, the data writing system 100 can be implemented in a portable electronic device, and the storage device 150 may be an embedded multimedia card (eMMC) or a USB Flash Device (UFD). In FIG. 1 , one of the core processors 112 A- 112 D is used to perform a write operation for writing the data 138 stored in the DRAM 130 into the storage device 150 via the bus arbiter 170 . Furthermore, the write operation can be divided into a first phase and a second phase. The detail of the first and second phases will be described below.

FIG. 2A and FIG. 2B respectively show the first and second phases P 1 and P 2 of the write operation according to an embodiment of the invention, and FIG. 3 shows a schematic illustrating the relationship of the data 138 of FIG. 1 and the first and second phases P 1 and P 2 of the write operation. In FIG. 3 , the data 138 are divided into a plurality of data segments SEG 0 -SEGx, wherein each segment corresponds to a write transaction. Referring to FIG. 2A and FIG. 3 together, it is assumed that the core processor 112 C is used to perform the write operation. In the first phase P 1 of the write operation, the core processor 112 C executes the write transactions to move the data segments SEG 0 -SEG 6 of the data 138 from the user buffer 135 of the DRAM 130 to the storage device 150 via a first write path Path_ 1 , wherein the first write path Path_ 1 comprises five segments S 11 , S 12 , S 13 , S 14 and S 15 . For example, if the transaction corresponding to the data segment SEG 0 is executed by the core processor 112 C, the data segment SEG 0 is moved from the user buffer 135 of the DRAM 130 to the level 1 cache 114 C of the core processor 112 C via the bus arbiter 170 first, i.e. the segment S 11 of the write path Path_ 1 . Next, the data segment SEG 0 is moved from the level 1 cache 114 C of the core processor 112 C to the buffer cache 140 of the DRAM 130 via the bus arbiter 170 (i.e. the segment S 12 of the first write path Path_ 1 ). Next, the data segment SEG 0 is moved from the buffer cache 140 of the DRAM 130 to the level 1 cache 114 C of the core processor 112 C via the bus arbiter 170 , i.e. the segment S 13 of the first write path Path_ 1 . Next, the data segment SEG 0 is moved from the level 1 cache 114 C of the core processor 112 C to the DMA buffer 145 of the DRAM 130 via the bus arbiter 170 , i.e. the segment S 14 of the first write path Path_ 1 . Next, the data segment SEG 0 is moved from the DMA buffer 145 of the DRAM 130 to the storage device 150 via the bus arbiter 170 , i.e. the segment S 15 of the first write path Path_ 1 . Thus, the transaction corresponding to the data segment SEG 0 is completed. Furthermore, in the first phase P 1 of the write operation, each data segment is accessed through the bus arbiter 170 five times in the write path Path_ 1 when the transaction corresponding to the data segment is executed and completed. In other words, the level 1 cache 114 C of the core processor 112 C obtains each data segment twice when the data segment is moved from the user buffer 135 of the DRAM 130 to the storage device 150 via the first write path Path_ 1 .

When the number of the data segments to be written to the storage device 150 in the first phase P 1 of the write operation exceeds a specific number, the core processor 112 C will determine that the write operation is a sequential write operation, and enter the second phase P 2 of the write operation to perform a sequential write process. Specifically, when the number of the write transactions exceeds the specific number, the sequential write process is performed, wherein the write transactions correspond to the data segments moved from the DRAM 130 to the storage device 150 via the first write path Path_ 1 . It should be noted that the specific number is determined according to various applications. Referring to FIG. 2B and FIG. 3 together, in the second phase P 2 of the write operation, the core processor 112 C executes the write transactions to move the remaining data segments SEG 7 -SEGx of the data 138 from the user buffer 135 of the DRAM 130 to the storage device 150 via a second write path Path_ 2 , wherein the second write path Path_ 2 comprises three segments S 21 , S 22 and S 23 . For example, if the transaction corresponding to the data segment SEG 7 is executed by the core processor 112 C, the data segment SEG 7 is moved from the user buffer 135 of the DRAM 130 to the level 1 cache 114 C of the core processor 112 C via the bus arbiter 170 first, i.e. the segment S 21 of the second write path Path_ 2 . Next, the data segment SEG 7 is moved from the level 1 cache 114 C of the core processor 112 C to the DMA buffer 145 of the DRAM 130 via the bus arbiter 170 , i.e. the segment S 22 of the second write path Path_ 2 . Next, the data segment SEG 7 is moved from the DMA buffer 145 of the DRAM 130 to the storage device 150 via the bus arbiter 170 , i.e. the segment S 23 of the second write path Path_ 2 . Thus, the transaction corresponding to the data segment SEG 7 is completed. Furthermore, in the second phase P 2 of the write operation, each data segment is accessed through the bus arbiter 170 three times in the second write path Path_ 2 when the transaction corresponding to the data segment is executed and completed. In other words, the level 1 cache 114 C of the core processor 112 C obtains each data segment only one time when the data segment is moved from the user buffer 135 of the DRAM 130 to the storage device 150 via the second write path Path_ 2 . Specifically, the buffer cache 140 of the DRAM 130 will not be occupied in the second phase P 2 of the write operation, thus decreasing power consumption and access time for the DRAM 130 . Furthermore, the number of the write transactions in the first phase P 1 of the write operation is smaller than the number of the write transactions in the second phase P 2 of the write operation.

FIG. 4 shows a data writing method for a core processor according to an embodiment of the invention, wherein the core processor writes data from a dynamic random access memory (DRAM) to a storage device through a bus arbiter coupled between the DRAM, the storage device and the core processor. In the embodiment, the DRAM comprises a user buffer, a buffer cache and a DMA buffer, and the data to be written to the storage device is stored in the user buffer, as shown in the DRAM 130 of the FIG. 1 . First, in step S 410 , the core processor executes a plurality of write transactions to move a portion of the data from the user buffer of the DRAM to the storage device via a first write path, e.g. the write path Path_ 1 of FIG. 2A . As described above, the portion of data is accessed through the bus arbiter five times in the first write path when the write transactions corresponding to the portion of data are completed. For example, the portion of data is moved from the user buffer of the DRAM to a level 1 cache of the core processor via the bus arbiter first. Next, the portion of data is moved from the level 1 cache of the core processor to the buffer cache of the DRAM via the bus arbiter. Next, the portion of data is moved from the buffer cache of the DRAM to the level 1 cache of the core processor via the bus arbiter. Next, the portion of data is moved from the level 1 cache of the core processor to the DMA buffer of the DRAM via the bus arbiter. Next, the portion of data is moved from the DMA buffer of the DRAM to the storage device via the bus arbiter. In step S 420 , the core processor determines whether to perform a sequential write process according to the number of the write transactions executed in step S 410 . If the number of the write transactions executed in step S 410 does not exceed a specific number, the core processor continues to move the remainder of the data from the user buffer of the DRAM to the storage device via the first write path (step S 430 ). Conversely, if the number of the write transactions executed in step S 410 exceeds the specific number, the core processor will determine that the write operation is a sequential write operation, and then the sequential write process is performed (step S 440 ), so as to move the remainder of the data from the user buffer of the DRAM to the storage device via a second write path, wherein the second write path is shorter than the first write path, e.g. the write path Path_ 2 of FIG. 2B . As described above, the remainder of data is accessed through the bus arbiter three times in the second write path when the write transactions corresponding to the portion of data are completed. For example, the remainder of data is moved from the user buffer of the DRAM to a level 1 cache of the core processor via the bus arbiter first. Next, the remainder of data is moved from the level 1 cache of the core processor to the DMA buffer of the DRAM via the bus arbiter without through the buffer cache of the DRAM. Next, the remainder of data is moved from the DMA buffer of the DRAM to the storage device via the bus arbiter.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.