USPatent applicationPatented

Touch display device

Granted 6 Dec 2016 · 1 office action

Life of the application

9 dated events
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Abstract

A touch display device includes a first substrate, a second substrate, a number of first sensing electrodes formed on the first substrate, a number of second sensing electrodes formed on the second substrate, a touch integrated circuit set on the first substrate, and a number of connecting wires formed on the first substrate. The touch integrated circuit includes a number of first pins correspondingly connected to the first sensing electrodes and a number of second pins correspondingly connected to the second sensing electrodes. The connecting wires correspondingly connect two opposite terminals of the first sensing electrodes with two opposite ends of the first pins. A part of connecting wires are arranged between the first pins and the second pins. The first substrate includes a shielding sheet formed in the first substrate and located above the part of the connecting wires arranged between the first pins and the second pins.

Description

5 parts
›FIELD

The disclosure generally relates to touch and display technologies.

›BACKGROUND

An in-cell touch display device usually includes a opposite substrate, an array substrate opposite to the opposite substrate, a number of first touch sensing electrodes formed on the opposite substrate, and a number of second touch sensing electrodes formed on the array substrate. The first touch sensing electrodes are connected to a number of first pins of a touch integrated circuit (IC) on the array substrate via a flexible printed circuit (FPC). The second touch sensing electrodes are connected to a number of second pins of the touch IC via a number of wires. However, a coupling capacitance is generated between the wires of the second touch sensing electrodes and the first pins of the first touch sensing electrodes, which adversely affects touch signal sensed by the first touch sensing electrodes and the second touch sensing electrodes and reduces accuracy of touch sensing.

›BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the views.

FIG. 1 is a diagrammatic view of a touch display device of a first embodiment.

FIG. 2 is an isometric view of the touch display device of FIG. 1 .

FIG. 3 is a diagrammatic view of a first substrate of the touch display device of FIG. 2 .

FIG. 4 is a cross-sectional view of the first substrate of FIG. 3 , taken along line IV-IV.

FIG. 5 is a cross-sectional view of the first substrate of FIG. 3 , taken along line V-V.

FIG. 6 is a diagrammatic view of a first substrate of a touch display device of a second embodiment.

›DETAILED DESCRIPTION · 1 of 2

The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references can mean “at least one.”

FIGS. 1 and 2 illustrate a touch display device 100 of a first embodiment. FIG. 3 illustrates a wiring pattern of the first substrate. Referring to FIGS. 1 to 3 , the touch display device 100 includes a first substrate 110 , a second substrate 190 , a liquid crystal layer 170 , a number of first sensing electrodes 120 , a number of second sensing electrodes 180 , a touch IC 150 , a number of connecting wires 121 , and a connecting circuit 140 . In this embodiment, the connecting circuit 140 is an FPC (flexible printed circuit). The liquid crystal layer 170 is disposed between the first substrate 110 and the second substrate 190 . The touch display device 100 defines a display area A-A and a non-display area B encircling the display area A-A on the first substrate 110 and the second substrate 190 . The first sensing electrodes 120 are formed on a surface of the first substrate 110 facing the liquid crystal layer 170 and located in the display area A-A. The second sensing electrodes 180 are formed on a surface of the second substrate 190 opposite to the liquid crystal layer 170 and located in the display area A-A. The touch IC 150 is set on the surface of the first substrate 110 facing the liquid crystal layer 170 and located in the non-display area B. The connecting circuit 140 connects the second sensing electrodes 180 with the touch IC 150 . The connecting wires 121 are formed in the first substrate 110 and located in the non-display area B. The first sensing electrodes 120 are connected to the touch IC 150 via the connecting wires 121 .

In this embodiment, the touch display device 100 is a fringe field switching (FFS) type touch display device 100 or an in-plane switching (IPS) type touch display device 100 . The first sensing electrodes 120 are extended along a first direction X. The second sensing electrodes 180 are extended along a second direction Y. The first direction X is perpendicular to the second direction Y. The first sensing electrodes 120 cooperates with the second sensing electrodes 180 to generate a touch sensing signal corresponding to a touch in the display area A-A. The touch sensing signal is transmitted to the touch IC 150 to determine a position of the touch in the display area A-A.

Referring to FIG. 3 , the touch IC 150 includes a number of first pins 123 and a number of second pins 125 . The first pins 123 are arranged as a line and near the display area A-A. The second pins 125 are arranged far away from display area A-A. The second pins 125 are also arranged as line parallel to the line of the first pins 123 . The first pins 123 correspondingly connects with the first sensing electrodes 123 via the connecting wires 121 . The second pins 125 correspondingly connects with the second sensing electrodes 180 via the connecting circuit 140 (see FIG. 2 ). Each of the first sensing electrode 120 includes two opposite connecting terminals 120 a and 120 b . Each of the first pins 123 includes two opposite ends 123 a and 123 b . A pair of connecting wires 121 correspondingly connect two opposite terminals 120 a and 120 b of each first sensing electrodes 120 with two opposite ends 123 a and 123 b of one of the first pins 123 to form a closed loop path.

FIG. 4 illustrates a cross-sectional view taken along line IV-IV of FIG. 3 . Referring to FIG. 4 , the first substrate 110 further includes a base 111 , a first insulating layer 112 , a second insulating layer 113 , a shielding sheet 127 , a third insulating layer 115 , and a number of connecting lines 1190 . The first insulating layer 112 is formed on the base 111 . The second insulating layer 113 is formed on the first insulating layer 112 to cover the connecting wires 121 . The shielding sheet 127 is formed on the second insulating layer 113 corresponding to at least a part of the connecting wires 121 . In the embodiment, the shielding sheet 127 is located above a part of the connecting wires 121 which are arranged between the first pins 123 and the second pins 125 . The shielding sheet 127 is made of conductive material. For example, in this embodiment, the shielding sheet 127 is made of conductive metal. In other embodiments, the shielding sheet 127 also can be made of indium tin oxide (ITO). The shielding sheet 127 is grounded or applied with a constant voltage to reduce a capacity coupling generated between the connecting wires 121 and the second pins 125 . The third insulating layer 115 is formed on the second insulating layer 113 to cover the shielding sheet 127 . Two opposite ends 123 a and 123 b of each first pin 123 are correspondingly aligned with the connecting wires 121 . The first substrate 110 defines a number of connecting through holes 119 passing through the second insulating layer 113 and the third insulating layer 115 . The connecting through holes 190 are corresponding to the two opposite ends 123 a and 123 b of each first pin 123 . The connecting lines 1190 are formed in the connecting through holes 119 to connect the connecting wires 121 with the first pins 123 .

FIG. 5 illustrates a cross-sectional view taken along line V-V of FIG. 3 . Referring to FIG. 5 , the first substrate 110 further includes a number of gate lines 116 and a number of data lines 114 . The gate lines 116 and the data lines 114 are located in the display area A-A. The gate lines 116 are formed on the first insulating layer 112 . The gate lines 116 are extended along a direction parallel to the first sensing electrodes 120 . The data lines 114 are formed on the second insulating layer 113 . The data lines 114 are extended along a direction perpendicular to the first sensing electrodes 120 . In this embodiment, the gate lines 116 are formed at the same time with the connecting wires 121 by patterning a first conductive metal. The data lines 114 are formed at the same time with the shielding sheet 127 by patterning a second conductive metal.

›DETAILED DESCRIPTION · 2 of 2

Referring to FIG. 3 , the part of the connecting wires 121 arranged between the first pins 123 and the second pins 125 includes a first portion 121 x located in a projection of the touch IC 150 and a second portion 121 y located out of a projection of the touch IC 150 . In this embodiment, the shielding sheet 127 covers both of the first portion 121 x and the second portion 121 y . Referring to FIG. 6 , in a second embodiment, the shielding sheet 127 only covers the first portion 121 x.

It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the scope of the disclosure or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments.

Claims as granted

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Classifications

1 codes
IPC · International Patent Classification
Section G — Physics
  • G06F3/041

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File wrapper

⤢ drag to zoomOct 2014Jan 2015Apr 2015Jul 2015Oct 2015Jan 2016Apr 2016Jul 2016Oct 2016Jan 2017USPTOApplicantNon-final rejectionResponse after non-finalNotice of allowance
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Pendency
2.1 y
783 days filing → grant
Office actions
1
non-final + final
Responses
1
no RCE
Examiner
Nathanael R Briggs
art unit 2871 · TC 2800
Citations: 6 back · 0 forward

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