Sample and hold circuit and source driver including the same

1. Field of the Invention

The present invention relates to a display device, and more particularly, to a sample and hold circuit and a source driver including the same.

2. Description of the Related Art

A sample and hold circuit refers to a circuit which samples a signal and holds the sampled signal until the sampled signal is processed. The sample and hold circuit may be represented by S/H.

When an analog-to-digital converter is used to quantize a signal, it is impossible to convert a wideband signal in case where a conversion time is not sufficiently short. Thus, the signal needs to be extended to the time required for processing the signal. Thus, an operation of converting continuous waveforms into discontinuous waveforms, that is, an operation of sampling a signal and holding the sampled signal for a predetermined time may be referred to as a sample and hold operation.

At this time, a switching noise signal may be introduced into the sample and hold circuit by switching operations of a plurality of switching elements formed in the sample and hold circuit. Such a switching noise signal may be contained in an output signal of the sample and hold circuit. The switching noise signal may cause an error while pixel information is detected.

Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and an object of the present invention is to provide a sample and hold circuit capable of offsetting and eliminating noise which may be introduced while pixel information is sampled and held, and a source driver including the same.

In order to achieve the above object, according to one aspect of the present invention, a sample and hold circuit may include: a main sample and hold circuit configured to sample and hold pixel information of an organic light emitting diode (OLED) cell, and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit, and output a second output signal for offsetting a switching noise signal contained in the first output signal.

According to another aspect of the present invention, a sample and hold circuit may include: a main sample and hold circuit including: a first main switching element configured to transmit pixel information of an OLED cell; a main sampling capacitor configured to sample the pixel information transmitted from the first main switching element; a second main switching element configured to transmit the pixel information sampled by the main sampling capacitor; a main charge sharing unit configured to hold the sampled pixel information; and a third main switching element configured to output the pixel information held in the main charge sharing unit as a first output signal; a dummy sample and hold circuit including: a first dummy switching element configured to transmit a reference voltage; a dummy sampling capacitor configured to sample the reference voltage transmitted from the first dummy switching element; a second dummy switching element configured to transmit the reference voltage sampled by the dummy sampling capacitor; a dummy charge sharing unit configured to hold the sampled reference voltage; and a third dummy switching element configured to output the reference voltage held in the dummy charge sharing unit as a second output signal; and a common coupling unit configured to couple the main sampling capacitor and the dummy sampling capacitor and couple the main charge sharing unit and the dummy charge sharing unit.

According to another aspect of the present invention, a source driver may include: a sample and hold circuit including: a main sample and hold circuit configured to sample and hold pixel information of an OLED cell and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit and output a second output signal for offsetting a switching noise signal contained in the first output signal; and an amplifier configured to receive the first and second output signals, and differentially amplify the first and second output signals so as to offset the switching noise signal contained in the first output signal.

The above objects, and other features and advantages of the present invention will become more apparent after a reading of the following detailed description taken in conjunction with the drawings, in which:

FIG. 1 is a block diagram of a display device to which an embodiment of the present invention is applied;

FIG. 2 is a schematic block diagram of a source driver illustrated in FIG. 1 ;

FIG. 3 is a block diagram of a sample and hold circuit illustrated in FIG. 2 ; and

FIG. 4 is a circuit diagram of the sample and hold circuit illustrated in FIG. 2 .

Reference will now be made in greater detail to a preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a block diagram of a display device 101 to which an embodiment of the present invention is applied. Referring to FIG. 1 , the display device 101 may include a timing controller 111 , a source driver 121 , a gate driver 131 , and a display panel 141 .

The timing controller 111 may transmit image data DA and a clock signal CLK to the source driver 121 , and transmit a gate control signal GC to the gate driver 131 .

The source driver 121 may receive the clock signal CLK and the image data DA from the timing controller 111 , process the image data DA in synchronization with the clock signal CLK, and output source driving signals S 1 and S 2 to the display panel 141 to drive data lines SL formed in the display panel 141 . FIG. 1 illustrates one source driver 121 , but the display device 101 may include a plurality of source drivers 121 in consideration of the size and resolution of the display panel 141 .

The source driver 121 may include output buffers 210 , sample and hold circuits 220 , an amplifier 230 , and an analog-to-digital converter 240 . The output buffers 210 may output the source driving signals S 1 and S 2 , respectively. The sample and hold circuits 220 may detect pixel information transmitted from the display panel 141 . The amplifier 230 may amplify output signals of the sample and hold circuits 220 . The analog-to-digital converter 240 may convert the output signals of the amplifier 230 into digital signals. Although not illustrated, the source driver 121 may further include a shift register (not illustrated), a latch (not illustrated), and a digital-to-analog converter (not illustrated), in order to process the image data DA in synchronization with the clock signal CLK. The signals processed through the digital-to-analog converter may be outputted as the source driving signals S 1 and S 2 through the output buffers 210 , respectively.

The output signals of the analog-to-digital converter 240 may be provided to the timing controller 111 , and the timing controller 111 may perform a control operation reflecting the pixel information by referring to the output signals of the analog-to-digital converter 240 .

The amplifier 230 may amplify the output signals of the sample and hold circuits 220 , in order to guarantee a high-speed operation of the analog-to-digital converter 240 .

The sample and hold circuit 220 may recognize pixel information of an OLED cell 143 , transmitted through a data line SL of the display panel 141 . The pixel information may include a turn-on voltage of an organic light emitting diode (OLED), a threshold voltage Vth of a thin film transistor (TFT), a current characteristic of the TFT, and a mobility characteristic of the TFT. Among the characteristics, the current characteristic of the TFT may be sensed through a voltage.

The gate driver 131 may receive a gate control signal GC outputted from the timing controller 111 , generate gate driving signals G 1 and G 2 using the gate control signal GC, and output the gate driving signals G 1 and G 2 to drive the scan lines GL formed in the display panel 141 . FIG. 1 illustrates one gate driver 131 , but the display device may include a plurality of gate drivers 131 in consideration of the size and resolution of the display panel 141 .

The display panel 141 may receive the source driving signals S 1 and S 2 and the gate driving signals G 1 and G 2 from the source driver 121 and the gate driver 131 , respectively, and display an image. In the present embodiment, the display panel 141 may include pixels implemented by using OLED cells 143 . The OLED cell 143 may receive a source driving signal of a data line SL and a gate driving signal of a scan line GL, and display an image in response to an operation of the OLED.

The operation of the OLED cell 143 may be described in detail as follows. According to the gate driving signal G 1 supplied to the scan line GL, a switching thin film transistor TSF-S of the data line SL may be turned on. Then, the source driving signal S 1 supplied through the data line SL may be supplied to the gate of a driving thin film transistor TFT-O through the switching thin film transistor TFT-S. The driving thin film transistor TFT-O may be turned on by the source driving signal S 1 transmitted through the switching thin film transistor TFT-S, and apply voltages PVDD and PVSS to the organic light emitting diode OLED. As a driving current is supplied at brightness corresponding to the source driving signal S 1 , the OLED may emit light.

Since the OLED gradually deteriorates with time, the threshold voltage Vth thereof may be changed. Then, due to the change of the threshold voltage Vth, the brightness of the OLED may gradually decrease in response to the same driving current. The change in threshold voltage Vth of the OLED may be detected through a threshold-voltage-detection thin film transistor TFT-V. At this time, a threshold-voltage-detection control signal VthC for detecting the change in threshold voltage Vth of the OLED may be provided to the threshold-voltage-detection thin film transistor TFT-V in a standby state or before an image is displayed. The above-described change of the threshold voltage Vth may correspond to an example of pixel information. The pixel information such as the threshold voltage Vth of the OLED may be provided to the sample and hold circuit 220 through the turned-on threshold-voltage-detection thin film transistor TFT-V and the data line SL.

FIG. 2 illustrates a path through which pixel information is transmitted in the source driver 121 . In FIG. 2 , the pixel information is represented by V IN . The pixel information V IN of each OLED cell 143 may be provided to the sample and hold circuit 220 . The sample and hold circuit 220 may be configured to provide a signal obtained by sampling and holding the pixel information V IN and a reference signal Vref 2 to the amplifier 230 .

The sample and hold circuit 220 may receive the pixel information V IN of the OLED cell 143 of the display panel 141 , and detect whether the pixel characteristic of the display panel 141 is changed. The source driver 121 may include a plurality of sample and hold circuits 220 corresponding to the number of data lines of the display panel 141 . Output signals of the sample and hold circuits 220 may be commonly applied to the amplifier 230 .

Referring to FIG. 2 , the source driver 121 may include a plurality of sample and hold circuits 220 , the amplifier 230 , and the analog-to-digital converter 240 .

The sample and hold circuit 220 may receive the pixel information V IN of the OLED cell 143 of the display panel 141 , and detect whether the pixel characteristic of the display panel 141 is changed. The number of sample and hold circuits 220 may correspond to the number of data lines of the display panel 141 . The output signals of the sample and hold circuits 220 may be commonly applied to the amplifier 230 .

More specifically, the sample and hold circuit 220 may receive the pixel information V IN and reference voltages Vref 1 and Vref 2 , and provide output signals OUTa and OUTb.

The amplifier 230 may receive the output signals OUTa and OUTb of the sample and hold circuits 220 , and differentially amplify the output signals OUTa and OUTb.

The analog-to-digital converter 240 may be configured to convert analog signals outputted from the amplifier 230 into digital signals, and provide the digital signals to the timing controller 111 . The timing controller 111 may perform control based on the pixel characteristic, by referring to the output signals of the analog-to-digital converter 240 .

FIG. 3 is a block diagram of the sample and hold circuit 220 illustrated in FIG. 2 . Referring to FIG. 3 , the sample and hold circuit 220 may include a main sample and hold circuit 220 a , a common coupling unit 220 c , and a dummy sample and hold circuit 220 b.

The main sample and hold circuit 220 a may sample and hold the pixel information V IN of the OLED cell 143 of the display panel 141 . While the pixel information V IN is sampled and held in the main sample and hold circuit 220 a , switching noise signals may be introduced by the plurality of switching elements MSW 1 to MSW 4 of FIG. 4 , which are formed in the main sample and hold circuit 220 a . Thus, the switching noise signals may be contained in the output signal OUTa of the main sample and hold circuit 220 a.

The common coupling unit 220 c may be positioned between the main sample and hold circuit 220 a and the dummy sample and hold circuit 220 b , and commonly coupled to the main sample and hold circuit 220 a and the dummy sample and hold circuit 220 b . The common coupling unit 220 c receiving the first and second reference voltages Vref 1 and Vref 2 will be described in detail with reference to FIG. 4 .

The dummy sample and hold circuit 220 b may sample and hold the reference voltage Vref 2 . While the reference voltage Vref 2 is sampled and held in the dummy sample and hold circuit 220 b , switching noise signals may be introduced by a plurality of switching elements DSW 1 to DSW 4 of FIG. 4 , which are formed in the dummy sample and hold circuit 220 b . Thus, switching noise signals may be contained in the output signal OUTb of the dummy sample and hold circuit 220 b . The reference voltage Vref 1 may be used for resetting, and the reference voltage Vref 2 may be used for sampling and holding the pixel information V IN . The reference voltages Vref 1 and Vref 2 may be set to have a lower level than the pixel information V IN . For example, the reference voltage Vref 2 may be set to a ground voltage, and the reference voltage Vref 1 may be set to a voltage having a higher level than the ground voltage and a lower level than the pixel information.

The dummy sample and hold circuit 220 b may have the same circuit structure as the main sample and hold circuit 220 a . Furthermore, the switching elements DSW 1 to DSW 4 of the dummy sample and hold circuit 220 b may be driven in synchronization with the switching elements MSW 1 to MSW 4 of the main sample and hold circuit 220 a.

Thus, the switching noise signal generated in the dummy sample and hold circuit 220 b may have the same level as or a similar level to the switching noise signal generated in the main sample and hold circuit 220 a.

The amplifier 230 of FIG. 2 may include a non-inverting input terminal (+) and an inverting input terminal (−), receive the output signal OUTa of the main sample and hold circuit 220 a through the non-inverting input terminal (+), and receive the output signal OUTb of the dummy sample and hold circuit 220 b through the inverting input terminal (−). Thus, the output signal OUTa of the main sample and hold circuit 220 a may be attenuated by the output signal OUTb of the dummy sample and hold circuit 220 b . That is, the switching noise signal contained in the output signal OUTa of the main sample and hold circuit 220 a may be offset and reduced or eliminated by the switching noise signal of the output signal OUTb outputted from the dummy sample and hold circuit 220 b . Thus, the signal outputted from the amplifier 230 of FIG. 2 may not contain the switching noise signal generated in the sample and hold circuit 220 . The amplifier 230 of FIG. 2 may be implemented with an operational amplifier having differential input terminals.

As described above, the sample and hold circuit 220 in accordance with the embodiment of the present invention may include the dummy sample and hold circuit 220 b having the same structure as the main sample and hold circuit 220 a which samples and holds the pixel information V IN transmitted from the display panel 141 , in order to eliminate the switching noise signals generated in the main sample and hold circuit 220 a . Therefore, the output signal of the amplifier 230 may be stably outputted as a stable signal containing no noise.

FIG. 4 is a circuit diagram of the sample and hold circuit 220 illustrated in FIG. 2 , and a detailed circuit diagram of FIG. 3 .

The main sample and hold circuit 220 a may include first to third main switching elements MSW 1 to MSW 3 , a main sampling capacitor Csm, a main charge sharing unit MCS, and a main reset unit MRS.

The first and third main switching elements MSW 1 and MSW 3 may include transmission gates, and the second main switching element MSW 2 may include a MOS (metal oxide semiconductor) transistor.

The main sampling capacitor Csm may be coupled between the common coupling unit 220 c and a coupling node MN 1 for the first and second switching elements MSW 1 and MSW 2 . The main sampling capacitor Csm may sample the pixel information V IN outputted from the first main switching element MSW 1 when the first main switching element MSW 1 is turned on. When the first main switching element MSW 1 for transmitting the pixel information V IN is turned on or off, a switching noise signal may be introduced from the first switching element MSW 1 . The switching noise signal and the pixel information V IN may be sampled together in the main sampling capacitor Csm.

The main charge sharing unit MCS may be coupled between the common coupling unit 220 c and a coupling node MN 2 for the second and third main switching elements MSW 2 and MSW 3 . The main charge sharing unit MCS may share the voltage sampled in the main sampling capacitor Csm. When the second main switching element MSW 2 is turned on, electric charges sampled in the main sampling capacitor Csm may be shared by the main charge sharing unit MCS through the second main switching element MSW 2 . Thus, the voltage of the main sampling capacitor Csm may decrease. The main charge sharing unit MCS may include a fourth main switching element MSW 4 , a first main charge sharing capacitor Ccsm 1 , and a second main charge sharing capacitor Ccsm 2 .

The fourth main switching element MSW 4 may be coupled between the first main charge sharing capacitor Ccsm 1 and a coupling node MN 2 for the second and third main switching elements MSW 2 and MSW 3 .

The first main charge sharing capacitor Ccsm 1 may be coupled between the fourth main switching element MSW 4 and the common coupling unit 220 c . The first main charge sharing capacitor Ccsm 1 may share the voltage sampled in the main sampling capacitor Csm. That is, when the second and fourth main switching elements MSW 2 and MSW 4 are turned on, the electric charges sampled in the main sampling capacitor Csm may be shared by the first main charge sharing capacitor Ccsm 1 through the second and fourth main switching elements MSW 2 and MSW 4 . Thus, the voltage of the main sampling capacitor Csm may decrease. At this time, while the second and fourth main switching element MSW 2 and MSW 4 are turned on or off, switching noise signals may be introduced from the second and fourth main switching elements MSW 2 and MSW 4 . The switching noise signals and the pixel information V IN may be sampled together in the first main charge sharing capacitor Ccsm 1 .

The second main charge sharing capacitor Ccsm 2 may be coupled between the common coupling unit 220 c and the coupling node MN 2 for the second and third switching elements MSW 2 and MSW 3 . The second main charge sharing capacitor Ccsm 2 may share the voltage sampled in the main sampling capacitor Csm. That is, when the second main switching element MSW 2 is turned on, the electric charges sampled in the main sampling capacitor Csm may be shared by the second main charge sharing capacitor Ccsm 2 through the second main switching element MSW 2 . Thus, the voltage of the main sampling capacitor Csm may decrease. At this time, while the second main switching element MSW 2 is turned on or off, a switching noise signal may be introduced from the second main switching element MSW 2 . The switching noise signal may be sampled in the second main charge sharing capacitor Ccsm 2 .

According to the number of first and second main charge sharing capacitors Ccsm 1 and Ccsm 2 formed in the main charge sharing unit MCS, the voltage sharing ratio of the main sampling capacitor Csm may differ. For example, when the main sampling capacitor Csm has the same capacity as the first and second main charge sharing capacitors Ccsm 1 and Ccsm 2 , the voltage of the main sampling capacitor Csm may decrease to the half in case where only one of the first and second main charge sharing capacitors Ccsm 1 and Ccsm 2 is included in the main charge sharing unit MCS, and decrease to ⅓ in case where both of the first and second main charge sharing capacitors Ccsm 1 and Ccsm 2 are included in the main charge sharing unit MCS. Thus, when a sensing voltage range for the pixel information V IN inputted to the sample and hold circuit 220 is wide, the number of main charge sharing capacitor may be properly adjusted.

That is, the main charge sharing unit MCS of FIG. 4 may include one or more first main charge sharing capacitors Ccsm 1 . At this time, a switching element coupled to the first main charge sharing capacitor Ccsm 1 may be turned on or off to adjust the voltage sharing ratio of the main sampling capacitor Csm.

The main reset unit MRS may be coupled between the common coupling unit 220 c and the coupling node MN 2 for the second and third main switching elements MSW 2 and MSW 3 , and reset the first and second main charge sharing capacitors Ccsm 1 and Ccsm 2 . The main reset unit MRS may include a MOS transistor. Thus, when the MOS transistor forming the main reset unit MRS is turned on, both of the first and second main charge sharing capacitors Ccsm 1 and Ccsm 2 may be discharged to the level of the reference voltage Vref 1 applied to the common coupling unit 220 c.

The third main switching element MSW 3 may be coupled to the output terminal of the sample and hold circuit 220 . Thus, when the third main switching element MSW 3 is turned on, the voltage sampled in the main sampling capacitor Csm may be outputted from the sample and hold circuit 220 and transmitted to the amplifier 230 of FIG. 2 .

The dummy sample and hold circuit 220 b may have the same circuit structure as the main sample and hold circuit 220 a . Furthermore, the switching elements DSW 1 to DSW 4 of the dummy sample and hold circuit 220 b may be driven in synchronization with the switching elements MSW 1 to MSW 4 of the main sample and hold circuit 220 a . Thus, the switching noise signal generated in the dummy sample and hold circuit 220 b may have the same level as or a similar level to the switching noise signal generated in the main sample and hold circuit 220 a.

The dummy sample and hold circuit 220 b may include first to third dummy switching elements DSW 1 to DSW 3 , a dummy sampling capacitor Csd, a dummy charge sharing unit DCS, and a dummy reset unit DRS.

The first and third dummy switching elements DSW 1 and DSW 3 may include transmission gates, and the second dummy switching element DSW 2 may include a MOS transistor.

The dummy sampling capacitor Csd may be coupled between the common coupling unit 220 c and a coupling node DN 1 for the first and second dummy switching elements DSW 1 and DSW 2 . The dummy sampling capacitor Csd may sample the voltage generated from the first dummy switching element DSW 1 when the first dummy switching element DSW 1 is turned on or off. That is, when the first dummy switching element DSW 1 is turned on or off, a switching noise signal may be generated from the first dummy switching element DSW 1 , and sampled in the dummy sampling capacitor Csd. As the reference voltages Vref 1 and Vref 2 are applied to both ends of the dummy sampling capacitor Csd, the switching noise signal generated from the first dummy switching element DSW 1 may be sampled in the dummy sampling capacitor Csd.

The dummy charge sharing unit DCS may be coupled between the common coupling unit 220 c and a coupling node DN 2 for the second and third dummy switching elements DSW 2 and DSW 3 . The dummy charge sharing unit DCS may receive the voltage outputted from the second dummy switching element DSW 2 and sample the received voltage, when the second dummy switching element DSW 2 is turned on or off. That is, when the second dummy switching element DSW 2 is turned on or off, a switching noise signal may be generated from the second dummy switching element DSW 2 , and sampled in the dummy charge sharing unit DCS. As the reference voltages Vref 1 and Vref 2 are applied to both ends of the dummy charge sharing unit DCS, the switching noise signal generated from the second dummy switching element DSW 2 may be sampled in the dummy charge sharing unit DCS. The dummy charge sharing unit DCS may include a fourth dummy switching element DSW 4 , a first dummy charge sharing capacitor Ccsd 1 , and a second dummy charge sharing capacitor Ccsd 2 .

The fourth dummy switching element DSW 4 may be coupled between the first dummy charge sharing capacitor Ccsd 1 and the coupling node DN 2 for the second and third dummy switching elements DSW 2 and DSW 3 , and include a MOS transistor.

The first dummy charge sharing capacitor Ccsd 1 may be coupled between the fourth dummy switching element DSW 4 and the common coupling unit 220 c . The first dummy charge sharing capacitor Ccsd 1 may sample switching noise signals generated from the second and fourth dummy switching elements DSW 2 and DSW 4 . That is, while the second and fourth dummy switching elements DSW 2 and DSW 4 are turned on or off, switching noise signals may be generated from the second and fourth dummy switching elements DSW 2 and DSW 4 , and sampled in the first dummy charge sharing capacitor Ccsd 1 .

The second dummy charge sharing capacitor Ccsd 2 may be coupled between the common coupling unit 220 c and the coupling node DN 2 for the second and third switching elements DSW 2 and DSW 3 . The second dummy charge sharing capacitor Ccsd 2 may sample a switching noise signal generated from the second dummy switching element DSW 2 . That is, while the second dummy switching element DSW 2 is turned on or off, a switching noise signal may be generated from the second dummy switching element DSW 2 , and sampled in the second dummy charge sharing capacitor Ccsd 2 .

The number of dummy charge sharing capacitors Ccsd 1 and Ccsd 2 formed in the dummy charge sharing unit DCS may be set to be equal to the number of main charge sharing capacitors Ccsm 1 and Ccms 2 formed in the main charge sharing unit MCS.

The dummy reset unit DCS may be coupled between the common coupling unit 220 c and the coupling node DN 2 for the second and third dummy switching elements DSW 2 and DSW 3 , and reset the first and second dummy charge sharing capacitors Ccsd 1 and Ccsd 2 . The dummy reset unit DRS may include a MOS transistor. Thus, when the MOS transistor forming the dummy reset unit DRS is turned on, both of the first and second dummy charge sharing capacitors Ccsd 1 and Ccsd 2 may be discharged to the level of the reference voltage Vref 1 applied to the common coupling unit 220 c.

The third dummy switching element DSW 3 may be coupled to the output terminal of the sample and hold circuit 220 . Thus, when the third dummy switching element DSW 3 is turned on, the voltage sampled in the dummy sampling capacitor Csd may be outputted from the sample and hold circuit 220 and transmitted to the amplifier 230 of FIG. 2 .

The common coupling unit 220 c may be formed between the main sample and hold circuit 220 a and the dummy sample and hold circuit 220 b , and couple the main sample and hold circuit 220 a and the dummy sample and hold circuit 220 b to each other. The common coupling unit 220 c may include a first common switching element CSW 1 , a second common switching element CSW 2 , and a reference line Lref. The first and second common switching elements CSW 1 and CSW 2 of the common coupling unit 220 c may be driven in synchronization with the first and second main switching elements MSW 1 and MSW 2 of the main sample and hold circuit 220 a and the first and second dummy switching elements DSW 1 and DSW 2 of the dummy sample and hold circuit 220 b.

The first switching element CSW 1 may include a transmission gate, and the second switching element CSW 2 may include a MOS transistor.

Both of the first and second common switching elements CSW 1 and CSW 2 may be coupled to the reference line Lref, and the main sample and hold circuit 220 a and the dummy sample and hold circuit 220 b may be commonly coupled to the reference line Lref.

The second reference voltage Vref 2 may be applied to the first common switching element CSW 1 , and the first reference voltage Vref 1 may be applied to the second common switching element CSW 2 . Thus, the first and second common switching elements CSW 1 and CSW 2 may not be turned on at the same time. That is, when the first common switching element CSW 1 is turned on, the second common switching element CSW 2 may be turned off. On the other hand, when the second common switching element CSW 2 is turned on, the first common switching element CSW 1 may be turned off.

The reference voltage Vref 1 may be used for resetting, and the reference voltage Vref 2 may be used for sampling and holding the pixel information V IN . The reference voltages Vref 1 and Vref 2 may be set to have a lower level than the pixel information V IN . For example, the reference voltage Vref 2 may be set to the ground voltage, and the reference voltage Vref 1 may be set to a voltage having a high level than the ground voltage and a lower level than the pixel information.

In accordance with the embodiments of the present invention, the sample and hold circuit may include the main sample and hold circuit configured to sample and hold pixel information and the dummy sample and hold circuit having the same structure as the main sample and hold circuit. The dummy sample and hold circuit may generate a signal for offsetting a switching noise signal introduced during the sampling and holding process of the main sample and hold circuit.

The source driver including the dummy sample and hold circuit to drive the display panel may precisely process signals transmitted from the plurality of pixels formed in the display panel.

Thus, the source driver including the dummy sample and hold circuit may precisely detect the characteristic information of the pixels formed in the display panel.

Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the invention as disclosed in the accompanying claims.