Zero current detector and DC-DC converter using same

This application claims priority to Taiwanese Patent Application No. 102134779 filed on Sep. 26, 2013, the contents of which are incorporated by reference herein.

The disclosure generally relates to a zero current detector and a DC-DC converter having the zero current detector.

A DC-DC converter supplies power for a microprocessor or a memory. When the DC-DC converter works in a discontinuous conduction mode (DCM), an inductor generates a reverse current. The reverse current makes additional power consumption.

Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.

FIG. 1 is a block diagram of a DC-DC converter having a zero current detector according to one embodiment.

FIG. 2 is a diagrammatic view of the zero current detector of FIG. 1 .

FIG. 3 is a graph showing an inductor current and a voltage of a detection node when the DC-DC converter of FIG. 1 is in discontinuous conduction mode (DCM)

It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the embodiments described herein.

The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected.

FIG. 1 shows a block diagram of a DC-DC converter 10 according to one embodiment. The DC-DC converter 10 can include a driver 102 , a high-side switch 104 , a low-side switch 106 , an inductor 108 , a capacitor 110 , a load RL, and a power output terminal VOUT. The driver 102 can switch the high-side switch 104 and the low-side switch 106 on or off. In one embodiment, the high-side switch 104 is a P-metal oxide semiconductor (PMOS) transistor; the low-side switch 106 is an N-metal oxide semiconductor (NMOS) transistor. A source of the high-side switch 104 is coupled to a voltage source VDD. A drain of the high-side switch 104 is coupled to a drain of the low-side switch 106 . A source of the low-side switch 106 is grounded. A gate of the high-side switch 104 and a gate of the low-side switch 106 are coupled to the driver 102 . A node between the drain of the high-side switch 104 and the drain of the low-side switch 106 is a detection node LX. The detection node LX is coupled to the load RL via the inductor 108 and the power output terminal VOUT. The inductor 108 is grounded via the capacitor 110 . The DC-DC converter 10 can further include a zero current detector 120 coupled between the detection node LX and the driver 102 .

When the DC-DC converter 10 works in a discontinuous conduction mode (DCM), the zero current detector 120 detects a zero current of the detection node LX. In other words, the zero current detector 120 detects a reverse current Ir (as shown in FIG. 1 ), when the high-side switch 104 is turned off and the low-side switch 106 is turned on. When the zero current generates, the zero current detector 120 outputs an indicating signal to the driver 102 to switch the low-side switch 106 off.

FIG. 2 shows a diagramatic view of the zero current detector 120 . The zero current detector 120 can include a bias current source 122 , a current mirror 124 , a zero current detection unit 126 , and a temperature compensation unit 128 . The current mirror 124 can include an input terminal VIN, a first PMOS transistor M 1 , a second PMOS transistor M 2 , a third PMOS transistor M 3 , a fourth PMOS transistor M 4 , a first output terminal V 1 , a second output terminal V 2 , and a third output terminal V 3 . The bias current 122 is coupled to the input terminal VIN and supplies a direct bias current IB to the input terminal VIN. The gates of the first, second, third, and fourth PMOS transistor M 1 , M 2 , M 3 , and M 4 are coupled to the input terminal VIN. A drain of the first PMOS transistor M 1 is coupled to the input terminal VIN. The sources of the first, second, third, and fourth PMOS transistor M 1 , M 2 , M 3 , and M 4 are coupled to the voltage source VDD. The drain of the second PMOS transistor M 2 serves as the first output terminal V 1 , the drain of the third PMOS transistor M 3 serves as the second output terminal V 2 , the drain of the fourth PMOS transistor M 4 serves as the third output terminal V 3 . As the function of the current mirror 124 , the current of the first and second output terminal V 1 , V 2 , and V 3 is also IB. A voltage of the detection node LX is denoted as VLX.

The zero current detection unit 126 can include a first transistor Q 1 , a second transistor Q 2 , a first resistor R 1 , a second resistor R 2 , and a first comparator CM 1 . The first output terminal V 1 is grounded via the first transistor Q 1 and the first resistor R 1 . The second transistor Q 2 and the second resistor R 2 are coupled between the output terminal V 2 and the detection node LX in series. The first comparator CM 1 can include an inverting input terminal V−, a non-inverting input terminal V+, and a first comparison output terminal Cout 1 . The inverting input terminal V− is coupled to the first output terminal V 1 , the non-inverting input terminal V+ is coupled to the second output terminal V 2 , and the first comparison output terminal Cout 1 is coupled with the driver 102 .

In the one embodiment, the first and second transistors Q 1 and Q 2 are NPN bipolar transistors which can be configured in diode-connected fashion. The first comparator CM 1 has a high speed and low input offset. A base and a collector of the first transistor Q 1 are coupled to the first output terminal V 1 , and an emitter of the first transistor Q 1 is grounded via the first resistor R 1 . A base and a collector of the second transistor Q 2 are coupled to the second output terminal V 2 , and an emitter of the second transistor Q 2 is coupled to the detection node LX via the second resistor R 2 . In one embodiment, the first and second transistors Q 1 and Q 2 are diodes, and anodes of the diodes are respectively coupled to the first and second output terminals V 1 and V 2 , cathodes of the diodes are coupled to the first and second resistors R 1 and R 2 .

A voltage level of the inverting input terminal V− of the first comparator CM 1 is IB*R 1 0 +VBE Q1 , wherein R 1 0 denotes a resistance of the first resistor R 1 , VBE Q1 denotes a forward conductive voltage of the first transistor Q 1 . A voltage level of the non-inverting input terminal V+ of the first comparator CM 1 is IB*R 2 0 +VBE Q2 +VLX, wherein R 2 0 denotes a resistance of the second resistor R 2 , VBE Q2 denotes a forward conductive voltage of the second transistor Q 2 .

The temperature compensation unit 128 can include a first NMOS transistor ME 1 , a second comparator CM 2 , and a third transistor Q 3 . A drain of the first NMOS transistor ME 1 is coupled to the second output terminal V 2 and a source of the first NMOS transistor ME 1 is grounded. The second comparator CM 2 can include a non-inverting input terminal V+, an inverting input terminal V−, and a second comparison output terminal Cout 2 . The non-inverting input terminal V+ of the second comparator CM 2 is coupled to the second output terminal V 2 . The inverting input terminal V− of the second comparator CM 2 is coupled to a base of the third transistor Q 3 . The second comparison output terminal Cout 2 is coupled to a gate of the first NMOS transistor ME 1 . The base of the third transistor Q 3 is coupled to a collector of the third transistor Q 3 . The collector of the third transistor Q 3 is grounded via a third resistor. A voltage of the inverting input terminal V− of the second comparator CM 2 is Vref=IB*R 3 0 +VBE Q3 , wherein R 3 0 denotes a resistance of the third resistor R 3 , VBE Q3 denotes a forward conductive voltage of the third transistor Q 3 .

FIG. 3 illustrates a graph of an inductor current IL and a voltage of a detection node VLX when the DC-DC converter of FIG. 1 is in discontinuous conduction mode (DCM) which is light load. During a first period T 1 , the driver 102 switches the high-side switch 104 on and the low-side switch 10 off. The inductor 108 is charged and power is supplied to the load RL via the power output terminal VOUT. The voltage VLX of the detection node LX is positive. The voltage level of the inverting input terminal V− of the first comparator CM 1 is lower than the voltage level of the non-inverting input terminal V+ of the first comparator CM 1 , the first comparison output terminal Cout 1 outputs a first control signal to the driver 102 . The driver 102 switches the high-side switch 104 on and the low-side switch 106 off under control of the first control signal. The zero current detector 120 does not work.

During a second period T 2 , the driver 102 switches the high-side switch 104 off and the low-side switch 106 on, the inductor 108 discharges and power is supplied to the load RL via the power output terminal VOUT. The voltage VLX of the detection node LX is negative. The voltage level of the inverting input terminal V− of the first comparator CM 1 is larger than the voltage level of the non-inverting input terminal V+ of the first comparator CM 1 , the first comparison output terminal Cout 1 outputs a second control signal to the driver 102 . The driver 102 switches the high-side switch 104 on and the low-side switch 106 off under control of the second control signal.

During a period T 3 , the detection node LX generates the zero current and the voltage VLX of the detection node LX is zero simultaneously, the voltage level of the non-inverting input terminal V+ of the first comparator CM 1 is larger than the voltage level of the inverting input terminal V− of the first comparator CM 1 , the first comparison output terminal Cout 1 outputs a third control signal to the driver 102 . The driver 102 switches the high-side switch 104 and the low-side switch 106 off simultaneously to suppress the reverse current Ir. Thus, a conversion efficiency of the DC-DC converter 10 is improved.

In the embodiment, a detection value of the reverse current is changed by changing resistance of the first resistor R 1 and the second resistor R 2 . The first resistor R 1 and the second resistor R 2 are high-resistance value resistors, when electrostatic discharge applies in the detection node LX, the first resistor R 1 and the second resistor R 2 protect the zero current detector 102 from the electrostatic discharge.

When the DC-DC converter 10 switches to DCM from continuous conduction mode (CCM) which is heavy load mode, the voltage of the detection node LX increases, the voltage level of the non-inverting input terminal V+ of the first comparator CM 1 increases.

In the embodiment, the first, second, and third transistors Q 1 , Q 2 , and Q 3 are NPN bipolar transistors. The first, second, and third transistors Q 1 , Q 2 , and Q 3 are made of same material and have temperature coefficient. The first, second, and third resistors R 1 , R 2 , and R 3 are made of same material and have temperature coefficient. As junction voltage of the NPN transistor has a negative temperature coefficient, when temperature of the NPN transistor rises in operation, the forward conductive voltage VBE Q1 of the first transistor Q 1 reduces to decrease the voltage level of the inverting input terminal V− of the first comparator CM 1 . Thus, a voltage difference between the non-inverting input terminal V+ and the inverting input terminal V− increases to decrease the responsivity of the first comparator CM 1 .

When the voltage level of the non-inverting input terminal V+ of the first comparator CM 1 is larger than the reference voltage Vref, the second comparison output terminal Cout 2 outputs a control signal to turn on the first NMOS transistor ME 1 . The first NMOS transistor ME 1 clamps the voltage level of the non-inverting input terminal V+ with the reference voltage Vref. The voltage of the non-inverting input terminal V+ is limited in a predetermined range by adjusting the reference voltage. The voltage difference between the voltage of the non-inverting input terminal V+ of the first comparator CM 1 and the voltage of the inverting input terminal V− of the first comparator CM 1 is controlled within a predetermined range to increase the responsivity of the first comparator CM 1 . In the embodiment, the control signal is a logic high signal. The voltage Vref of the inverting input terminal V− of the second comparator CM 2 is adjusted automatically along temperature change. In detail, the voltage Vref of the inverting input terminal V− of the second comparator CM 2 decreases along the temperature rises; the voltage Vref of the inverting input terminal V− of the second comparator CM 2 increases along the temperature decreases. The responsivity of the first comparator CM 1 is not influenced by the temperature.

When the DC-DC converter 10 works in CCM, the voltage of the non-inverting input terminal V+ is remained by adjusting the resistance of the third resistor R 3 to adjust the voltage Vref, thus the DC-DC converter 10 can work normally.

In summary, the DC-DC converter 10 includes the zero current detector 120 to detect the zero current of the reverse current, and when the detection node LX generates the zero current, the zero current detector outputs the control signal to the driver. The driver 102 switches the high-side switch 104 and the low-side switch 106 off simultaneously according to the control signal to improve conversion efficiency of the DC-DC converter. Further, when the DC-DC converter 10 switches to DCM from continuous conduction mode (CCM) which is heavy load mode, the responsivity of the first comparator CM 1 is improved by adjusting the reference voltage which is adjusted automatically along the temperature to limit the voltage of the non-inverting input terminal V+ in the predetermined range.

It is to be understood that even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description, with details of the structures and functions of the embodiments, the disclosure is illustrative only and changes may be in detail, especially in the matter of arrangement of parts within the principles of the embodiments, to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.