Transistor devices and methods

The present disclosure relates to semiconductor devices and methods, and in particular, to transistor devices and methods.

Performance demands on electronic circuits continue to escalate. A basic building block of nearly all electronic circuits is the transistor. As transistors are operated at even increasing speeds, parasitic effects inside the devices become increasing problematic. For example, as current flow through terminals of a transistor device, internal resistances may cause voltage drops that can dissipate power and reduce the efficiency of the circuit. Such internal resistance can place limits on the size of devices used in particular applications due to the voltage drop. Many applications require transistors that can deliver large amounts of current at very high speeds. At the same time, in order to manage high power levels, the transistors must be able to manage high voltages. Existing solutions for reducing these parasitic effects and for managing high current and high voltage are not optimal for meeting the increasing demands of the electronics industry.

The present disclosure includes transistor devices and methods. In one embodiment, a transistor includes a gate, a source, and a drain. According to one aspect of the disclosure, delays caused by different resistive paths in the drain are compensated using different gate-to-drain capacitances. According to another aspect of the disclosure, current enters a drain finger at a center tap point and flows symmetrically outward under two adjacent gates to two adjacent sources.

The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present disclosure.

FIG. 1 illustrates transistor according to one embodiment.

FIG. 2A illustrates a model of parasitic resistance in a transistor according to one embodiment.

FIG. 2B illustrates a compensation technique for parasitic resistance according to one embodiment.

FIG. 3 illustrates an example transistor with backend compensation according to one embodiment.

FIG. 4 illustrates tapered compensation according to one embodiment.

FIG. 5 illustrates tapered compensation according to another embodiment.

FIG. 6 illustrates a model of parasitic resistance and capacitance in a transistor according to one embodiment.

The present disclosure pertains to transistor devices and methods. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

FIG. 1 illustrates an example transistor 100 according to one embodiment. In this example, transistor 100 is a metal oxide semiconductor field effect transistor (MOSFET). Transistor 100 includes a drain 110 , a gate 120 A-B, and a source 130 A-B. In this example, the source and gate comprise two structures 120 A and 120 B on opposite sides 110 A and 110 B of drain 110 . In particular, drain 110 comprises a length Ld and a width Wd. The source comprises a first source finger 130 A arranged in parallel with the length, Ld, of the drain 110 on a first side 110 A of drain 110 and a second source finger 130 B arranged in parallel with the length of drain 110 on a second side 110 B of drain 110 . The gate of transistor 100 comprises a first gate finger 120 A arranged in parallel with the length of drain 110 between the first side 110 A of the drain and the first source finger 130 A and a second gate finger 120 B arranged in parallel with the length of the drain 110 between the second side 110 B of the drain and the second source finger 130 B.

Features and advantages of the present disclosure include a center tap 101 on drain 110 . A conductive material 180 (dashed line) may be arranged vertically above drain 110 and in electrical contact with the drain at the center tap 101 located at a midpoint (e.g., Ld/ 2 ) of the length, Ld, of drain 110 , for example. Conductive material 180 may be a backend (BE) metal layer, for example. Accordingly, current may flow to drain 101 from BE 180 along current paths 150 A-F. As current flows along each path, the current encounters a parasitic resistance in the drain and/or source. Accordingly, paths 150 A-F are also referred to herein as resistive paths.

In this example, current flows into drain 110 at center tap 101 , across a channel 152 under gates 120 A-B, and out both ends of source 130 A along paths 150 E and 150 F and out both ends of source 130 B along paths 150 A and 150 B. For current 151 A flowing out of a first end of source 130 A, the current may traverse a variety of paths along half of drain 110 , across the channel under gate 120 A, and along half of source 130 A. For example, current may flow into center tap 101 and directly from drain 110 to source 130 A. In this case, current may experience a resistive path including a negligible drain resistance (from the center tap to the channel region) and a large source resistance along half the length of the source. Alternatively, current may flow into center tap 101 , along a portion of drain 110 , across the channel to source 130 A, and along a portion of source 130 A. In this case, current may experience a resistive path including a larger drain resistance (from the center tap to a point between the center and end of the drain) and a lower source resistance along less than half the length of the source. This path is illustrated at 151 , for example. Similarly, current may flow into center tap 101 to an end of drain 110 , across the channel to an end of source 130 A. In this case, current may experience a resistive path including the largest drain resistance (from the center tap to the end of the drain) and the smallest source resistance (out the end of the source), which may be negligible.

Of course, a continuum of such current and resistive paths may exist as current flows into center tap 101 , along various sections of the drain, across the channel, and along various lengths of the source. For example, current 151 B may likewise flow into center tap 101 , toward the other end of drain 110 along current and resistive path 150 D, across the channel to source 130 A, and along current and resistive path 150 F. Similarly, current 151 C may flow into center tap 101 , toward the end of drain 110 along current and resistive path 150 C, across the channel to source 130 B, and along current and resistive path 150 A. Finally, current 151 D may flow into center tap 101 , toward the end of drain 110 along current and resistive path 150 D, across the channel to source 130 B, and along current and resistive path 150 B.

FIG. 2A illustrates a model of parasitic resistance in a transistor according to one embodiment. In this example, transistor 100 of FIG. 1 is modeled as a circuit. From the above description it can be seen that transistor 100 may be divided into three parallel transistors with different resistive/current paths along a center region, center to edge region, and edge region. A center region of transistor 100 may be modeled as a first transistor 200 A having a drain resistance (Rd 1 ) 260 and source resistance (Rs 1 ) 261 . A center to edge region may be modeled as a second transistor 200 B having a drain resistance (Rd 2 ) 262 and source resistance (Rs 2 ) 263 . An edge region may be modeled as a third transistor 200 C having a drain resistance (Rd 3 ) 264 and source resistance (Rs 3 ) 265 , for example. Each transistor 200 A-C has a common gate 220 , drain 210 , and source 220 , for example. It is to be understood that transistor 100 may be modeled using fewer or additional parallel transistors, for example.

The parasitic resistances along each resistive path may be different. As mentioned above, for a center region, transistor 200 A may have a small drain resistance and a large source resistance. For a center-to-edge region, transistor 200 B may have a similar sized drain resistance and source resistance. For an edge region, transistor 200 A may have a large drain resistance and a small source resistance. One example advantage of a center tap 101 in the example shown in FIG. 1 is that the current and resistive paths are symmetric across four quadrants of the device, thereby producing balanced drain-to-source resistive paths. Accordingly, both paths for top and bottom end regions for drain 110 , gate 120 A-B, and sources 130 A-B may be combined into a single model, paths for top and bottom center-to-end regions for drain 110 , gate 120 A-B, and sources 130 A-B may be combined into a single model, and paths for top and bottom center regions for drain 110 , gate 120 A-B, and sources 130 A-B may be combined into a single model.

FIG. 2B illustrates a compensation technique according to one embodiment. Another aspect of the present disclosure pertains to compensating delay caused by parasitic resistance in a transistor. For example, FIG. 2 illustrates a circuit 200 B to compensate for different delays along the parasitic drain resistive paths of transistor 200 according to one embodiment. In this example, a capacitance 261 is provided between the gate 220 and drain 210 to form an RC circuit with drain resistance 260 . Embodiments of the present disclosure include a capacitance that varies across a length of the drain to compensate for corresponding variations between different resistive paths along the drain, for example. In some embodiments, a conductive material (e.g., backend metal 180 in FIG. 1 ) may produce a gate to drain capacitance. As described in more detail below, the conductive material may be varied across the length of the drain to produce different gate-to-drain capacitances that compensate for different drain resistances along the length of the drain.

FIG. 3 illustrates an example transistor with backend compensation according to one embodiment. In this example, a transistor is formed on a silicon-on-insulator substrate including a silicon substrate 398 and buried oxide (BOX) 397 . The transistor includes a heavily doped n+ drain 310 , gates 320 A-B and heavily doped n+ sources 330 A-B. The transistor device may include a shallow trench isolation (STI) 305 A-B, Ndrift regions 302 A-B, depletion regions 304 A-B, and p-type well (PW) region 303 A-B. In this example, a metallization layer (M 1 ) 301 forms a center tap connection to drain 310 . M 1 is coupled to another metallization layer (M 2 ) 380 through a via 390 . Likewise, M 2 is coupled to a third metallization layer (M 3 ) 399 through vias 391 and 392 .

Embodiments of the present disclosure may vary the width of a backend layer (e.g., M 2 ) to change the gate-to-drain capacitance at different points along the length of a drain. As illustrated in FIG. 3 , M 2 380 is electrically connected to drain 310 . M 2 is also in proximity to gate 320 A-B with a non-conductive material 377 between M 2 and the gate. The proximity of the gate and M 2 produces a gate-to-drain capacitance, Cgd, for example. As illustrated at 381 A-B, the position of each end of M 2 may be different at different points along the drain so that different points of the drain have different values for Cgd. In one embodiment, the width of M 2 is modified so that both gates have the same Cgd at the same point on the drain. As illustrated here, the width of M 2 may be different at different points along the drain to produce different overlaps with the gate and correspondingly different values of Cgd. Widths 381 A-B illustrate that at some points M 2 may overlap all, or nearly all, of the gate for a larger values Cgd, and at other points along the length of the drain M 2 may not overlap the gate at all for smaller values of Cgd.

The example transistor shown in FIG. 3 may be a high voltage MOS device (HVMOS), an extended drain MOS device (EDMOS), or a laterally diffused MOS device (LDMOS). High voltage devices sometimes suffer from high electric field gradients, for example, in the Ndrift-PW interface. M 2 may form a field plate to reduce stress along the device fingers, for example. In this example, backend metal M 2 is patterned on the drain to allow a voltage balance along the finger. Contrary to traditional approaches, which exploit a gate field plate designed to reduce electric field effects, embodiments of the present disclosure tap the drain at the center for reduced path loss and a controllable gate-to-drain capacitance to maintain a constant drain to gate delay over the finger width, for example. Furthermore, a drain field plate is often avoided as it induces charge at the surface reducing the depletion and providing early BV. However, in a thin silicon-on-insulator (SOI) application, the usage of a M 2 backend metal, for example, as field plate will not reduce the breakdown voltage because the Ndrift is already fully depleted.

Additionally, patterning the drain metallization M 2 over the length of the finger, and partially covering the gate in some embodiments, allows for modulation of the capacitive coupling between drain and gate. In one example embodiment, M 2 is decreased from the highest drain voltage point (the center of the finger) toward the edge of the finger (e.g., top and bottom of drain 110 in FIG. 1 ). This capacitive effect, while potentially reducing gain, may bootstrap the gate voltage where the drain voltage is higher, may normalize the voltage stress across the finger width, for example. Accordingly, embodiments of M 2 may be patterned to allow a balanced drain-to-gate delay corresponding to an RC time constant over the length of the drain finger, allowing for the exploitation of very long finger widths in some example applications.

FIG. 4 illustrates tapered compensation according to one embodiment. In this example, a BE metal layer M 2 is configured such that a taper is wider at a midpoint of the length of the drain and narrows toward endpoints of the length of the drain. In one implementation, the taper comprises stepwise changes in the width of the conductive material along the length of the drain. For example, M 2 at 481 A may be the widest, where M 2 overlaps the gate on both sides of the drain. However, M 2 at 481 B, adjacent to two sides of M 2 at 481 A, is narrower and overlaps less of the gate on both sides of the drain than M 2 at 481 A. Similarly, M 2 at 481 C may be the narrowest, where M 2 may overlap the gate on both sides of the drain the least (or not at all, for example). M 2 at 481 C, adjacent to two sides of M 2 at 481 B, is narrower and overlaps less of the gate on both sides of the drain than M 2 at 481 B. It is to be understood that fewer or more steps in a stepwise taper could be used in other embodiments, for example.

FIG. 5 illustrates tapered compensation according to another embodiment. In this example, a BE metal layer M 2 581 is configured such that a taper is wider at a midpoint of the length of the drain and narrows toward endpoints of the length of the drain. In one implementation, the taper of M 2 581 comprises a linear change in the width of the conductive material along the length of the drain. For example, at the center point of the drain (e.g., Ld/ 2 ), M 2 may have a maximum width 582 . M 2 may taper linearly toward each end of the drain toward a minimum width 583 . Accordingly, as the resistive path increases, the gate-to-drain capacitance is decreased to compensate for changes in drain voltage and maintain approximately the same RC time constant, for example.

FIG. 6 illustrates a model of parasitic resistance and capacitance in a transistor according to one embodiment. In this example, a single transistor is modeled as three parallel transistors 610 - 612 . Transistor 610 corresponds to an MOS structure near the center tap, and may have a low drain resistance relative to the other devices due to the short resistive path in the drain. Transistor 611 corresponds to an MOS structure in a region between the center tap and edges, and may have a higher drain resistance than the center device 610 , for example, due to the longer resistive path in the drain. Transistor 612 corresponds to an MOS structure in a region at the upper and lower edges, and may have a highest drain resistance, for example, due to the long resistive path in the drain. As illustrated in FIG. 6 , tapering may produce different gate-to-drain capacitances, Cgd, along the length of the drain. For example, center transistor 610 may have a first Cgd 602 (C 1 ). The taper is widest at the center so that Cgd 602 has the largest value at the center region. As the resistive path increases along the drain finger, the gate-to-drain capacitance is reduced. For example, center-to-edge transistor 611 may have a second Cgd 604 (C 1 ) that is lower in value than Cgd 602 . Similarly, edge transistor 611 may have a third Cgd 606 (C 1 ) that is lower in value than Cgd 604 . Accordingly, as the resistive path along the length of the drain increases, the capacitive coupling between the gate and the drain is reduced. Advantageously, a time constant produced by the parasitic resistance and gate-to-drain capacitance may be maintained approximately constant across the drain length. A constant RC gate-to-drain time constant, in turn, improves stability and provides a more uniform delay for long width devices.

The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.