Driving device, light-emitting device, projection device, control method, and storage medium

1. Field of the Invention

The present invention relates to a driving device, a light-emitting device, a projection device, a control method, and a storage medium.

2. Description of Related Art

Japanese Patent Application Laid-Open Publication No. 2008-234842 discloses a field sequential-type projection device. A field sequential-type projection device projects a color image by sequentially and repetitively radiating red light, green light, and blue light to a display element. In particular, a projection device disclosed in Japanese Patent Application Laid-Open Publication No. 2008-234842 sequentially and repetitively illuminates red light-emitting diodes, green light-emitting diodes, and blue light-emitting diodes using one DC/DC converter. The voltages of the red light-emitting diodes, the green light-emitting diodes, and the blue light-emitting diodes differ during illumination, and these are driven by one DC/DC converter, and thus, the voltage outputted by the DC/DC converter changes in synchronization with the start of illumination of the red light-emitting diodes, the green light-emitting diodes, and the blue light-emitting diodes, respectively.

An input terminal of this DC/DC converter is connected to an output terminal of an AC/DC converter. If the voltage outputted by the AC/DC converter is not stable, then the voltage outputted by the DC/DC converter is also unstable, and thus, the AC/DC converter is provided with a stabilization circuit. If the stabilization circuit provided in the AC/DC converter is of a switching type, then it is preferable that the stabilization circuit and the DC/DC converter be controlled with one controller in order to reduce the number of components or the like. If the stabilization circuit and the DC/DC converter are controlled by one controller in this manner, then when the voltage outputted by the DC/DC converter is changed, then due to control cycles, there is an increased susceptibility to response delay for the voltage outputted by the stabilization circuit. As a result, when changing the voltage outputted by the DC/DC converter by turning ON and OFF the load, then pulsations (glitches) in the voltage outputted by the stabilization circuit become greater, and as a result, the pulsation increases in the voltage outputted by the DC/DC converter (waveform becomes rounded). A problem to be solved by the present invention is to mitigate the occurrence of pulsation in output from a power source circuit that is a switching-type stabilization circuit when output from a driver circuit changes when controlling a driving device in which a driver circuit driving a load is connected to a power circuit.

Additional or separate features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect, the present disclosure provides a driving device for driving a load, including: a power source circuit that converts power inputted thereto to a power of a constant voltage or a constant current, and then outputs the power that has been converted; a driver circuit that receives the power outputted by the power source circuit and outputs a power to the load; and a control unit performing feedback control on the power source circuit, the control unit receiving a voltage or a current of the power outputted by the power source circuit as a detected value, and outputting to the power source circuit a feedback signal based on a value obtained by multiplying a difference of the detected value and a constant target value by a control gain, wherein the control gain is increased when a voltage or a current of the power outputted from the driver circuit is to change.

In another aspect, the present disclosure provides a method of controlling a power source circuit that converts power inputted thereto to a constant power and outputs the power that has been converted, and a driver circuit that receives the power outputted by the power source circuit and outputs a power to a load that includes: performing feedback control on the power source circuit by receiving a voltage or a current of the power outputted by the power source circuit as a detected value, obtaining a value by multiplying a difference of the detected value and a constant target value by a control gain, and by outputting a feedback signal based on the value to the power source circuit; and increasing the control gain when a voltage or a current of the power outputted from the driver circuit is to change.

In another aspect, the present disclosure provides a non-transitory storage medium to be read by a control unit of a driving device including: a power source circuit that converts power inputted thereto to a power of a constant voltage or a constant current, and then outputs the power that has been converted; a driver circuit that receives the power outputted by the power source circuit and outputs a power to the load; and the control unit, the control unit performing feedback control on the power source circuit and feedback control on the driver circuit to control a voltage or a current of the power outputted by the driver circuit, the storage medium storing a data array in which a plurality of data are arranged in chronological order, the plurality of data including a control gain to be used by the control unit such that when the storage medium is read by the control unit, the control unit successively reads in the control gain to perform the feedback control on the power source circuit by receiving the voltage or the current of the power outputted by the power source circuit as a detected value, obtaining a value by multiplying a difference of the detected value and a constant target value by the control gain retrieved from the storage medium, and outputting a feedback signal based on the value to the power source circuit, wherein the control gain in the data array is set to a constant value except when the voltage or the current of the power outputted by the driver circuit is to change, the control gain being set to a value greater than the constant value when the voltage or the current of the power outputted by the driver circuit is to change.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.

FIG. 1 is a block diagram of a driving device according to Embodiment 1 of the present invention.

FIG. 2 is a chart showing a process flow in an arithmetic processing unit according to the same embodiment.

FIG. 3 is a chart that shows in chronological order a data structure of a target value and control gain stored in a storage medium according to the same embodiment, and that shows a change in output resulting from feedback control.

FIG. 4 is a block diagram of a driving device according to Embodiment 2 of the present invention.

FIG. 5 is a chart showing a process flow in an arithmetic processing unit according to the same embodiment.

FIG. 6 is a chart that shows in chronological order a data structure of a target value and control gain stored in a storage medium according to the same embodiment, and that shows a change in output resulting from feedback control.

FIG. 7 is a block diagram of a driving device according to a modification example of the same embodiment.

FIG. 8 is a chart showing a process flow in an arithmetic processing unit according to the same modification example.

FIG. 9 is a chart that shows in chronological order a data structure of a target value and control gain stored in a storage medium according to the same embodiment, and that shows a change in output resulting from feedback control.

FIG. 10 is a plan view of an optical unit of a projection device according to Embodiment 3 of the present invention.

Embodiments of the present invention will be described below with reference to drawings. The embodiments described below have various limitations that are technically preferred in order to implement the present invention.

Thus, the technical scope of the present invention is not limited to the embodiments and drawing examples below.

FIG. 1 is a block diagram of a driving device 10 for a load 2 .

The driving device 10 drives the load 2 . Specifically, the driving device 10 starts and stops the load 2 in a periodic manner. The load 2 is a light source (semiconductor light-emitting element (light-emitting diode, laser diode, organic light-emitting diode, organic EL element, or the like, for example), an incandescent lamp, a discharge lamp, or the like), a resistor, a heater, a motor, or the like. If the load 2 is a light source, then the device including the driving device 10 and the load 2 is a light-emitting device.

This driving device 10 includes a first switching power source circuit 11 , a second switching power source circuit 12 , an arithmetic processing unit 13 (control unit), a memory 14 (non-transitory storage medium), and the like.

The arithmetic processing unit 13 is a processor such as a microcomputer or a digital signal processor (DSP). The memory 14 is a non-volatile semiconductor memory. The memory 14 may be provided in the arithmetic processing unit 13 or outside the arithmetic processing unit 13 .

An input terminal of the first switching power source circuit 11 is an input terminal of the driving device 10 , and an output terminal of a second switching power source circuit 12 is an output terminal of the driving device 10 . The second switching power source circuit 12 and the load 2 are connected in series to an output terminal of the first switching power source circuit 11 and to a reference potential node 15 (ground), the output terminal of the first switching power source circuit 11 is connected to the input terminal of the second switching power source circuit 12 , the output terminal of the second switching power source circuit 12 is connected to the load 2 , and the load 2 is connected to the reference potential node 15 .

The first switching power source circuit 11 is a direct current output-type and constant voltage output-type DC-DC converter. In other words, the first switching power source circuit 11 is a DC-DC converter that converts direct current power of a voltage Vin to direct current power of a voltage V 1 . More specifically, the first switching power source circuit 11 is a switching regulator that converts the direct current power of the voltage Vin to the direct current power of the voltage V 1 by repeatedly turning ON and OFF a direct current inputted to the first switching power source circuit 11 . The first switching power source circuit 11 has a switching element, an inductor, a smoothing circuit, and the like.

The direct current power of the voltage Vin is generated by an AC-DC converter. The voltage Vin may be stabilized by a stabilization circuit provided in the AC-DC converter, or the voltage Vin may be stabilized without a stabilization circuit being provided in the AC-DC converter.

The method of controlling the first switching power source circuit 11 is of pulse width modulation (PWM) type, and a PWM signal S 1 having a constant period is inputted to the first switching power source circuit 11 , thereby controlling the first switching power source circuit 11 . The PWM signal S 1 is outputted by the arithmetic processing unit 13 , and a duty ratio (pulse width) of the PWM signal S 1 is controlled by the arithmetic processing unit 13 . Here, the arithmetic processing unit 13 performs feedback control on the first switching power source circuit 11 . In other words, the voltage V 1 outputted by the first switching power source circuit 11 is inputted into the arithmetic processing unit 13 as a detected value D 1 , and the arithmetic processing unit 13 controls the outputted voltage V 1 so as to be a target value C 1 by controlling the voltage V 1 outputted by the first switching power source circuit 11 on the basis of the difference calculated between the detected value D 1 and the target value C 1 . More specifically, during one period of the PWM signal S 1 , the arithmetic processing unit 13 receives the detected value D 1 as input and calculates the difference between the detected value D 1 and the target value C 1 , determines a duty ratio on the basis of the value obtained by multiplying the difference by a control gain G 1 , and outputs the PWM signal S 1 of the duty ratio to the first switching power source circuit 11 . The arithmetic processing unit 13 determines the duty ratio every period of the PWM signal S 1 .

The voltage V 1 controlled in this manner is applied to the input terminal of the second switching power source circuit 12 , and a direct current power of the voltage V 1 is supplied to the second switching power source circuit 12 .

The second switching power source circuit 12 is a DC-DC converter that outputs direct current. The second switching power source circuit 12 is a constant voltage source or a constant current source. If the second switching power source circuit 12 is a constant voltage source, then the second switching power source circuit 12 is a switching regulator that converts the direct current power of the voltage V 1 to a direct current power of a constant voltage V 2 by repeatedly switching ON and OFF a direct current inputted from the first switching power source circuit 11 . If the second switching power source circuit 12 is a constant current source, then the second switching power source circuit 12 is a switching regulator that converts the direct current power of the voltage V 1 to direct current power having a constant current I 2 by repeatedly switching ON and OFF a direct current inputted from the first switching power source circuit 11 . The second switching power source circuit 12 has a switching element, an inductor, a smoothing circuit, and the like.

The method of controlling the second switching power source circuit 12 is pulse width modulation (PWM), and a PWM signal S 2 having a constant period is outputted to the second switching power source circuit 12 by the arithmetic processing unit 13 , and the arithmetic processing unit 13 performs feedback control on the second switching power source circuit 12 by controlling a duty ratio (pulse width) of the PWM signal S 2 . If the second switching power source circuit 12 is a constant voltage source, the voltage V 2 outputted by the second switching power source circuit 12 is inputted to the arithmetic processing unit 13 as a detected value D 2 , and the arithmetic processing unit 13 controls the voltage V 2 outputted by the second switching power source circuit 12 on the basis of the difference calculated between the detected value D 2 and the target value C 2 , such that the voltage V 2 becomes the target value C 2 . On the other hand, if the second switching power source circuit 12 is a constant current source, then the current I 2 outputted from the second switching power source circuit 12 is inputted to the arithmetic processing unit 13 as the detected value D 2 , and the arithmetic processing unit 13 controls the current I 2 outputted from the second switching power source circuit 12 on the basis of the difference calculated between the detected value D 2 and the target value C 2 , such that the current I 2 becomes the target value C 2 .

More specifically, whether the second switching power source circuit 12 is a constant voltage source or a constant current source, during one period of the PWM signal S 2 , the arithmetic processing unit 13 receives the detected value D 2 as input and calculates the difference between the detected value D 2 and the target value C 2 , determines a duty ratio on the basis of the value obtained by multiplying the difference by a control gain G 2 , and outputs the PWM signal S 2 of the duty ratio to the second switching power source circuit 12 . The arithmetic processing unit 13 determines the duty ratio every period of the PWM signal S 2 .

If the current I 2 is sent as feedback to the arithmetic processing unit 13 as the detected value D 2 , a resistor is provided between the second switching power source circuit 12 and a load 2 , and the voltage of this resistor is sent as feedback to the arithmetic processing unit 13 as the detected value D 2 and the current I 2 .

The target values C 1 and C 2 and the control gains G 1 and G 2 are stored in the memory 14 , and the arithmetic processing unit 13 reads in the target values C 1 and C 2 and the control gains G 1 and G 2 from the memory 14 . A control circuit that is separate from the arithmetic processing unit 13 (a microcomputer, for example) may output the target value C 1 to the arithmetic processing unit 13 as a control signal, and the target value C 1 may be variably controlled by the control circuit. This similarly applies to the target value C 2 .

FIG. 2 shows a process flow conducted by the arithmetic processing unit 13 based on a program 14 a stored in the memory 14 . As shown in FIG. 2 , the arithmetic processing unit 13 sequentially and repeatedly performs a duty ratio determination process for the PWM signal S 1 and a duty ratio determination process for the PWM signal S 2 . Specifically, the process is as described below. In step ST 1 , the arithmetic processing unit 13 reads in the voltage V 1 outputted by the first switching power source circuit 11 as the detected value D 1 . Next, in step ST 2 , the arithmetic processing unit 13 reads in the target value C 1 from the memory 14 . Next, in step ST 3 , the arithmetic processing unit 13 calculates the difference between the detected value D 1 and the target value C 1 . Next, in step ST 4 , the arithmetic processing unit 13 reads in the control gain G 1 from the memory 14 . Next, in step ST 5 , the arithmetic processing unit 13 calculates a duty ratio based on a value obtained by multiplying this difference by the control gain G 1 , and the PWM signal S 1 of this duty ratio is outputted to the first switching power source circuit 11 . The “f” in FIG. 2 represents a function for determining the duty ratio based on the value obtained by multiplying the difference by the control gain G 1 . Next, in step ST 6 , the arithmetic processing unit 13 reads in the voltage V 2 or the current I 2 outputted from the second switching power source circuit 12 as the detected value D 2 . Next, in step ST 7 , the arithmetic processing unit 13 reads in the target value C 2 from the memory 14 . Next, in step ST 8 , the arithmetic processing unit 13 calculates the difference between the detected value D 2 and the target value C 2 . Next, in step ST 9 , the arithmetic processing unit 13 reads in the control gain G 2 from the memory 14 . Next, in step ST 10 , the arithmetic processing unit 13 calculates a duty ratio based on a value obtained by multiplying this difference by the control gain G 2 , and the PWM signal S 2 of this duty ratio is outputted to the second switching power source circuit 12 . The “F” in FIG. 2 represents a function for determining the duty ratio based on the value obtained by multiplying the difference by the control gain G 2 . Then, the process flow of the arithmetic processing unit 13 returns to the step ST 1 .

The process of steps ST 1 to ST 10 of FIG. 2 is a process conducted during one period of the PWM signal S 1 and the PWM signal S 2 . The arithmetic processing unit 13 repeats the process of steps ST 1 to ST 10 of FIG. 2 , resulting in the PWM signals S 1 and S 2 being received and outputted to the respective switching power source circuits 11 and 12 , and thus, the arithmetic processing unit 13 performs feedback control on the switching power source circuits 11 and 12 .

The target values C 1 and C 2 stored in the memory 14 will be described with reference to FIG. 3 . FIG. 3 shows timing charts of data structures of the target values C 1 and C 2 and the control gain G 1 stored in the memory 14 , and the change in the voltage V 2 (or current I 2 ) and the voltage V 1 due to feedback control. In FIG. 3 , a plurality of data values of the control gain G 1 are arranged in chronological order, and these data values are joined together by a solid line. This similarly applies to the target values C 1 and C 2 . In FIG. 3 , the horizontal axis indicates time and the vertical axis represents the target values C 1 and C 2 and data values of the control gain G 1 , the voltage V 2 (or the current I 2 ), and the voltage V 1 .

As shown in FIG. 3 , the target value C 1 is a non-zero constant value. In other words, the data structure of the target value C 1 includes a data array in which the plurality of data values are arranged in chronological order, and all data are equal (the data is non-zero). The data array of the target value C 1 is stored in the memory 14 in order of address, and the address in the memory 14 corresponds to time. Thus, the process of step ST 2 in FIG. 2 is performed repeatedly in order of addresses of the data array (in chronological order) of the target value C 1 , and thus, the data array of the target value C 1 is read in in order of address (chronological order). The target value C 1 may be read in to the program 14 a for the arithmetic processing unit 13 as a prescribed constant.

Because the target value C 1 is a constant value, if feedback control is performed on the first switching power source circuit 11 by the arithmetic processing unit 13 , the voltage V 1 outputted by the first switching power source circuit 11 is maintained at a constant value.

The target value C 2 is not a constant value. In other words, the data structure of the target value C 2 includes a data array in which a plurality of data values are arranged in chronological order, and the data array constitutes a pulse wave that changes periodically. The data array of the target value C 2 includes a first data array arranged in chronological order as data of a constant K 2 (K 2 ≠0) and a second data array that includes zero as data in chronological order. The data array of the target value C 2 is stored in the memory 14 in order of address, and the address in the memory 14 corresponds to time. Thus, the process of step ST 7 in FIG. 2 is performed repeatedly in order of addresses of the data array (in chronological order) of the target value C 2 , and thus, the data array of the target value C 2 is read in in order of address (chronological order). A period P of the data array of the target value C 2 is sufficiently longer than the period of the PWM signals S 1 and S 2 .

The data structure of the target value C 2 is a pulse wave data array, and thus, if feedback control is performed on the second switching power source circuit 12 by the arithmetic processing unit 13 , then the voltage or current outputted by the second switching power source circuit 12 changes so as to be a pulse wave. In other words, when the target value C 2 is a constant K 2 , then the voltage V 2 or the current I 2 outputted by the second switching power source circuit 12 is maintained at a constant value. If the target value C 2 falls to zero from the constant K 2 , then the voltage V 2 or the current I 2 outputted by the second switching power source circuit 12 falls. When the target value C 2 is zero, then the PWM signal S 2 does not change and the duty ratio (pulse width) of the PWM signal S 2 is zero, no voltage/current is outputted by the second switching power source circuit 12 , and the voltage V 2 or the current I 2 outputted by the second switching power source circuit 12 is maintained at zero. If the target value C 2 rises from zero to the constant K 2 , then the voltage V 2 or the current I 2 outputted by the second switching power source circuit 12 rises.

In this manner, the second switching power source circuit 12 is a power source circuit that converts a voltage/current of the first switching power source circuit 11 , and a driver circuit (driver) that fulfills the role of a switching circuit that supplies an intermittent voltage/current to a load. Here, an example will be described in which the second switching power source circuit 12 fulfills both roles, but the power source circuit and the switching circuit may be separate circuits.

When the voltage V 2 or the current I 2 of the second switching power source circuit 12 is not zero, then the load 2 operates, and if the voltage V 2 or the current I 2 is zero, then the load 2 stops. A switching element is provided between the output terminal of the second switching power source circuit 12 and the load 2 or between the load 2 and the reference potential node 15 , and the switching element may turn ON and OFF in synchronization with the operation of the second switching power source circuit 12 . In other words, the switching element turns ON when the target value C 2 is at the constant K 2 , and the switching element is OFF when the target value C 2 is at zero. In this case, the switching element is turned ON and OFF by the arithmetic processing unit 13 or turned ON and OFF by another circuit (microcomputer, timing generator, or the like). If the switching element is turned ON and OFF by another circuit, then the ON/OFF signal outputted from the other circuit to the switching element is also inputted to the arithmetic processing unit 13 , and the switching element and the target value C 2 are synchronized by the arithmetic processing unit 13 .

Next, the data structure of the control gain G 1 stored in the memory 14 will be described with reference to FIG. 3 . The data structure of the control gain G 1 includes a data array in which a plurality of data values are arranged in chronological order. The data array of the control gain G 1 is stored in the memory 14 in order of address, and the address of the memory 14 corresponds to time. Thus, the process of step ST 4 in FIG. 2 is performed repeatedly in order of addresses of the data array (in chronological order) of the control gain G 1 , and thus, the data array of the control gain G 1 is read in in order of address (chronological order).

The control gain G 1 is not a constant value. In other words, other than when the target value C 2 changes, the data in the data array of the control gain G 1 is at a constant Gc 1 , and when the target value C 2 changes, the data in the data array of the control gain G 1 is set higher than the constant Gc 1 .

Specifically, the control gain G 1 rises to the constant Gc 1 in synchronization with or immediately prior to the time T 1 when the target value C 2 rises from zero to the constant K 2 , and after the time T 1 when the target value C 2 rises from zero to the constant K 2 , the control gain G 1 decreases to the constant Gc 1 , and during the period P 1 therebetween, the data of the control gain G 1 is set higher than the constant Gc 1 . Furthermore, the control gain G 1 rises from the constant Gc 1 in synchronization with or immediately prior to the time T 2 when the target value C 2 falls from the constant K 2 to zero, and after the time T 2 when the target value C 2 falls from the constant K 2 to zero, the control gain G 1 falls to the constant Gc 1 , and in the period P 2 therebetween, the control gain G 1 is set higher than the constant Gc 1 . The control gain G 1 remains at the constant Gc 1 other than the above-mentioned periods.

A quantity of increase Δ1 and the period of increase P 1 of the control gain G 1 when the target value C 2 rises is determined by experiment, simulation, or the like conducted in advance. Specifically, the quantity of increase Δ1 and the period of increase P 1 take into account the size of the pulsation (glitch) that occurs in the voltage outputted by the first switching power source circuit 11 when the target value C 2 and the voltage V 2 (or current I 2 ) changes. The quantity of increase Δ2 and the period of increase P 2 of the control gain G 1 when the target value C 2 falls are similar.

The quantity of increase Δ1 and the quantity of increase Δ2 may be equal to or different from each other. The period of increase P 1 and the period of increase P 2 may be equal to or different from each other. If the effect or rise and the effect of fall are considered to be equal, then the quantity of increase Δ1 and the quantity of increase Δ2, and the period of increase P 1 and the period of increase P 2 may respectively be equal to each other. The waveform of the control gain G 1 when the target value C 2 rises is a pulse wave (refer to FIG. 3 ), a triangular wave, or a sine wave. The waveform of the control gain G 1 when the target value C 2 falls is similar.

The data array for such a control gain G 1 is stored in the memory 14 , and thus, the arithmetic processing unit 13 increases the control gain G 1 (the control gain G 1 of step ST 4 performed for the xth time is higher than the control gain G 1 of a previously performed step ST 4 ) if the target value C 2 changes when the sequential processes are repeated as shown in FIG. 2 (if the target value C 2 of step ST 7 performed for the xth time is different from the target value C 2 of a next performed step ST 7 ).

Feedback control may be performed on the quantity of increase Δ1 and the period of increase P 1 . In other words, the arithmetic processing unit 13 may determine the quantity of increase Δ1 and/or the period of increase P 1 on the basis of the difference between the detected value D 1 and the target value C 1 , and may increase the control gain G 1 in the period of increase P 1 to a value greater than the constant Gc 1 by the quantity of increase Δ1 when the target value C 2 rises. This also applies to the quantity of increase Δ2 and the period of increase P 2 .

The embodiment of the present invention described above has the following effects. (1) The waveform of the voltage or current outputted from the second switching power source circuit 12 is a pulse waveform, and the voltage or current outputted from the second switching power source circuit 12 changes (rises or falls). One arithmetic processing unit 13 sequentially performs a process to determine the duty ratio of the PWM signal S 1 and a process to determine the duty ratio of the PWM signal S 2 (refer to FIG. 2 ), and thus, if the duty ratio of the PWM signal S 1 is determined based on normal gain after the voltage or current outputted from the second switching power source circuit 12 changes, the effect of change in the voltage or current outputted from the second switching power source circuit 12 is not completely absorbed, which results in a large pulsation due to the delay in response of the voltage outputted from the first switching power source circuit 11 . Thus, when the voltage or current outputted from the second switching power source circuit 12 changes, there is a risk of pulsation occurring in the voltage outputted by the first switching power source circuit 11 (refer to FIG. 3 ). However, it is possible to increase the control gain G 1 when the voltage or current outputted from the second switching power source circuit 12 changes, or in other words, when the target value C 2 rises or falls, and thus, it is possible to mitigate delays in response of the voltage outputted from the first switching power source circuit 11 , and it is also possible to mitigate pulsation in the voltage outputted by the first switching power source circuit 11 when the voltage or current outputted from the second switching power source circuit 12 changes. Furthermore, it is also possible to mitigate pulsation in the voltage or current outputted from the second switching power source circuit 12 when the voltage or current outputted from the second switching power source circuit 12 changes. Thus, it is possible to speed up the rising and falling of the voltage or current outputted from the second switching power source circuit 12 , thereby making the waveform closer in shape to the ideal waveform.

(2) Meanwhile, if the control gain G 1 is high in periods other than the periods P 1 and P 2 shown in FIG. 3 , then the voltage outputted from the first switching power source circuit 11 may undergo large pulsation in synchronization with the PWM signal S 1 , or other effects such as vibration occur due to disturbance or the like. However, in the embodiment of the present invention, the control gain G 1 is low at a constant Gc 1 during periods other than the periods P 1 and P 2 , and thus, it is possible to mitigate pulsation in the voltage outputted by the first switching power source circuit 11 .

(3) The quantities of increase Δ1 and Δ2 and the periods of increase P 1 and P 2 are determined by experiment, simulation, or the like, and thus, the pulsation in the voltage outputted by the first switching power source circuit 11 can be minimized, and the waveform for the voltage or current outputted from the second switching power source circuit 12 can be made closer in shape to the ideal waveform.

An embodiment of the present invention was described above. Various modifications can be made to the embodiment without departing from the spirit of the present invention. A few modification examples will be described below. The modification examples below may be combined.

Modification Example 1

In the embodiment above, there was one second switching power source circuit 12 and one load 2 , but there may be a plurality of second switching power source circuits 12 and loads 2 . In such a case, the output terminals of the plurality of second switching power source circuits 12 are connected to the respective plurality of loads 2 , and any of the input terminals of the second switching power source circuits 12 is connected to the output terminal of the first switching power source circuit 11 . The loads 2 may be of the same type or different types. The second switching power source circuits 12 may be of the same type or different types. In a manner similar to that shown in FIG. 2 , the arithmetic processing unit 13 performs the process of determining the duty ratio of the PWM signal S 1 for the first switching power source circuit 11 and then performs the process of determining the duty ratio of the PWM signal S 2 for each second switching power source circuit 12 . The arithmetic processing unit 13 sequentially and repeatedly performs these determining processes. Also, the memory 14 has stored therein target values C 2 and control gains G 2 for each second switching power source circuit 12 . The target values C 2 of the second switching power source circuit may be equal to the constant K 2 or different therefrom. The period P of the data array of the target value C 2 is equal for all second switching power source circuits 12 . The period during which the target value C 2 is equal to the constant K 2 may differ for each second switching power source circuit 12 or be the same for all second switching power source circuits 12 . The period during which the target value C 2 is the constant K 2 may be synchronized for all the second switching power source circuits 12 or not synchronized. When the target value C 2 of any of the second switching power source circuits 12 changes, the control gain G 1 is greater than the constant Gc 1 .

Modification Example 2

In the embodiment above, digital control circuits (arithmetic processing unit 13 and memory 14 ) were used to digitally control the switching power source circuits 11 and 12 . However, analog control circuits may be used instead of the arithmetic processing unit 13 and the memory 14 so as to perform analog control of the switching power source circuits 11 and 12 .

FIG. 4 is a block diagram of a driving device 40 for light-emitting elements 32 a and 32 b and a cooling unit 39 .

The driving device 40 drives the light-emitting elements 32 a and 32 b. Specifically, the driving device 40 causes the light-emitting elements 32 a and 32 b to blink. The light-emitting elements 32 a and 32 b blink at a speed high enough that it cannot be perceived by the naked eye. The period by which the light-emitting element 32 a blinks (period of one instance of turning ON and one instance of turning OFF) is equal to the period by which the light-emitting element 32 b blinks. The light-emitting element 32 a is a laser diode and the light-emitting element 32 b is a light-emitting diode. The cooling unit 39 is a fan or a Peltier element. The cooling unit 39 cools the light-emitting elements 32 a and 32 b.

The driving device 40 includes a first switching power source circuit 41 , second switching power source circuits 42 a and 42 b, an arithmetic processing unit 43 (control unit), a memory 44 (storage medium), a switching element 47 , a temperature sensor 48 , a processing unit 49 , and the like. A device including the driving device 40 and the light-emitting elements 32 a and 32 b is a light-emitting device.

The temperature sensor 48 detects a temperature external to the driving device 40 by converting the temperature external to the driving device 40 into an electrical signal. More specifically, the temperature sensor 48 is disposed on or close to the light-emitting elements 32 a and 32 b and converts the temperature of the light-emitting elements 32 a and 32 b into an electrical signal. The electrical signal representing the temperature detected by the temperature sensor 48 is outputted to the processing unit 49 . The calculating device 43 and the processing unit 49 are processors such as a microcomputer or a digital signal processor (DSP).

The processing unit 49 monitors the output from the temperature sensor 48 and functions as a comparator of a digital circuit. Specifically, the processing unit 49 compares the temperature detected by the temperature sensor 48 to a prescribed threshold, and outputs a signal representing the result of this comparison to the arithmetic processing unit 43 . If the temperature detected by the temperature sensor 48 exceeds the threshold, the signal outputted from the processing unit 49 to the arithmetic processing unit 43 is at a high level, and if the temperature detected by the temperature sensor 48 is less than or equal to the threshold, the signal outputted from the processing unit 49 to the arithmetic processing unit 43 is at a low level. A comparison circuit as an analog circuit may be used instead of the processing unit 49 .

The memory 44 is a non-volatile memory. The memory 44 stores target values C 1 , Ca 2 , and Cb 2 , and control gains G 1 , Ga 2 , and Gb 2 . Details of the target values C 1 , Ca 2 , and Cb 2 , and the control gains G 1 , Ga 2 , and Cb 2 will be described below.

The input terminal of the first switching power source circuit 41 is the input terminal of the driving device 40 , and a constant voltage Vin is applied to the input terminal. The output terminal of the first switching power source circuit 41 is connected to the input terminals of the second switching power source circuit 42 and 42 b, the output terminal of the second switching power source circuit 42 a is connected to the positive pole (anode) of the light-emitting element 32 a through a resistor 46 a, and the output terminal of the second switching power source circuit 42 b is connected to the positive pole of the light-emitting element 32 b through the resistor 46 b. The negative poles (cathode) of the light-emitting elements 32 a and 32 b are connected to a reference potential node 45 (ground). Also, the cooling unit and the switching element 47 are connected in series between the output terminal of the first switching power source circuit 41 and the reference potential node 45 .

The first switching power source circuit 41 is a DC-DC converter (switching regulator) of the direct current output type, the constant voltage output type, and the voltage step up type. The first switching power source circuit 41 has a capacitor 51 , an inductor 52 , a switching element 53 (transistor), and a rectifying element 54 . A capacitor 51 and an inductor 52 are connected in series between the reference potential node 45 and the positive pole of the rectifying element 54 , and the connecting portion of the capacitor 51 and the inductor 52 is the input terminal of the first switching power source circuit 41 . A switching element 53 is connected between the positive pole of the rectifying element 54 and the reference potential node 45 . The negative pole of the rectifying element 54 is the output terminal of the first switching power source circuit 41 .

The second switching power source circuits 42 a and 42 b are DC-DC converters (switching regulators) of the direct current output type, the constant current output type, and the step down type. The second switching power source circuit 42 a has a switching element 61 (transistor), a rectifying element 62 , and a capacitor 63 . The positive pole of the rectifying element 62 is connected to the reference potential node 45 . The switching element 61 is connected between the negative pole of the rectifying element 62 and the negative pole of the rectifying element 54 of the first switching power source circuit 41 . The negative pole of the rectifying element 62 is connected to one electrode of the capacitor 63 , and the negative pole of the rectifying element 62 and one electrode of the capacitor 63 are the output terminal of the second switching power source circuit 42 a. The other electrode of the capacitor 63 is connected to the reference potential node 45 . An inductor may be connected between the negative pole of the rectifying element 62 and the one electrode of the capacitor 63 .

The second switching power source circuit 42 b has a switching element 71 (transistor), a rectifying element 72 , and a capacitor 73 . The positive pole of the rectifying element 72 is connected to the reference potential node 45 . The switching element 71 is connected between the negative pole of the rectifying element 72 and the negative pole of the rectifying element 54 of the first switching power source circuit 41 . The negative pole of the rectifying element 72 is connected to one electrode of the capacitor 73 , and the negative pole of the rectifying element 72 and one electrode of the capacitor 73 are the output terminal of the second switching power source circuit 42 b. The other electrode of the capacitor 73 is connected to the reference potential node 45 . An inductor may be connected between the negative pole of the rectifying element 72 and the one electrode of the capacitor 73 .

The arithmetic processing unit 43 outputs a PWM signal S 1 having a constant period to the switching element 53 (in particular, the gate or the base), and the switching element 53 turns ON or OFF according to the PWM signal S 1 . The current flowing from the input terminal of the first switching power source circuit 41 to the reference potential node 45 through the inductor 52 and the switching element 53 is turned ON or OFF by the switching element 53 , and thus, direct current power of the voltage Vin is converted to direct current power of the voltage V 1 . The voltage V 1 outputted by the first switching power source circuit 41 is returned to the arithmetic processing unit 43 as a detected value D 1 .

The arithmetic processing unit 43 outputs a PWM signal Sa 2 having a constant period to the switching element 61 (in particular, the gate or the base), and the switching element 61 turns ON or OFF according to the PWM signal Sa 2 . The current flowing from the input terminal of the second switching power source circuit 42 a to the output terminal of the second switching power source circuit 42 a through the switching element 61 is turned ON or OFF by the switching element 61 , and thus, direct current power of the voltage V 1 is converted to direct current power of a current Ia 2 . The current Ia 2 outputted by the second switching power source circuit 42 a returns to the arithmetic processing unit 43 as a detected value Da 2 . Here, the current Ia 2 outputted by the second switching power source circuit 42 a is converted to a voltage of the resistor 46 a.

The arithmetic processing unit 43 outputs a PWM signal Sb 2 having a constant period to the switching element 71 (in particular, the gate or the base), and the switching element 71 turns ON or OFF according to the PWM signal Sb 2 . The current flowing from the input terminal of the second switching power source circuit 42 b to the output terminal of the second switching power source circuit 42 b through the switching element 71 is turned ON or OFF by the switching element 71 , and thus, direct current power of the voltage V 1 is converted to direct current power of a current Ib 2 . The current Ib 2 outputted by the second switching power source circuit 42 b returns to the arithmetic processing unit 43 as a detected value Db 2 . Here, the current Ib 2 outputted by the second switching power source circuit 42 b is converted to a voltage of the resistor 46 b.

The duty ratio (pulse width) of the PWM signals S 1 , Sa 2 , and Sb 2 is determined by the arithmetic processing unit 43 every period of the PWM signals S 1 , Sa 2 , and Sb 2 . In other words, the arithmetic processing unit 43 sequentially and repeatedly performs a process of determining a duty ratio of the PWM signal S 1 , a process of determining a duty ratio of the PWM signal Sa 2 , and a process of determining a duty ratio of the PWM signal Sb 2 (refer to FIG. 5 ). FIG. 5 shows a process flow performed by the arithmetic processing unit 43 according to a program 44 a stored in the memory 44 . In the step ST 21 , the arithmetic processing unit 43 reads in the voltage V 1 outputted from the first switching power source circuit 41 as the detected value D 1 . Next, in step ST 22 , the arithmetic processing unit 43 reads in the target value C 1 from the memory 44 . Next, in step ST 23 , the arithmetic processing unit 43 calculates the difference between the detected value D 1 and the target value C 1 . Next, in step ST 24 , the arithmetic processing unit 43 reads in the control gain G 1 from the memory 44 . Next, in step ST 25 , the arithmetic processing unit 43 calculates the duty ratio based on the value resulting from multiplying the difference by the control gain G 1 , and outputs the PWM signal S 1 of this duty ratio to the switching element 53 of the first switching power source circuit 41 . The “f” shown in FIG. 5 represents a function for determining the duty ratio based on the value obtained by multiplying the difference by the control gain G 1 . Next, in step ST 26 , the arithmetic processing unit 43 reads in the current Ia 2 outputted by the second switching power source circuit 42 a as the detected value Da 2 . Next, in step ST 27 , the arithmetic processing unit 43 reads in the target value Ca 2 from the memory 44 . Next, in step ST 28 , the arithmetic processing unit 43 calculates the difference between the detected value Da 2 and the target value Ca 2 . Next, in step ST 29 , the arithmetic processing unit 43 reads in the control gain Ga 2 from the memory 44 . Next, in step ST 30 , the arithmetic processing unit 43 calculates the duty ratio based on the value resulting from multiplying the difference by the control gain Ga 2 , and outputs the PWM signal Sa 2 of this duty ratio to the switching element 61 of the second switching power source circuit 42 a. The “F” shown in FIG. 5 represents a function for determining the duty ratio based on the value obtained by multiplying the difference by the control gain Ga 2 . Next, in step ST 31 , the arithmetic processing unit 43 reads in the current Ib 2 outputted by the second switching power source circuit 42 b as the detected value Db 2 . Next, in step ST 32 , the arithmetic processing unit 43 reads in the target value Cb 2 from the memory 44 . Next, in step ST 33 , the arithmetic processing unit 43 calculates the difference between the detected value Db 2 and the target value Cb 2 . Next, in step ST 34 , the arithmetic processing unit 43 reads in the control gain Gb 2 from the memory 44 . Next, in step ST 35 , the arithmetic processing unit 43 calculates the duty ratio based on the value resulting from multiplying the difference by the control gain Gb 2 , and outputs the PWM signal Sb 2 of this duty ratio to the switching element 71 of the second switching power source circuit 42 b. The “G” shown in FIG. 5 represents a function for determining the duty ratio based on the value obtained by multiplying the difference by the control gain Gb 2 . Then, the process flow of the arithmetic processing unit 43 returns to the step ST 21 . During one period of the PWM signals S 1 , Sa 2 , and Sb 2 , the above-mentioned steps ST 21 to ST 35 are performed once, and by the steps ST 21 to ST 35 being repeated, the PWM signals S 1 , Sa 2 , and Sb 2 are continuously outputted, which allows for feedback control of the switching power source circuits 41 , 42 a, and 42 b.

The target values C 1 , Ca 2 , and Cb 2 , and the control gain G 1 stored in the memory 44 will be described with reference to FIG. 6 . FIG. 6 shows timing charts showing the data structure of the target values C 1 , Ca 2 , and Cb 2 , and the control gain G 1 stored in the memory 44 in chronological order, and showing the change in voltage V 1 , currents Ia 2 and Ia 2 resulting from feedback control.

The data structure of the target value C 1 is similar to the data structure of the target value C 1 described in Embodiment 1, and thus, description of the data structure of the target value C 1 will be omitted. The process of step ST 22 in FIG. 5 is performed repeatedly in order of addresses of the data array (in chronological order) of the target value C 1 , and thus, the data array of the target value C 1 is read in in order of address (chronological order). Thus, the voltage V 1 outputted from the first switching power source circuit 41 is maintained at a constant value.

The data structures of the target values Ca 2 and Cb 2 are data arrays such as pulses that periodically change, similar to the target value C 2 described in Embodiment 1. The data array of the target value Ca 2 includes a data array arranged in chronological order as data of a constant K 2 a (Ka 2 ≠0) and a data array that includes zero as data in chronological order. The data array of the target value Cb 2 includes the data array in which a constant Kb 2 (Kb 2 ≠0) is arranged in chronological order and a data array that includes zero as data in chronological order. A period P of the data array of the target value Ca 2 is equal to a period P of the data array of the target value Cb 2 . The period of the data array of the target value Ca 2 and the period during which the target value Ca 2 is at the constant Ka 2 is longer than the period during which the target value Cb 2 is at the constant Kb 2 , and the entire period during which the target value Cb 2 is at the constant Kb 2 overlaps (is included) in time the period during which the target value Ca 2 is at the constant Ka 2 .

The process of step ST 27 in FIG. 5 is performed repeatedly in order of addresses of the data array (in chronological order) of the target value Ca 2 , and thus, the data array of the target value Ca 2 is read in in order of address (chronological order). Thus, during the period when the target value Ca 2 is at the constant Ka 2 , the current Ia 2 outputted from the second switching power source circuit 42 a is maintained at a constant value, and the light-emitting element 32 a is illuminated. When the target value Ca 2 is at zero, the current Ia 2 outputted from the second switching power source circuit 42 a is maintained at zero, and the light-emitting element 32 a is turned off.

Similarly, the process of step ST 29 in FIG. 5 is performed repeatedly in order of addresses of the data array (in chronological order) of the target value Cb 2 , and thus, the data array of the target value Cb 2 is read in in order of address (chronological order). Thus, during the period when the target value Cb 2 is at the constant Kb 2 , the current Ib 2 outputted from the second switching power source circuit 42 b is maintained at a constant value, and the light-emitting element 32 b is illuminated. When the target value Cb 2 is at zero, the current Ib 2 outputted from the second switching power source circuit 42 b is maintained at zero, and the light-emitting element 32 b is turned off.

The data structure of the control gain G 1 includes a data array in which a plurality of data are arranged in chronological order, and the data array is stored in the memory 44 in order of address, and the addresses in the memory 44 correspond to time. The control gain G 1 rises from the constant Gc 1 simultaneously or immediately prior to a time T 11 when the target value Ca 2 rises from zero to the constant Ka 2 , the control gain G 1 falls to the constant Gc 1 after the time T 11 when the target value Ca 2 rises from zero to the constant Ka 2 , and during the period P 11 therebetween, the data of the control gain G 1 is set higher than the constant Gc 1 . Also, the control gain G 1 rises from the constant Gc 1 simultaneously or immediately prior to a time T 12 when the target value Cb 2 rises from zero to the constant Kb 2 , the control gain G 1 falls to the constant Gc 1 after the time T 12 when the target value Cb 2 rises from zero to the constant Kb 2 , and during the period P 12 therebetween, the data of the control gain G 1 is set higher than the constant Gc 1 . The control gain G 1 rises from the constant Gc 1 simultaneously or immediately prior to a time T 13 when the target value Cb 2 falls from the constant Kb 2 to zero, the control gain G 1 falls to the constant Gc 1 after the time T 13 when the target value Cb 2 falls from the constant Kb 2 to zero, and during the period P 13 therebetween, the data of the control gain G 1 is set higher than the constant Gc 1 . The control gain G 1 rises from the constant Gc 1 simultaneously or immediately prior to a time T 14 when the target value Ca 2 falls from the constant Ka 2 to zero, the control gain G 1 falls to the constant Gc 1 after the time T 14 when the target value Ca 2 falls from the constant Ka 2 to zero, and during the period P 14 therebetween, the data of the control gain G 1 is set higher than the constant Gc 1 . In other words, besides when the target values Ca 2 and Cb 2 and the currents Ia 2 and Ib 2 change, the data of the control gain G 1 is set to the constant Gc 1 , and when the target values Ca 2 and Cb 2 and the currents Ia 2 and Ib 2 change, the data of the control gain G 1 is set higher than the constant Gc 1 .

The quantities of increase Δ11, Δ12, Δ13, and Δ14 and the periods of increase P 11 , P 12 , P 13 , and P 14 when the target values Ca 2 and Cb 2 and the currents Ia 2 and Ib 2 change are determined in advance by experiment, simulation, or the like. The quantities of increase Δ11, Δ12, Δ13, and Δ14 are equal to or different from each other. The periods of increase P 11 , P 12 , P 13 , and P 14 are equal to or different from each other.

In general, if the change in current is large, the pulsation is also large, and thus, as shown in FIG. 6 , when Ka 1 is larger than Kb 2 , the quantity of change Δ11 is set at a value larger than Δ12, and Δ13 is set at a value smaller than Δ14.

The process of step ST 24 in FIG. 5 is performed repeatedly in order of addresses of the data array (in chronological order) of the control gain G 1 , and thus, the data array of the control gain G 1 is read in in order of address (chronological order). Thus, as the arithmetic processing unit 43 repeatedly performs the steps in order as shown in FIG. 5 , when the target values Ca 2 and Cb 2 and the currents Ia 2 and Ib 2 change, the arithmetic processing unit 43 increases the control gain G 1 .

Feedback control may be performed on the quantity of increase Δ11 and the period of increase P 11 . In other words, the arithmetic processing unit 43 may determine the quantity of increase Δ11 and/or the period of increase P 12 based on the difference between the detected value D 1 and the target value C 1 , and increase the control gain G 1 in the period of increase P 11 from the constant Gc 1 by the quantity of increase Δ11 when the target value Ca 2 rises. This similarly applies to the quantity of increase Δ12 and the period of increase P 12 , the quantity of increase Δ13 and the period of increase P 13 , and the quantity of increase Δ14 and the period of increase P 14 .

If the temperature detected by the temperature sensor 48 exceeds a prescribed threshold as the arithmetic processing unit 43 repeatedly executes the steps shown in FIG. 5 , the signal outputted from the processing unit 49 to the arithmetic processing unit 43 changes. The arithmetic processing unit 43 detects when the temperature detected by the temperature sensor 48 exceeds the threshold as an interrupting step. In such a case, during the step ST 24 , the arithmetic processing unit 43 reads in data greater than the constant Gc 1 as the control gain G 1 from the memory 44 instead of reading in the data of the data array shown in FIG. 6 as the control gain G 1 . Here, data of a greater value than the constant Gc 1 is stored in the memory 44 . Alternatively, a value greater than the constant Gc 1 may be calculated and read in by the arithmetic processing unit 43 as the control gain G 1 when the temperature detected by the temperature sensor 48 exceeds the threshold.

The arithmetic processing unit 43 repeatedly executes the steps of FIG. 5 (however, in any instance of the step ST 24 being executed, data of a value greater than the constant Gc 1 is read in as the control gain G 1 ). If the arithmetic processing unit 43 , which is executing these processes, detects that the temperature detected by the temperature sensor 48 exceeds the prescribed threshold, or the opposite phenomenon is observed, then an interrupting process is executed. In the interrupting process, the arithmetic processing unit 43 causes the switching element 47 to switch from ON to OFF or from OFF to ON. Specifically, if the signal outputted from the processing unit 49 to the arithmetic processing unit 43 changes from a low level to a high level, the arithmetic processing unit 43 causes the switching element 47 to which from OFF to ON, causing the cooling unit 39 to operate. If the signal outputted from the processing unit 49 to the arithmetic processing unit 43 changes from a high level to a low level, the arithmetic processing unit 43 causes the switching element 47 to switch from ON to OFF, causing the cooling unit 39 to stop.

Immediately after the interrupting process, the arithmetic processing unit 43 repeatedly executes the steps shown in FIG. 5 for a fixed period (however, in any instance of the step ST 24 being executed, data having a value greater than the constant GC 1 related to the operation of the cooling unit 39 is read in as the control gain G 1 ). Then, after a certain period of time until the effects of the operation of the cooling unit 39 end, the arithmetic processing unit 43 returns the control gain G 1 to data of the data array shown in FIG. 6 , and repeatedly executes the steps of FIG. 5 (in the step ST 24 , the data of the data array shown in FIG. 6 is read in as the control gain G 1 ).

As a result of the arithmetic processing unit 43 executing the steps above, the control gain G 1 is greater than the constant Gc 1 even outside of the times T 11 , T 12 , T 13 , and T 14 when the target values Ca 2 and Cb 2 and the currents Ia 2 and Ib 2 change. In other words, the control gain G 1 is greater than the constant Gc 1 during a certain period when (or after) the temperature of the driving device 40 rises and the cooling unit 39 operates. Even during (after) the certain period when the cooling unit 39 is stopped, the control gain G 1 is made greater than the constant Gc 1 .

If the actual start/stop of the cooling unit 39 from when the temperature above the threshold is detected is delayed, then the control gain G 1 can be raised even during the prescribed delay time immediately prior to start/stop, and not only immediately after start/stop.

According to Embodiment 2, effects similar to those described in Embodiment 1 can be attained, and in addition, the following effects can be attained.

(1) The control gain G 1 when the cooling unit 39 is started or stopped can be raised, and thus, pulsation in the voltage outputted by the first switching power source circuit 41 can be mitigated, the effect of starting or stopping the cooling unit 39 on the output from the second switching power source circuits 42 a and 42 b can be minimized, and the pulsation in the first switching power source circuit 41 can be mitigated. Thus, it is possible to make the waveform of the output from the second switching power source circuits 42 a and 42 b closer in shape to the ideal waveform.

An embodiment of the present invention was described above. Various modifications can be made to Embodiment 2 without departing from the spirit of the present invention. A few modification examples will be described below. The modification examples below may be combined.

Modification Example 1

The phase of the data array of the target value Cb 2 may be offset such that the period when the target value Cb 2 is zero overlaps in time with the period in which the target value Ca 2 is equal to the constant Ka 2 , and such that the period when the target value Ca 2 is zero overlaps in time with the period when the target value Cb 2 is equal to the constant Kb 2 . In such a case, the periods P 12 and P 14 when the control gain G 1 increases as the target value Cb 2 and the current Ib 2 change is offset by an amount equal to the offset of the data array of the target value Cb 2 . Thus, when the target values Ca 2 and Cb 2 and the currents Ia 2 and Ib 2 change, the control gain G 1 is raised from the constant Gc 1 .

Modification Example 2

The number of second switching power source circuits connected to the output terminal of the first switching power source circuit 41 may be three or more, and a plurality of light-emitting elements may respectively be connected to the output terminals of the second switching power source circuits.

For example, as shown in FIG. 7 , an input terminal of a second switching power source circuit 42 c is connected to the output terminal of the first switching power source circuit 41 in addition to the second switching power source circuits 42 a and 42 b, the positive pole of the light-emitting element 32 c is connected to the output terminal of the second switching power source circuit 42 c, and the negative pole of the light-emitting element 32 c is connected to the reference potential node 45 .

The second switching power source circuit 42 c has a configuration similar to the second switching power source circuits 42 a and 42 b. The reference characters 81 , 82 , and 83 are respectively assigned to the switching element, the rectifying element, and the capacitor of the second switching power source circuit 42 c. Also, the reference character 46 c is assigned to a resistor. The reference character Ic 2 is assigned to a current outputted from the second switching power source circuit 42 c, the reference character Sc 2 is assigned to a PWM signal outputted to the switching element 81 by the arithmetic processing unit 43 , the reference character Dc 2 is assigned to a detected value of the current Ic 2 , the reference character Cc 2 is assigned to a target value read in by the arithmetic processing unit 43 , and the reference character Gc 2 is assigned to a control gain read in by the arithmetic processing unit 43 .

The detected value Dc 2 , the target value Cc 2 , and the control gain Gc 2 are used when determining the duty ratio of the PWM signal Sc 2 . In other words, the arithmetic processing unit 43 conducts process of determining the duty ratio of the PWM signal Sc 2 as shown in FIG. 8 (steps ST 36 to ST 40 ) following the process of determining the duty ratio of the PWM signal Sb 2 shown in FIG. 5 (steps ST 31 to ST 35 ). The arithmetic processing unit 43 repeatedly performs the process of determining the duty ratio of the PWM signal S 1 (steps ST 21 to ST 25 ), the process of determining the duty ratio of the PWM signal Sa 2 (steps ST 26 to ST 30 ), the process of determining the duty ratio of the PWM signal Sb 2 (steps ST 31 to ST 35 ), and the process of determining the duty ratio of the PWM signal Sc 2 (steps ST 36 to ST 40 ) (refer to FIG. 8 ). In step ST 40 in FIG. 8 , “g” represents a function.

FIG. 9 shows a data structure of the target values C 1 , Ca 2 , Cb 2 , and Cc 2 , and the control gain G 1 stored in the memory 44 . As shown in FIG. 9 , the data structure of both the target values C 1 , Ca 2 , Cb 2 , and Cc 2 and the control gain G 1 are data arrays in which a plurality of data are arranged in chronological order (in order of address). The data in the data array for the target value C 1 are all equal.

The data arrays for the target values Ca 2 , Cb 2 , and Cc 2 are data arrays for pulses that change periodically, and the period is the same for all of the data arrays. The period when the target value Ca 2 is at the constant Ka 2 (period from the time 21 to the time 22 ), the period when the target value Cb 2 is at the constant Kb 2 (period from the time 22 to the time 23 ), and the period when the target value Cc 2 is at the constant Kc 2 (Kc 2 ≠0) (period from the time 23 to the time 21 ) are offset in time from each other. The target value Cc 2 falls from the constant Kc 2 to zero in synchronization with the target value Ca 2 rising from zero to the constant Ka 2 (refer to time T 21 ). The target value Ca 2 falls from the constant Ka 2 to zero in synchronization with the target value Cb 2 rising from zero to the constant Kb 2 (refer to time T 22 ). The target value Cb 2 falls from the constant Kb 2 to zero in synchronization with the target value Cc 2 rising from zero to the constant Kc 2 (refer to time T 23 ).

The data in the data array for the control gain G 1 in a period outside of the periods P 21 , P 22 , and P 23 is set at the constant Gc 1 , and during the periods P 21 , P 22 , and P 23 , the data is set to zero. The period P 21 is a period that straddles the time T 21 when the target values Cc 2 and Ca 2 and the currents Ic 2 and Ia 2 change, the period P 22 is a period that straddles the time T 22 when the target values Ca 2 and Cb 2 and the currents Ia 2 and Ib 2 change, and the period P 23 is a period that straddles the time T 23 when the target values Cb 2 and Cc 2 and the currents Ib 2 and Ic 2 change. The periods P 21 , P 22 , and P 23 are shorter than the period of the data arrays of the target values Ca 2 , Cb 2 , and Cc 2 . The period P 21 may start at the time T 21 , the period P 22 may start at the time T 22 , and the period P 23 may start at the time T 23 .

The process of step ST 24 in FIG. 8 is performed repeatedly in order of addresses of the data array (in chronological order) of the control gain G 1 , and thus, the data array of the control gain G 1 is read in in order of address (chronological order). Thus, when the target values Ca 2 , Cb 2 , and Cc 2 and the currents Ia 2 , Ib 2 , and Ic 2 change as the arithmetic processing unit 43 repeatedly performs the steps in order as shown in FIG. 8 , the arithmetic processing unit 43 raises the control gain G 1 .

As shown in FIG. 9 , the size of the pulsation is affected by the (difference in) changes, or in other words, the (difference in) wave height of the target values, and thus, it is preferable that the control gain G 1 be set so as to be determined by the (difference in) wave height of the target values.

In the embodiments above, the voltages from the power source circuits (first switching power source circuit 11 , first switching power source circuit 41 ) receive feedback control, but the currents may receive feedback control such that power of a constant current is outputted.

A projection device including the light-emitting device according to Modification Example 2 of Embodiment 2 will be described with reference to FIG. 10 . FIG. 10 is a plan view of an optical unit of the projection device.

As shown in FIG. 10 , the projection device, in addition to the light-emitting device, includes an excitation light/fluorescent light conversion device 80 , an optical system 70 , a display element 75 , a projection lens unit 90 , and the like.

The light-emitting element 32 a is a blue light-emitting diode, and the light-emitting element 32 c is a red light-emitting diode. They are disposed such that the optical axes of the light-emitting element 32 c and the light-emitting element 32 a are perpendicular to each other.

There are a plurality of light-emitting elements 32 b. The light-emitting elements 32 b are arranged in a two-dimensional array. The wavelength band of laser excitation light emitted by the light-emitting element 32 b is in the blue waveband or the ultraviolet waveband, but is not limited thereto. The light-emitting element 32 b is a laser diode that emits excitation light. The light-emitting element 32 b and the light-emitting element 32 a are disposed such that the optical axes thereof are perpendicular to each other.

The excitation light/fluorescent light conversion device 80 generates green fluorescent light from the excitation light emitted by the light-emitting element 32 b. The excitation light/fluorescent light conversion device 80 has a plurality of collimator lenses 81 , a group of lenses 82 , a group of lenses 83 , a fluorescent wheel 84 , and a spindle motor 85 . The collimator lenses 81 respectively face the light-emitting elements 32 b, and laser excitation light emitted by the light-emitting elements 32 b is collimated by the collimator lenses 81 . The group of lenses 82 and the group of lenses 83 are disposed on the same optical axis. The group of lenses 82 and the group of lenses 83 are gather the beams of laser excitation light collimated by the collimator lenses 81 and condense them.

The fluorescent wheel 84 faces the surface in which the plurality of light-emitting elements 32 b are arranged in the two-dimensional array. The group of lenses 82 and the group of lenses 83 are disposed between the fluorescent wheel 84 and the light-emitting elements 32 b , and the optical axes of the group of lenses 82 and the group of lenses 83 are perpendicular to the fluorescent wheel 84 . Also, the optical axes of the groups of lenses 82 and 83 are parallel to the optical axes of the light-emitting elements 32 b and 32 c and are perpendicular to the optical axis of the light-emitting element 32 a.

The laser excitation light condensed by the group of lenses 82 and the group of lenses 83 is radiated to the fluorescent wheel 84 . The fluorescent wheel 84 is formed by forming a green fluorescent body that emits green light when excited by the laser excitation light onto a mirrored wheel. Thus, as a result of the laser excitation light being radiated onto the green fluorescent body of the fluorescent wheel 84 , the green fluorescent light emits green light. The fluorescent wheel 84 is connected to the spindle motor 85 , and the fluorescent wheel 84 rotates as a result of the spindle motor 85 .

The plurality of light-emitting elements 32 b that generate excitation light may be changed to one light-emitting element 32 b (light emitting diode) that emits green light. In such a case, it is possible to provide the light-emitting element 32 b where the optical axes of the fluorescent wheel 84 and the group of lenses 83 intersect, and it is possible to omit the collimator lens 81 and the group of lenses 82 .

Next, the optical system 70 will be described in detail. The optical system 70 radiates red light, green light, and blue light to the display element 75 by merging together the optical axis of the red light emitted by the light-emitting element 32 c, the optical axis of the green light emitted by the fluorescent wheel 84 , and the optical axis of the blue light emitted by the light-emitting element 32 a. The optical system 70 has a group of lenses 70 a, a lens 70 b, a group of lenses 70 c, a first dichroic mirror 70 d, a second dichroic mirror 70 e, a lens 70 f, a reflective mirror 70 g, a lens 70 h, an integrator optical element 70 i, a lens 70 j, an optical axis conversion mirror 70 k, a group of condensing lenses 70 m, an illumination mirror 70 p, and an illumination lens 70 q.

The group of lenses 70 a face the light-emitting element 32 a. The group of lenses 70 a and the lens 70 b are disposed such that the optical axes thereof are aligned in one line. The optical axis of the group of lenses 70 a and the lens 70 b intersect perpendicularly with the optical axis of the group of lenses 82 and the group of lenses 83 , between the group of lenses 82 and the group of lenses 83 .

The first dichroic mirror 70 d is disposed between the group of lenses 70 a and the lens 70 b, and between the group of lenses 82 and the group of lenses 83 . The first dichroic mirror 70 d is at a 45° angle with respect to the optical axis of the groups of lenses 82 and 83 , and at a 45° angle with respect to the optical axis of the group of lenses 70 a and the lens 70 b. The first dichroic mirror 70 d allows through excitation light of the wavelength band emitted by the light-emitting element 82 b (blue excitation light, for example) so as to travel towards the fluorescent wheel 84 , and allows through blue wavelength light emitted by the light-emitting element 32 a so as to travel towards the second dichroic mirror 70 e. The first dichroic mirror 70 d reflects green wavelength light emitted by the fluorescent wheel 84 towards the second dichroic mirror 70 e.

The group of lenses 70 c face the light-emitting element 32 c. The group of lenses 70 c is disposed such that the optical axis thereof intersects perpendicularly with the optical axis of the group of lenses 70 a and the lens 70 b, the group of lenses 70 c being on the side of the lens 70 b opposite to the light-emitting element 32 a and the first dichroic mirror 70 d.

The second dichroic mirror 70 e is disposed on the side of the group of lenses 70 c opposite to the light-emitting element 32 c, and is disposed on the side of the lens 70 b opposite to the first dichroic mirror 70 d. The second dichroic mirror 70 e is at a 45° angle to the optical axis of the group of lenses 70 c, and is at a 45° angle to the optical axis of the group of lenses 70 a and the lens 70 b. The second dichroic mirror 70 e allows through blue and green wavelength light from the first dichroic mirror 70 d so as to travel towards the lens 70 f, and reflects red wavelength light emitted by the light-emitting element 32 c towards the lens 70 f.

The lens 70 f is disposed on the side of the second dichroic mirror 70 e opposite to the lens 70 b. The lens 70 f is disposed such that the optical axis thereof matches the optical axis of the lens 70 b and the group of lenses 70 a.

The lens 70 h, the integrator optical element 70 i, and the lens 70 j are disposed such that optical axes thereof are all in one line. The lens 70 h, the integrator optical element 70 i, and the lens 70 j have optical axes that intersect perpendicularly to the lens 70 f, the lens 70 b, and the group of lenses 70 a.

The reflective mirror 70 g is disposed in a portion where the optical axis of the lens 70 h intersects with the optical axis of the lens 70 f. The reflective mirror 70 g is at a 45° angle to the optical axis of the lenses 70 f and 70 b, and the group of lenses 70 a, and at a 45° angle to the optical axis of the lens 70 h, the integrator optical element 70 i, and the lens 70 j. The red light, green light, and blue light are condensed by the lens 70 f and the lens 70 h, and reflected by the reflective mirror 70 g towards the integrator optical element 70 i.

The integrator optical element 70 i is a light tunnel or a light rod. Light that has entered the light-receiving face of the integrator optical element 70 i facing the lens 70 h is guided within the integrator optical element 70 i and emitted from the opposite end face. The integrator optical element 70 i makes even the illuminance distribution of light emitted, along the surface intersecting perpendicularly with the optical axis of the emitted light.

The lens 70 j emits the red light, green light, and blue light guided by the integrator optical element 70 i towards the optical axis conversion mirror 70 k and condenses the light. The optical axis conversion mirror 70 k reflects the red light, green light, and blue light received from the lens 70 j towards the group of condensing lenses 70 m. The group of condensing lenses 70 m radiate the red light, green light, and blue light reflected by the optical axis conversion mirror 70 k towards the illumination mirror 70 p and condenses this light. The illumination mirror 70 p reflects the light received from the group of condensing lenses 70 m towards the display element 75 . The illumination lens 70 q radiates the light reflected by the illumination mirror 70 p towards the display element 75 .

The display element 75 is a reflective spatial light modulator, and more specifically, is a digital micromirror device (DMD). The display element 75 may be a transmissive special light modulator (a liquid crystal shutter array panel; a so-called liquid crystal display device) instead of a reflective spatial light modulator. If the display element 75 is a transmissive spatial light modulator, the optical design of the optical system 70 is modified such that light is radiated to the display element 75 from the side opposite to the projection lens unit 90 (projection optical system).

The projection lens unit 90 is provided so as to face the display element 75 , and the optical axis of the projection lens unit 90 extends in the front/rear direction and intersects with the display element 75 (specifically, perpendicularly). The projection lens unit 90 radiates light reflected by the display element 75 towards the front, thus projected images formed by the display element 75 onto a screen. The projection lens unit 90 includes a movable group of lenses 91 , a fixed group of lenses 92 , and the like. The projection lens unit 90 is configured such that the focus distance can be changed by movement of the movable group of lenses 91 , thus allowing focusing.

The projection device shown in FIG. 10 may be applied to a rear projection display device. A rear projection display device includes a transmissive screen, and a projection device disposed on the rear of the transmissive screen and that projects images from the rear of the transmissive screen to the transmissive screen. The transmissive screen is not limited to being rectangular in shape, and may have the shape of a person, an animal, or another character.

Embodiments of the present invention were described above, but the technical scope of the present invention is not limited to the embodiments above, and is determined on the basis of the claims. Furthermore, equal configurations in which modifications unrelated to the gist of the present invention are added in addition to the claims are also included in the technical scope of the present invention.

In the embodiments described above, values of the control gains and their increased values are stored in a memory or the like. Alternatively, all or some of these values may be calculated by the control unit or a processor so that the values themselves need not be stored in a memory.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention.