Pixel circuit, driving method thereof and display apparatus

The application is a U.S. National Phase Entry of International Application No. PCT/CN2014/085543 filed on Aug. 29, 2014, designating the United States of America and claiming priority to Chinese Patent Application No. 201410238690.4, filed on May 30, 2014. The present application claims priority to and the benefit of the above-identified applications and the above-identified applications are incorporated by reference herein in their entirety.

The present disclosure relates to a pixel circuit, a driving method thereof and a display apparatus.

With the rapid development of display technique, the technique of the semiconductor elements as the core of a display apparatus has been developed rapidly. For the existing display apparatus, an Organic Light Emitting Diode(OLED), as a current-type light-emitting element, is increasingly applied to a field of a high performance display due to its features such as self-luminescence, rapid response, wide view angle, and the capability of being manufactured on a flexible substrate and the like. The OLEDs can be classified into two types, the Passive Matrix Driving OLED(PMOLED) and the Active Matrix Driving OLED(AMOLED). Since an AMOLED display has advantages such as low manufacturing cost, high response speed, power-saving, direct current driving applicable to a mobile device, a wide range of operating temperature, and the like, the AMOLED display is likely to replace the Liquid Crystal Display(LCD) to be a novel flat display of a next generation.

In an existing AMOLED display panel, each of OLEDs comprises a plurality of Thin Film Transistor(TFT) switching circuits. The TFT switching circuit manufactured on a glass substrate with a large size has non-uniformity on electrical parameters such as threshold voltage, mobility or the like due to limitation on production process, manufacturing level and the like, so that the current flowing through the AMOLED not only varies with the variation of the stress of the turn-on voltage generated when the TFT is in a ON state for a long time, but also varies with the drift of the threshold voltage of the TFT. As a result, the uniformity and the constancy on luminance of the display would be affected.

To address the above issues, as known by the inventor(s), in general, an AMOLED pixel compensation circuit would be adopted to compensate for the threshold voltage of TFT. Nevertheless, during the compensation phase, the sum of the data voltage and the threshold voltage(Vdata+Vth), or the sum of the power supply voltage and the threshold voltage(Vdd+Vth), would be written to the gate of the driving transistor. As a result, since the driving transistor is in a diode-connection state at this time, the internal resistance is large; thus, the larger the potential of the gate is, the slower the writing procedure is, and during the limited charging time, it is difficult for the potential Vdata+Vth or Vdd+Vth to be written exactly, thus resulting in a relative large difference between the data output from the Integrated Circuit(IC) and the data actually written to the pixel circuit, decreasing the display effect and quality of the display apparatus.

At least one of embodiments of the present disclosure provides a pixel circuit, a driving method thereof, and a display apparatus, which can reduce the difference between the data output from the Integrated Circuit and the data written to the pixel circuit.

According to one aspect of at least one of embodiments of the present disclosure, there is provided a pixel circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a storage capacitor and a light-emitting element;

a gate of the first transistor is connected to a control line of the light-emitting element, a first electrode of the first transistor is connected to a first voltage, and a second electrode of the first transistor is connected to a first electrode of the third transistor;

a gate of the second transistor is connected to the control line of the light-emitting element, a first electrode of the second transistor is connected to a second electrode of the third transistor, and a second electrode of the second transistor is connected to an anode of the light-emitting element;

a gate of the third transistor is connected to one terminal of the storage capacitor;

a gate of the fourth transistor is connected to a gate line, a first electrode of the fourth transistor is connected to the second electrode of the third transistor, and a second electrode of the fourth transistor is connected to the gate of the third transistor;

a gate of the fifth transistor is connected to the gate line, a first electrode of the fifth transistor is connected to a second electrode of the seventh transistor, and a second electrode of the fifth transistor is connected to a data line;

a gate of the sixth transistor is connected to the gate line, a first electrode of the sixth transistor is connected to an initial voltage, and a second electrode of the sixth transistor is connected to the first electrode of the third transistor;

a gate of the seventh transistor is connected to the control line of the light-emitting element, and a first electrode of the seventh transistor is connected to the first voltage;

the other terminal of the storage capacitor is connected to the second electrode of the seventh transistor;

a cathode of the light-emitting element is connected to a second voltage.

According to another aspect of at least one of embodiments of the present disclosure, there is provided a display apparatus comprising the pixel circuit as described above.

According to a yet aspect of at least one of embodiments of the present disclosure, there is provided a pixel circuit driving method applicable to the pixel circuit as described above, wherein the driving method comprises: turning on the fourth transistor, the fifth transistor and the sixth transistor, so that the third transistor forms a diode connection, and the potentials at the two terminals of the storage capacitor are the data voltage provided by the data line and the sum of the initial voltage and the threshold voltage of the third transistor respectively;

turning off the fourth transistor, the fifth transistor and the sixth transistor, and turning on the first transistor, the second transistor and the seventh transistor, so that the current flowing through the first transistor, the third transistor and the second transistor drives the light-emitting element to emit light.

In the pixel circuit, the driving method thereof, and the display apparatus provided in at least one of embodiments of the present disclosure, the pixel circuit is controlled to be switched on/off and charged/discharged by a plurality of transistors and the storage capacitor, thus reducing the voltage written to the third transistor in the diode connection manner. On the other hand, the current flowing through the third transistor is independent of the threshold voltage of the third transistor and the first voltage; further, since there is no series connection loop formed for the initial voltage, the effect that the inconsistency or drift of the threshold voltage of the third transistor and the IR drop of the initial voltage have on the current flowing through the light-emitting element can be avoided, improving the uniformity of the display luminance of the display apparatus significantly.

FIG. 1 is a schematic diagram of a structure of a pixel circuit provided in an embodiment of the present disclosure;

FIG. 2 is a timing sequence diagram of a pixel circuit in operation which is provided in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an equivalent circuit of the pixel circuit illustrated in FIG. 1 in a writing phase;

FIG. 4 is a schematic diagram of an equivalent circuit of the pixel circuit illustrated in FIG. 1 in a light-emitting phase; and

FIG. 5 is a schematic flowchart of a driving method for a pixel circuit provided in an embodiment of the present disclosure.

Hereinafter, clear and complete descriptions will be given to implementations of the present disclosure with reference to accompanying drawings of the present disclosure. Obviously, the embodiments as described are only a part of the embodiments of the present invention, not all of the embodiments of the present invention. All other embodiments obtained by those skilled in the art on the basis of the embodiments of the present disclosure without paying any creative labor belong to the protection scope of the present disclosure.

FIG. 1 is a schematic diagram of a structure of a pixel circuit provided in an embodiment of the present disclosure. As illustrated in FIG. 1 , the pixel circuit comprises:

a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 , a seventh transistor M 7 , a storage capacitor CST and a light-emitting element D.

A gate of the first transistor M 1 is connected to a control line Em of the light-emitting element D, a first electrode of the first transistor M 1 is connected to a first voltage Vdd, and a second electrode of the first transistor M 1 is connected to a first electrode of the third transistor M 3 .

A gate of the second transistor M 2 is connected to the control line Em of the light-emitting element D, a first electrode of the second transistor M 2 is connected to a second electrode of the third transistor M 3 , and a second electrode of the second transistor M 2 is connected to an anode of the light-emitting element D. It should be noted that in the embodiments of the present disclosure, the control line Em of the light-emitting element D is configured to input a starting signal, and the light-emitting element D is controlled by the starting signal to emit light.

A gate of the third transistor M 3 is connected to one terminal of the storage capacitor CST.

A gate of the fourth transistor M 4 is connected to a gate line Gate, a first electrode of the fourth transistor M 4 is connected to the second electrode of the third transistor M 3 , and a second electrode of the fourth transistor M 4 is connected to the gate of the third transistor M 3 .

A gate of the fifth transistor M 5 is connected to the gate line Gate, a first electrode of the fifth transistor M 5 is connected to a second electrode of the seventh transistor M 7 , and a second electrode of the fifth transistor M 5 is connected to a data line Data.

A gate of the sixth transistor M 6 is connected to the gate line Gate, a first electrode of the sixth transistor M 6 is connected to an initial voltage V_initial, and a second electrode of the sixth transistor M 6 is connected to the first electrode of the third transistor M 3 .

A gate of the seventh transistor M 7 is connected to the control line Em of the light-emitting element D, and a first electrode of the seventh transistor M 7 is connected to the first voltage Vdd.

The other terminal of the storage capacitor CST is connected to the second electrode of the seventh transistor M 7 .

A cathode of the light-emitting element D is connected to a second voltage Vss.

It should be noted that in the embodiment of the present disclosure, the light-emitting element D can be a known current-driving type light-emitting element comprising a Light Emitting Diode(LED) or an OLED. In the embodiments of the present disclosure, the OLED is taken as an example for illustration.

In the pixel circuit provided in the embodiment of the present disclosure, the pixel circuit is controlled to be switched on/off and charged/discharged by a plurality of transistors and the storage capacitor, thus reducing the voltage written to the third transistor in the diode connection manner. On the other hand, the current flowing through the third transistor is independent of the threshold voltage of the third transistor and the first voltage; further, since there is no series connection loop formed for the initial voltage, the effect that the inconsistency or drift of the threshold voltage of the third transistor and the IR drop of the initial voltage have on the current flowing through the light-emitting element can be avoided, improving the uniformity of the display luminance of the display apparatus significantly.

It should be noted that in the embodiments of the present disclosure, the first voltage Vdd can be a high voltage, the second voltage Vss can be a low voltage or an earth terminal voltage.

Herein, the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are all N type transistors; or

the first transistor M 1 , the second transistor M 2 , and the seventh transistor M 7 are all N type transistors; the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , and the sixth transistor M 6 are all P type transistors; or

the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are all P type transistors; or

the first transistor M 1 , the second transistor M 2 , and the seventh transistor M 7 are all P type transistors; the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , and the sixth transistor M 6 are all N type transistors. In a case in which different type transistors are adopted, external control signals of the pixel circuit are different accordingly.

For example, taking P type transistors as an example, in the pixel circuit of the present disclosure, the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 may all be P type enhancement Thin Film Transistors(TFTs) or P type depletion TFTs. Herein, the first electrodes of the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are sources, and the second electrodes thereof are drains.

Hereinafter, taking a case in which the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are all P type enhancement TFTs as an example, a detailed description will be given to the operating procedure of the pixel circuit provided in the embodiment of the disclosure.

When the pixel circuit illustrated in FIG. 1 operates, the operating procedure can be divided into two phases particularly, i.e., a writing phase and a light-emitting phase. FIG. 2 is a timing sequence diagram of respective signal lines during the operating procedure of the pixel circuit illustrated in FIG. 1 . As illustrated in FIG. 2 , P 1 and P 2 represent the writing phase and the light-emitting phase respectively.

FIG. 3 is a schematic diagram of an equivalent circuit of the pixel circuit illustrated in FIG. 1 during the writing phase P 1 . As illustrated in FIG. 3 , the wires and the elements which are turned on are denoted by solid lines, and the units which are not turned on are denoted by dotted lines; the same denotation is adopted in the following equivalent circuit diagrams. During the writing phase P 1 , the data line Data inputs a data voltage(Vdata) at a low level and the gate line Gate inputs a voltage at a low level, and the control line Em of the light-emitting element D inputs a high level signal. As illustrated in FIG. 3 , the fifth transistor M 5 , the sixth transistor M 6 and the fourth transistor M 4 are turned on, and the first transistor M 1 , the second transistor M 2 and the seventh transistor M 7 are turned off. After the sixth transistor M 6 is turned on, the initial voltage V_initial is inputted to a node C where the second electrode of the sixth transistor M 6 and the first electrode of the third transistor M 3 are connected; at the same time, since the fourth transistor M 4 is turned on, the gate and the second electrode of the third transistor M 3 are connected together, so that the third transistor M 3 forms a diode connection. At this time, the voltage at a node b, where the gate of the third transistor M 3 and one terminal of the storage capacitor CST are connected, is increased to V_initial+Vth, after the initial voltage V_initial passes the third transistor M 3 , wherein Vth represents the threshold voltage of the third transistor M 3 . In a case in which the initial voltage V_initial is very low, or is at zero (for example, in a case in which the minimum data voltage (Vdata) and the threshold voltage Vth of the third transistor M 3 are greater than zero, the initial voltage V_initial can be set as zero so as to achieve the function of resetting the voltage at a corresponding node), the voltage actually written to the node b is Vth. Thus, in the pixel circuit provided in the embodiment of the present disclosure, the potential at the gate of the third transistor M 3 (i.e., the driving transistor in the pixel circuit) can be decreased during the writing phase P 1 , and meantime the difference between the data output from the IC and the data written to the pixel circuit can be reduced, thus the writing operation is easier and more accurate.

Further, after the fifth transistor M 5 is turned on, the data line Data inputs the data voltage(Vdata) to a node a at the other terminal of the storage capacitor CST where the second electrode of the seventh transistor M 7 and the first electrode of the fifth transistor M 5 are connected. At this time, the potentials at two terminals of the storage capacitor CST are Vdata at the node a and V_initial+Vth at the node b respectively. Therefore, the potential difference across the storage capacitor CST is Vdata−(V_initial+Vth).

FIG. 4 is a schematic diagram of an equivalent circuit of the pixel circuit illustrated in FIG. 1 during the light-emitting phase P 2 . As illustrated in FIG. 4 , during the light-emitting phase P 2 , the data line Data inputs the data voltage(Vdata) at a high level and the gate line Gate inputs a voltage at a high level, and the control line Em of the light-emitting element D inputs a low level signal. The first transistor M 1 , the second transistor M 2 and the seventh transistor M 7 are turned on. After the seventh transistor M 7 is turned on, the potential at the node a is Vdd; according to the charge retention principle of the storage capacitor CST, the potential at the node b is Vdd−[Vdata−(V_initial+Vth)]. After the first transistor M 1 and the second transistor M 2 are turned on, the potential at the node c is Vdd. At this time, the current flowing through the third transistor M 3 drives the OLED to emit light. Since the third transistor M 3 is in a saturation region, the current flowing through the third transistor M 3 can be obtained from the current characteristics of the TFT in the saturation region:

wherein K represents the current constant related to the third transistor M 3 , Vgs represents the gate-source voltage of the third transistor M 3 , that is, the voltage of the node b with respect to the node c, and Vth represents the threshold voltage of the third transistor M 3 . In general, Vth varies from a pixel unit to another pixel unit, and the Vth of the same pixel might drift with time, which renders difference in display luminance; since such a difference relates to the image as previously displayed, image sticking phenomenon often occurs.

It can be seen that the current Ids flowing through the third transistor M 3 is independent of the first voltage Vdd and the threshold voltage Vth of the third transistor M 3 . Further, in a case in which the initial voltage V_initial is a zero voltage, the current Ids only depends on the data voltage Vdata output from the data line Data. Moreover, since there is no series connection loop formed for the initial voltage V_initial, the effect that the inconsistency or drift of the threshold voltage Vth of the third transistor M 3 and the IR drop of the initial voltage V_initial have on the current flowing through the light-emitting element can be avoided, thus improving the uniformity of the luminance of the display apparatus in display significantly, and preventing the image-sticking phenomenon occurring.

It should be noted that the above embodiments are described by taking a case in which all the transistors are all P type enhancement TFTs as an example. Optionally, P type depletion TFTs can be adopted as all the transistors, and the difference is in that for an enhancement TFT, the threshold voltage Vth is a positive value, and for a depletion TFT, the threshold voltage Vth is a negative value.

Further, the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 may all be N type transistors. The timing sequence of the external signals for driving a pixel circuit adopting such a structure is adjusted accordingly, wherein the timing sequence of the data line Data, the gate line Gate and the control line Em of the light-emitting element D is inverted to that of corresponding signals illustrated in FIG. 2 , that is, there is a phase difference of 180 degrees therebetween.

Optionally, the first transistor M 1 , the second transistor M 2 , and the seventh transistor M 7 are all N type transistors, and the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , and the sixth transistor M 6 are P type transistors. The timing sequence of the external signals for driving a pixel circuit adopting such a structure is adjusted accordingly, wherein the timing sequence of the control line Em of the light-emitting element D is inverted to that of the corresponding signal illustrated in FIG. 2 , that is, there is a phase difference of 180 degrees therebetween.

Optionally, the first transistor M 1 , the second transistor M 2 , and the seventh transistor M 7 are all P type transistors, and the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , and the sixth transistor M 6 are N type transistors. The timing sequence of the external signals for driving a pixel circuit adopting such a structure is adjusted accordingly, wherein the timing sequence of the data line Data and the gate line Gate is inverted to that of the corresponding signals illustrated in FIG. 2 , that is, there is a phase difference of 180 degrees therebetween.

An embodiment of the present disclosure further provides a display apparatus comprising any one of the pixel circuits as described above, wherein the display apparatus can comprise an array of a plurality of pixel units each comprising any one of the pixel circuit as described above, with the same beneficial effect as that of the pixel circuit as provided in the aforementioned embodiments of the present disclosure. Since the pixel circuit has been described in the above embodiments in detail, and the repeated description is omitted.

In particular, the display apparatus provided in the embodiments of the present disclosure can be a display apparatus having a light-emitting element driven by current, such as a LED display, OLED display or the like.

In the display apparatus provided in the embodiment of the present disclosure, a plurality of pixel circuits are included therein, wherein the pixel circuit is controlled to be switched on/off and charged/discharged by a plurality of transistors and the storage capacitor, thus reducing the voltage written to the third transistor in the diode connection manner. On the other hand, the current flowing through the third transistor is independent of the threshold voltage of the third transistor and the first voltage; further, since there is no series connection loop formed for the initial voltage, the effect that the inconsistency or drift of the threshold voltage of the third transistor and the IR drop of the initial voltage have on the current flowing through the light-emitting element can be avoided, improving the uniformity of the display luminance of the display apparatus significantly.

FIG. 5 is a schematic flowchart of a driving method for a pixel circuit provided in an embodiment of the present disclosure. The driving method for the pixel circuit can be applied to the pixel circuit provided in the above embodiments. As illustrated in FIG. 5 , the method comprises steps of:

S 101 : turning on the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 , so that the third transistor M 3 forms a diode connection, and the potentials at the two terminals of the storage capacitor CST are the data voltage Vdata and the sum of the initial voltage V_initial and the threshold voltage Vth of the third transistor M 3 respectively;

S 102 : turning off the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 , and turning on the first transistor M 1 , the second transistor M 2 and the seventh transistor M 7 , so that the current flowing through the first transistor M 1 , the third transistor M 3 and the second transistor M 2 drives the light-emitting element D to emit light.

In the driving method for the pixel circuit provided in the embodiment of the present disclosure, the pixel circuit is controlled to be switched on/off and charged/discharged by a plurality of transistors and the storage capacitor, thus reducing the voltage written to the third transistor in the diode connection manner. On the other hand, the current flowing through the third transistor is independent of the threshold voltage of the third transistor and the first voltage; further, since there is no series connection loop formed for the initial voltage, the effect that the inconsistency or drift of the threshold voltage of the third transistor and the IR drop of the initial voltage have on the current flowing through the light-emitting element can be avoided, improving the uniformity of the display luminance of the display apparatus significantly.

It should be noted that in the embodiment of the present disclosure, the light-emitting element D can be a known current-driving type light-emitting element such as a Light Emitting Diode(LED) or an OLED.

Herein, the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are all N type transistors; or

the first transistor M 1 , the second transistor M 2 , and the seventh transistor M 7 are all N type transistors; the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , and the sixth transistor M 6 are all P type transistors; or

the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are all P type transistors; or

the first transistor M 1 , the second transistor M 2 , and the seventh transistor M 7 are all P type transistors; the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , and the sixth transistor M 6 are all N type transistors. In a case in which different type transistors are adopted, external control signals of the pixel circuit are different accordingly.

For example, taking P type transistors as an example, in the pixel circuit of the present disclosure, the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 may all be P type enhancement TFTs or P type depletion TFTs.

It should be noted that in a case in which the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are all P type enhancement TFTs, the timing sequence of the control signals is illustrated in FIG. 2 , wherein

during the writing phase P 1 , the data line Data inputs a data voltage(Vdata) at a low level and the gate line Gate inputs a voltage at a low level, and the control line Em of the light-emitting element D inputs a high level signal; and

during the light-emitting phase P 2 , the data line Data inputs the data voltage(Vdata) at a high level and the gate line Gate inputs a voltage at a high level, and the control line Em of the light-emitting element D inputs a low level signal.

For instance, in a case in which the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the seventh transistor M 7 are all P type enhancement TFTs, the step S 101 corresponds to the writing phase P 1 , and the equivalent circuit diagram of the pixel circuit during this phase is illustrated in FIG. 3 . Herein, the wires and the elements which are turned on are denoted by solid lines, and the units which are not turned on are denoted by dotted lines; the same denotation is adopted in the following equivalent circuit diagrams. During the writing phase P 1 , the data line Data inputs a data voltage(Vdata) at a low level and the gate line Gate inputs a voltage at a low level, and the control line Em of the light-emitting element D inputs a high level signal. As illustrated in FIG. 3 , the fifth transistor M 5 , the sixth transistor M 6 and the fourth transistor M 4 are turned on, and the first transistor M 1 , the second transistor M 2 and the seventh transistor M 7 are turned off. After the sixth transistor M 6 is turned on, the initial voltage V_initial is inputted to the node c; at the same time, since the fourth transistor M 4 is turned on, the gate and the second electrode of the third transistor M 3 are connected together, so that the third transistor M 3 forms a diode connection. At this time, the voltage at the node b, where the gate of the third transistor M 3 and one terminal of the storage capacitor CST are connected, is increased to V_initial+Vth, after the initial voltage V_initial passes the third transistor M 3 , wherein Vth represents the threshold voltage of the third transistor M 3 . In a case in which the initial voltage V_initial is very low, or is at zero (for example, in a case in which the minimum data voltage (Vdata) and the threshold voltage Vth of the third transistor M 3 are greater than zero, the initial voltage V_initial can be set as zero so as to achieve the function of resetting the voltage at a corresponding node), the voltage actually written to the node b is Vth. Thus, in the pixel circuit provided in the embodiment of the present disclosure, the potential at the gate of the third transistor M 3 can be decreased during the writing phase P 1 , and meantime the difference between the data output from the IC and the data written to the pixel circuit can be reduced, thus the writing operation is easier and more accurate.

Further, after the fifth transistor M 5 is turned on, the data line Data inputs the data voltage(Vdata) to the node a, i.e., the other terminal of the storage capacitor CST. At this time, the potentials at two terminals of the storage capacitor CST are Vdata at the node a and V_initial+Vth at the node b respectively. Therefore, the potential difference across the storage capacitor CST is Vdata−(V_initial+Vth).

Accordingly, the step S 102 corresponds to the light-emitting phase P 2 , and the equivalent circuit diagram of the pixel circuit during this phase is illustrated in FIG. 4 . During this phase, the data line Data inputs the data voltage(Vdata) at a high level and the gate line Gate inputs a voltage at a high level, and the control line Em of the light-emitting element D inputs a low level signal. The first transistor M 1 , the second transistor M 2 and the seventh transistor M 7 are turned on. After the seventh transistor M 7 is turned on, the potential at the node a is Vdd; according to the charge retention principle of the storage capacitor CST, the potential at the node b is Vdd−[Vdata−(V_initial+Vth)]. After the first transistor M 1 and the second transistor M 2 are turned on, the potential at the node c is Vdd. At this time, the current flowing through the third transistor M 3 drives the OLED to emit light. Since the third transistor M 3 is in a saturation region, the current flowing through the third transistor M 3 can be obtained from the current characteristics of the TFT in the saturation region:

wherein K represents the current constant related to the third transistor M 3 , Vgs represents the gate-source voltage of the third transistor M 3 , that is, the voltage of the node b with respect to the node c, and Vth represents the threshold voltage of the third transistor M 3 . In general, Vth varies from a pixel unit to another pixel unit, and the Vth of a same pixel might drift with time, which renders difference in display luminance; since such a difference relates to the image as previously displayed, image sticking phenomenon often occurs.

It can be seen that the current Ids flowing through the third transistor M 3 is independent of the first voltage Vdd and the threshold voltage Vth of the third transistor M 3 . Further, in a case in which the initial voltage V_initial is a zero voltage, the current Ids only depends on the data voltage Vdata output from the data line Data. Moreover, since there is no series connection loop formed for the initial voltage V_initial, the effect that the inconsistency or drift of the threshold voltage Vth of the third transistor M 3 and the IR drop of the initial voltage V_initial have on the current flowing through the light-emitting element can be avoided, thus improving the uniformity of the luminance of the display apparatus in display significantly, and preventing the image-sticking phenomenon occurring.

Those skilled in the art can understand that all or part of steps in the above method/process embodiments can be implemented through hardware instructed by associated computer program. The associated computer program can be stored in a computer readable storage medium, and, when being executed, the steps in the above method/process embodiments are performed. The storage medium can include any kind of medium capable of storing program codes such as ROM, RAM, magnetic disc, optical disc, etc.

The above descriptions are only implementations of the present disclosure, and in no way limit the scope of the present invention. It will be obvious that those skilled in the art may readily conceive variations and equivalences to the above embodiments without departing from the spirit and scope of the present invention as defined by the following claims. Such variations and modifications are intended to be included within the scope of the present invention. The protection scope of the present invention should be defined by the attached claims.

The present application claims the priority of a Chinese application filed on May 30, 2014, with No. 201410238690.4, and the disclosure of which is entirely incorporated herein by reference.