Semiconductor device having hierarchical sense amplifiers assigned to multiple local bit lines

The present invention relates to a semiconductor device, and in particular relates to a semiconductor device having bit lines that are separated hierarchically.

Semiconductor devices, typified by DRAMs (Dynamic Random Access Memory), include those in which the bit lines are separated hierarchically into local bit lines and global bit lines (see patent literature article 1). The local bit lines are lower-order bit lines which are connected to memory cells. Meanwhile, the global bit lines are higher-order bit lines which are connected to global sense amplifiers. Separating the bit lines hierarchically makes it possible to increase the number of memory cells allocated to one global sense amplifier, while reducing the wiring line length of the local bit lines, which have a relatively high electrical resistance.

The semiconductor device described in patent literature article 1 is provided with local sense amplifiers (LSA) connected to local bit lines.

Patent literature article 1: Japanese Patent Kokai 2008-262632

Problems to be Resolved by the Invention

However, the local sense amplifiers described in patent literature article 1 are what are known as single-end type sense amplifiers in which the local bit lines are connected to the gates of input transistors comprising vertical MOS transistors, and therefore, because the sense margin varies as a result of variability in the characteristics of the input transistors contained in the local sense amplifiers, there is a problem in that process control during manufacture is difficult. In patent literature article 1 there is also a problem in that it is necessary to allocate a local sense amplifier to each local bit line.

Means of Overcoming the Problems

The semiconductor device according to the present invention is characterized in that it is provided with: a global bit line; a global sense amplifier which amplifies a signal on the global bit line; first and second local bit lines; a plurality of word lines which each intersect at least one of the first and second local bit lines; a plurality of memory cells disposed at the points of intersection of the plurality of word lines and the first and second local bit lines; first and second hierarchical switches connected respectively between the first and second local bit lines and the global bit line; and a hierarchical sense amplifier which has first and second signal nodes and which amplifies an electric potential difference generated between the first and second signal nodes; wherein the first signal node is connected to the first local bit line, and the second signal node is connected to the second local bit line.

According to the present invention, the hierarchical sense amplifier connected to the local bit lines is a differential-type circuit, and it is therefore possible for stable sensing operations to be performed. Further, because one hierarchical sense amplifier can be allocated to a plurality of local bit lines, it is also possible to reduce the number of hierarchical sense amplifiers.

FIG. 1 is a block diagram illustrating the configuration of a semiconductor device according to a preferred mode of embodiment of the present invention.

FIG. 2 is a circuit diagram used to describe the circuit configuration of a memory cell array region 10 according to a first mode of embodiment of the present invention.

FIG. 3 is an operational waveform diagram used to describe the operation of a semiconductor device according to a preferred first mode of embodiment of the present invention during row access.

FIG. 4 is a circuit diagram used to describe the circuit configuration of a hierarchical sense amplifier HSAx according to a prototype considered by the inventors during the process leading to the present invention.

FIG. 5 is a schematic diagram used to describe the layout when the prototype hierarchical sense amplifier HSAx is employed.

FIG. 6 is a schematic diagram used to describe a first example of the layout when the hierarchical sense amplifier HSA according to the preferred first mode of embodiment of the present invention is employed.

FIG. 7 is a schematic diagram used to describe a second example of the layout when the hierarchical sense amplifier HSA according to the preferred first mode of embodiment of the present invention is employed.

FIG. 8 is a generalized diagram of the hierarchical sense amplifier HSA illustrated in FIG. 2 .

FIG. 9 is a circuit diagram used to describe the circuit configuration of a memory cell array region 10 according to a second mode of embodiment of the present invention.

FIG. 10 is an operational waveform diagram used to describe the operation of a semiconductor device according to the second mode of embodiment of the present invention during a read operation.

FIG. 11 is an operational waveform diagram used to describe the operation of the semiconductor device according to the second mode of embodiment of the present invention during a write operation.

FIG. 12 is a circuit diagram used to describe the circuit configuration of a memory cell array region 10 according to a third mode of embodiment of the present invention.

FIG. 13 is an operational waveform diagram used to describe the operation of a semiconductor device according to the third mode of embodiment of the present invention during a read operation.

FIG. 14 is an operational waveform diagram used to describe a modified example of the operation of the semiconductor device according to the third mode of embodiment of the present invention during a read operation.

Preferred modes of embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating the configuration of a semiconductor device according to a preferred first mode of embodiment of the present invention.

As illustrated in FIG. 1 , the semiconductor device according to this mode of embodiment is a DRAM (Dynamic Random Access Memory) having a memory cell array region 10 . Details are discussed hereinafter, but hierarchically separated global bit lines and local bit lines are provided in the memory cell array region 10 , and memory cells are disposed at the points of intersection of word lines and the local bit lines. The word lines are selected by means of a row-system control circuit 11 , and the global bit lines and the local bit lines are selected by means of a column-system control circuit 12 . Further, hierarchical switches, discussed hereinafter, are connected between the global bit lines and the local bit lines, control thereof also being performed by the row-system control circuit 11 .

A row address RA is supplied to the row-system control circuit 11 by way of a row address buffer 13 . Further, a column address CA is supplied to the column-system control circuit 12 by way of a column address buffer 14 . The row address RA and the column address CA are both address signals ADD supplied from the outside, and a control circuit 18 controls to which of the row address buffer 13 and the column address buffer 14 the address signal ADD is input. The control circuit 18 is a circuit which controls each functional block on the basis of an output from a command decoder 17 which decodes external commands CMD. More specifically, if the external command CMD indicates an active command, the address signal ADD is supplied to the row address buffer 13 . Further, if the external command CMD indicates a read command or a write command, the address signal ADD is supplied to the column address buffer 14 .

Therefore, if an active command and a read command are issued successively, and a row address RA and a column address CA are input in synchronism therewith, data DQ in a memory cell specified by these addresses can be read. Further, if an active command and a write command are issued successively, and a row address RA and a column address CA are input in synchronism therewith, data DQ can be written to a memory cell specified by these addresses. The data DQ are written and read by way of an input/output control circuit 15 and a data buffer 16 .

Further, the semiconductor device according to this mode of embodiment is provided with a mode register 19 , and the set value thereof is supplied to the control circuit 18 . A parameter indicating the operating mode of the semiconductor device according to this mode of embodiment is set in the mode register 19 .

FIG. 2 is a circuit diagram used to describe the circuit configuration of the memory cell array region 10 according to the first mode of embodiment of the present invention.

As illustrated in FIG. 2 , a pair of global bit lines GBLT and GBLB, and a global sense amplifier GSA which amplifies the electric potential difference generated between the global bit lines GBLT and GBLB are contained in the memory cell array region 10 . FIG. 2 depicts only one global sense amplifier GSA, but it goes without saying that in practice the memory cell array region 10 contains multiple global sense amplifiers GSA.

The global sense amplifier GSA has what is known as a flip-flop configuration, in which a power-supply potential VARY is supplied by way of a transistor TSAP 1 to the sources of cross-coupled p-channel MOS transistors, and a ground potential VSS is supplied by way of a transistor TSAN 1 to the sources of cross-coupled n-channel MOS transistors. Sense activation signals SAP 1 and SAN 1 are supplied respectively to the gate electrodes of the transistors TSAP 1 and TSAN 1 . Then, the global bit line GBLT is connected to one signal node N 3 , and the global bit line GBLB is connected to another signal node N 4 . By means of said configuration, if the sense activation signals SAP 1 and SAN 1 are activated, then on the basis of the electric potential difference generated between the pair of global bit lines GBLT and GBLB, one of the global bit lines is driven to the power-supply potential VARY, and the other is driven to the ground potential VSS.

The signal nodes N 3 and N 4 are connected by way of column switches YSW to a local I/O line pair LIOT, LIOB. The column switches YSW turn on in response to a column selection signal YS. Therefore, during a read operation, read data read out by means of the global sense amplifier GSA are transferred to the local I/O line pair LIOT, LIOB by way of the column switches YSW. Further, during a write operation, write data supplied by way of the local I/O line pair LIOT, LIOB are transferred to the global bit lines GBLT and GBLB by way of the column switches YSW. Further, an equalizing circuit EQ 1 is connected between the signal nodes N 3 and N 4 . An equalizing signal BLEQ 1 is supplied to the equalizing circuit EQ 1 , and when the equalizing signal BLEQ 1 activates the equalizing circuit EQ 1 the global bit lines GBLT and GBLB are precharged to an intermediate potential VBLP. The intermediate potential VBLP is a potential between the power-supply potential VARY and the ground potential VSS (=(VARY+VSS)/2).

A hierarchical sense amplifier HSA is connected to the global bit line GBLT. Only one hierarchical sense amplifier HSA connected to the global bit line GBLT is illustrated in FIG. 2 , but in practice two or more hierarchical sense amplifiers HSA can be connected. Further, although not illustrated in FIG. 2 , a hierarchical sense amplifier HSA is also connected to the global bit line GBLB.

The hierarchical sense amplifier HSA has the same flip-flop configuration as the global sense amplifier GSA, the power-supply potential VARY being supplied by way of a transistor TSAP 0 to the sources of cross-coupled p-channel MOS transistors, and the ground potential VSS being supplied by way of a transistor TSAN 0 to the sources of cross-coupled n-channel MOS transistors. Sense activation signals SAP 0 and SAN 0 are supplied respectively to the gate electrodes of the transistors TSAP 0 and TSAN 0 . By means of said configuration, if the sense activation signals SAP 0 and SAN 0 are activated, then on the basis of the electric potential difference generated between signal nodes N 1 and N 2 , one of the signal nodes is driven to the power-supply potential VARY, and the other is driven to the ground potential VSS.

An equalizing circuit EQ 0 is connected between the signal nodes N 1 and N 2 . An equalizing signal BLEQ 0 is supplied to the equalizing circuit EQ 0 , and when the equalizing signal BLEQ 0 activates the equalizing circuit EQ 0 the signal nodes N 1 and N 2 are precharged to the intermediate potential VBLP.

The signal node N 1 of the hierarchical sense amplifier HSA is connected to local bit lines LBL 1 and LBL 3 by way of selection switches SELSW 1 and SELSW 3 . Similarly, the signal node N 2 of the hierarchical sense amplifier HSA is connected to local bit lines LBL 2 and LBL 4 by way of selection switches SELSW 2 and SELSW 4 . The local bit lines LBL 1 to LBL 4 are connected to the global bit line GBLT by way of hierarchical switches HSW 1 to HSW 4 respectively. The hierarchical switches HSW 1 to HSW 4 comprise n-channel MOS transistors, and they conduct in response to connection signals TG 1 to TG 4 respectively. Further, the selection switches SELSW 1 to SELSW 4 also comprise n-channel MOS transistors, and they conduct in response to selection signals SEL 1 to SEL 4 .

As illustrated in FIG. 2 , the local bit lines LBL 1 and LBL 3 belong to a submat SMAT 1 , and the local bit lines LBL 2 and LBL 4 belong to a submat SMAT 2 . Only one word line WL 1 allocated to the submat SMAT 1 and one word line WL 2 allocated to the submat SMAT 2 are depicted in FIG. 2 , but in practice a plurality of word lines are allocated to each submat SMAT 1 and SMAT 2 . The word line WL 1 allocated to the submat SMAT 1 intersects the local bit lines LBL 1 and LBL 3 , and the word line WL 2 allocated to the submat SMAT 2 intersects the local bit lines LBL 2 and LBL 4 .

The memory cells of the DRAM are disposed at the points of intersection of the word lines and the local bit lines. FIG. 2 depicts only memory cells MC 1 and MC 3 disposed respectively at the points of intersection of the word line WL 1 and the local bit lines LBL 1 and LBL 3 , and memory cells MC 2 and MC 4 disposed respectively at the points of intersection of the word line WL 2 and the local bit lines LBL 2 and LBL 4 , but in practice multiple memory cells MC are provided in each submat. The memory cells MC 1 to MC 4 have a configuration in which a cell transistor TR and a cell capacitor C are connected in series between the corresponding local bit line LBL and a plate wiring line VPLT, and the gate electrode of the cell transistor TR is connected to the corresponding word line WL.

The circuit configuration of the memory cell array region 10 is as described hereinbove. The operation of the semiconductor device according to this mode of embodiment will now be described.

As has already been explained, access to the semiconductor device in this mode of embodiment is effected by successively issuing an active command and a read command or a write command, and inputting the row address RA and the column address CA in synchronism therewith. Here, if the row address RA is input in synchronism with an active command, then row access, in other words a word line selection operation and a concomitant sensing operation, is performed, and if the column address CA is input in synchronism with a read command or a write command then column access, in other words a global sense amplifier GSA selection operation and a concomitant read data input operation or write data output operation, is performed. Of these, the semiconductor device according to this mode of embodiment is characterized by its operation during row access, and therefore the operation during row access will now be described in detail.

FIG. 3 is an operational waveform diagram used to describe the operation of the semiconductor device according to this mode of embodiment during row access.

A period T 0 up to a time t 10 illustrated in FIG. 3 is a precharge period prior to the time at which the row access is performed. During the period T 0 , the selection signals SEL 1 to SEL 4 are all at the high level, and the connection signals TG 1 to TG 4 are all at the low level. In other words, the state is such that the local bit lines LBL 1 to LBL 4 are disconnected from the global bit line GBLT, and the local bit lines LBL 1 to LBL 4 are connected to the hierarchical sense amplifier HSA. Further, the equalizing signals BLEQ 0 and BLEQ 1 are both at the high level, and therefore the global bit line GBLT and the local bit lines LBL 1 to LBL 4 are all precharged to the intermediate potential VBLP.

If in this state the row address RA is input in synchronism with an active command, then the control circuit 18 and the row-system control circuit 11 illustrated in FIG. 1 begin the row access described hereinbelow. The following description describes an example in which the row address RA indicating the memory cell MC 1 illustrated in FIG. 2 is input. It should be noted that the following operation is executed mainly under the control of the control circuit 18 and the row-system control circuit 11 .

When the row address RA indicating the memory cell MC 1 is input, at the time t 10 the equalizing signal BLEQ 0 is changed to the low level, and the selection signals SEL 3 and SEL 4 are changed to the low level. By this means, the precharge state of the local bit lines LBL 1 to LBL 4 is released, and the local bit lines LBL 3 and LBL 4 are isolated from the hierarchical sense amplifier HSA. The local bit lines LBL 1 and LBL 2 remain in a state in which they are connected to the hierarchical sense amplifier HSA. This operation continues until a time t 11 . A period T 1 between the times t 10 and t 11 is a period for release of the precharge state.

At the time t 11 , the word line WL 1 changes from a VKK level to a VPP level. The VPP level is an electric potential which turns on the cell transistors TR contained in the memory cells MC, and by this means the cell capacitors C which are constituents of the memory cells MC 1 and MC 3 are respectively connected to the corresponding local bit lines LBL 1 and LBL 3 .

Here, the reference code A in FIG. 3 indicates operations for a case in which high-level and low-level data are respectively being held in the memory cells MC 1 and MC 3 , where the reference code A 1 indicates changes in the potentials of the signal nodes N 1 and N 2 of the hierarchical sense amplifier HSA, the reference code A 2 indicates changes in the potentials of a storage node SN 1 of the memory cell MC 1 , the local bit line LBL 1 and the global bit lines GBLT and GBLB, and the reference code A 3 indicates changes in the potentials of a storage node SN 3 of the memory cell MC 3 and the local bit line LBL 3 . This is also the case in FIG. 10 , FIG. 11 , FIG. 13 and FIG. 14 discussed hereinafter. Meanwhile, the reference code B indicates operations for a case in which low-level and high-level data are respectively being held in the memory cells MC 1 and MC 3 , where the waveforms indicated by the reference codes B 1 to B 3 correspond to the waveforms indicated by the reference codes A 1 to A 3 .

As indicated by the reference code A in FIG. 3 , if high-level and low-level data are being held in the memory cells MC 1 and MC 3 respectively, then when the word line WL 1 is activated to the VPP level, charge sharing causes the electric potential of the local bit line LBL 1 to rise slightly from the intermediate potential VBLP, and the electric potential of the local bit line LBL 3 to fall slightly from the intermediate potential VBLP. Conversely, as indicated by the reference code B, if low-level and high-level data are being held in the memory cells MC 1 and MC 3 respectively, then when the word line WL 1 is activated to the VPP level, charge sharing causes the electric potential of the local bit line LBL 1 to fall slightly from the intermediate potential VBLP, and the electric potential of the local bit line LBL 3 to rise slightly from the intermediate potential VBLP. During the corresponding period T 2 , the selection switch SELSW 1 is on and the selection switch SELSW 3 is off, and therefore in the former case, as indicated by the reference code A 1 , the electric potential of the signal node N 1 rises, and in the latter case, as indicated by the reference code B 1 , the electric potential of the signal node N 1 falls. It should be noted that in both cases, the electric potential of the signal node N 2 remains at the intermediate potential VBLP.

Then, at a time t 12 , the sense activation signals SAP 0 and SAN 0 are activated, and the electric potential difference generated between the signal nodes N 1 and N 2 is amplified. Therefore, in the case indicated by the reference code A 1 , the local bit line LBL 1 is driven to the power-supply potential VARY and the local bit line LBL 2 is driven to the ground potential VSS. Conversely, in the case indicated by the reference code B 1 , the local bit line LBL 1 is driven to the ground potential VSS and the local bit line LBL 2 is driven to the power-supply potential VARY. In both cases, because the selection switch SELSW 3 is off, the electric potential of the local bit line LBL 3 does not change even when the sense activation signals SAP 0 and SAN 0 are activated.

Further, concurrent with the abovementioned sensing operation, the equalizing signal BLEQ 1 is changed to the low level, and therefore the precharge state of the global bit lines GBLT and GBLB is released. These operations continue until a time t 13 . A period T 3 between the times t 12 and t 13 is a period for amplification of the electric potential of the local bit line LBL 1 .

Then, at the time t 13 , the connection signal TG 1 is activated to the VPP level, turning on the hierarchical switch HSW 1 . The other connection signals TG 2 to TG 4 are maintained in an inactive state. By this means, the local bit line LBL 1 is connected to the global bit line GBLT, and charge sharing takes place between these two bit lines. Therefore in the case indicated by the reference code A 2 , the electric potential of the global bit line GBLT rises, and in the case indicated by the reference code B 2 , the electric potential of the global bit line GBLT falls. In both cases, the electric potential of the other global bit line GBLB is maintained at the intermediate potential VBLP, and therefore an electric potential difference is generated between the signal nodes N 3 and N 4 of the global sense amplifier GSA.

At a time t 14 , the sense activation signals SAP 1 and SAN 1 are activated, and the electric potential difference generated between the signal nodes N 3 and N 4 is amplified. Therefore, in the case indicated by the reference code A 2 , the global bit line GBLT is driven to the power-supply potential VARY and the global bit line GBLB is driven to the ground potential VSS. Conversely, in the case indicated by the reference code B 2 , the global bit line GBLT is driven to the ground potential VSS and the global bit line GBLB is driven to the power-supply potential VARY. As a result, the data read from the memory cell MC 1 are immediately re-stored by means of the global sense amplifier GSA and the hierarchical sense amplifier HSA.

The sensing state is subsequently maintained until a precharge command is issued (until a time t 18 ). A column access can therefore be executed by inputting the column address CA in synchronism with a read command or a write command.

While the column access is being executed, the data read from the memory cell MC 3 are re-stored. First, at a time t 15 the selection signals SEL 1 and SEL 2 are changed to the low level, and the equalizing signal BLEQ 0 is activated. By this means, all the selection switches SELSW 1 to SELSW 4 enter the off state, and the signal nodes N 1 and N 2 in the hierarchical sense amplifier HSA are again precharged to the intermediate potential VBLP. This operation continues until a time t 16 . A period T 6 between the times t 15 and t 16 is a re-precharge period for re-storing of the data to the memory cell MC 3 .

Next, at the time t 16 the selection signals SEL 3 and SEL 4 are changed to the high level. By this means, the selection switches SELSW 3 and SELSW 4 are turned on, and therefore the local bit lines LBL 3 and LBL 4 are respectively connected to the signal nodes N 1 and N 2 of the hierarchical sense amplifier HSA. Therefore, in the case indicated by the reference code A 1 in FIG. 3 , the electric potential of the signal node N 1 falls slightly from the intermediate potential VBLP, and in the case indicated by the reference code B 1 , the electric potential of the signal node N 1 rises slightly from the intermediate potential VBLP.

Then, at a time t 17 , the sense activation signals SAP 0 and SAN 0 are again activated, and the electric potential difference generated between the signal nodes N 1 and N 2 is amplified. Therefore, in the case indicated by the reference code A 1 , the local bit line LBL 3 is driven to the ground potential VSS and the local bit line LBL 4 is driven to the power-supply potential VARY. Conversely, in the case indicated by the reference code B 1 , the local bit line LBL 3 is driven to the power-supply potential VARY and the local bit line LBL 4 is driven to the ground potential VSS. By this means the data read from the memory cell MC 3 are correctly re-stored.

When a precharge command is subsequently issued, at a time t 18 the word line WL 1 is deactivated, all the selection signals SEL 1 to SEL 4 are set to the high level and all the selection signals TG 1 to TG 4 are set to the low level. Further, both equalizing signals BLEQ 0 and BLEQ 1 are set to the high level. In other words, the state returns to the same state as that up to the time t 10 , and the next row access can be executed.

The operation of the semiconductor device according to this mode of embodiment is as described above. Thus in the semiconductor circuit according to this mode of embodiment the hierarchical sense amplifier HSA has a differential-type flip-flop circuit configuration, and stable sensing operations can therefore be performed.

Further, because the hierarchical sense amplifier HSA can itself perform the re-storing operation, a re-storing operation for a memory cell (MC 3 in the example in FIG. 3 ) that is not being accessed can be performed concurrently with a read operation of a memory cell (MC 1 in the example in FIG. 3 ) that is being accessed. This means that it is not necessary to separate the word line corresponding to the memory cell MC 1 from the word line corresponding to the memory cell MC 3 , and therefore the array configuration can be simplified. Moreover, the re-storing operation to the memory cell MC 3 that is not being accessed can be executed concurrently with the column access to the memory cell MC 1 being accessed, and therefore the access efficiency does not deteriorate as a result of said re-storing operation.

Further, two or more pairs of local bit lines can be allocated to one hierarchical sense amplifier HSA, and it is therefore also possible to increase the hierarchical sense amplifier HSA arrangement pitch. Further, more local bit lines LBL can be allocated to one global bit line GBL, and it is therefore also possible to reduce the number of global sense amplifiers GSA.

FIG. 4 is a circuit diagram used to describe the circuit configuration of a hierarchical sense amplifier HSAx according to a prototype considered by the inventors during the process leading to the present invention.

The hierarchical sense amplifier HSAx illustrated in FIG. 4 is provided with control transistors CT 1 and CT 2 connected respectively between a signal node Nx and local bit lines LBL 1 and LBL 2 , a write transistor WT connected between a global bit line GBLx and the signal node Nx, and a read transistor RT connected between the global bit line GBLx and a sense transistor ST. The gate electrode of the sense transistor ST is connected to the signal node Nx, and therefore if the electric potential of the signal node Nx exceeds the threshold of the sense transistor ST, the global bit line GBLx is discharged to a low potential VSNL by way of the read transistor RT.

The operation of the hierarchical sense amplifier HSAx is as follows. First, precharging transistors PC 1 and PC 2 are turned on, thereby precharging the local bit lines LBL 1 and LBL 2 to the low potential VSNL, after which the precharge state is released. Next, data held in the memory cell MC 1 are read out to the local bit line LBL 1 by activating the word line WL 1 , for example.

Here, if the data held in the memory cell MC 1 are low-level data, the electric potential of the local bit line LBL 1 is maintained at the low potential VSNL, and therefore the control transistor CT 1 , which has the local bit line LBL 1 as its source side, enters a state in which its threshold is exceeded, and it turns on. By this means, the electric potential of the signal node Nx falls, and the sense transistor ST turns off. In this case, the electric potential of the global bit line GBLTx does not change even if the read transistor RT turns on.

Meanwhile, if the data held in the memory cell MC 1 are high-level data, the electric potential of the local bit line LBL 1 rises slightly from the low potential VSNL. Therefore the control transistor CT 1 , which has the local bit line LBL 1 as its source side, enters a state in which its threshold is not exceeded, and it turns off By this means, the electric potential of the signal node Nx is maintained in the precharge state, and the sense transistor ST turns on. In this case, the electric potential of the global bit line GBLTx is discharged to the low potential VSNL when the read transistor RT turns on.

The hierarchical sense amplifier HSAx having such a configuration determines whether the data that have been read out are high-level or low-level data on the basis of the threshold voltages of the control transistors CT 1 and CT 2 , and therefore variability in the characteristics of the control transistors CT 1 and CT 2 results in variations in the sense margin. This gives rise to the problem that process control during manufacture is difficult.

Further, as illustrated in FIG. 5 , if the hierarchical sense amplifier HSAx illustrated in FIG. 4 is employed, its arrangement pitch is twice the arrangement pitch of the local bit lines LBL, and therefore the density with which the hierarchical sense amplifiers HSAx must be disposed is very high. For example, if the arrangement pitch of the local bit lines LBL is 2F (where F is a minimum processing dimension), then the arrangement pitch of the hierarchical sense amplifiers HSAx is 4F. In contrast, as illustrated in FIG. 6 , if the hierarchical sense amplifier HSA illustrated in FIG. 2 is employed, its arrangement pitch can be increased to four times the arrangement pitch of the local bit lines LBL (8F). This generates spare space in the layout of the hierarchical sense amplifiers HSA, and it is therefore also possible to reduce the width of the hierarchical sense amplifiers HSA in the local bit line LBL direction. This gives rise to a reduction in the size of the memory cell array region 10 . Further, even if the width of the hierarchical sense amplifiers HSA is not reduced, processing rules can be relaxed.

It should be noted that the layout illustrated in FIG. 6 is an example in which the hierarchical sense amplifiers HSA are disposed in a dispersed manner, and in which the local bit lines LBL are connected alternately to hierarchical sense amplifiers HSA located to the left and the right. In other words, one local bit line LBL connected to a certain hierarchical sense amplifier HSA is disposed between two local bit lines LBL connected to another hierarchical sense amplifier HSA. The F-value in the hierarchical sense amplifier HSA can thus be relaxed, and this has the merit that if in the future it becomes problematic to arrange bit lines (tungsten wiring lines), in particular, within the hierarchical sense amplifier HSA, relaxing the F-value allows the hierarchical sense amplifier HSA to be laid out up to one generation ahead.

In contrast, the layout illustrated in FIG. 7 is an example in which the hierarchical sense amplifiers HSA are disposed in a centralized manner, and in which the two local bit lines LBL connected to each hierarchical sense amplifier HSA do not have another wiring line disposed therebetween. With such a layout, it is not necessary to provide hierarchical sense amplifiers HSA in the end portions of the memory cell array region, in addition to which the total number of hierarchical sense amplifiers HSA is reduced, and it is therefore possible to reduce the size of the memory cell array region 10 further. It should be noted that with the layout illustrated in FIG. 6 , local bit lines LBL which serve as a reference side do not exist in the hierarchical sense amplifiers HSA located in the end portions, and in some cases the sensing operation may therefore be problematic. In order to prevent such problems it is necessary to implement countermeasures such as obtaining a balance between the signal nodes N 1 and N 2 by turning off the selection switches SELSW 1 to SELSW 4 immediately prior to starting sensing, and there is thus a possibility that another problem may arise, namely that it is necessary for only the hierarchical sense amplifiers HSA located in the end portions to be controlled using a different sequence. In contrast, such problems do not arise if the layout illustrated in FIG. 7 is employed.

It should be noted that the layout illustrated in FIG. 7 has the merits that, although the hierarchical sense amplifiers HSA themselves have the same F-value as in the prior art, by laying out the hierarchical sense amplifiers HSA in a centralized manner it is possible to minimize the separation region between the array and the hierarchical sense amplifiers, and by sharing part of the logic, the surface area can be reduced compared with the prior art.

A second mode of embodiment of the present invention will now be described.

FIG. 9 is a circuit diagram used to describe the circuit configuration of the memory cell array region 10 according to the second mode of embodiment of the present invention.

As illustrated in FIG. 9 , the memory cell array region 10 according to this mode of embodiment differs from the memory cell array region 10 illustrated in FIG. 2 in that hierarchical switches HSW 5 and HSW 6 have been added. Further, FIG. 9 illustrates an example in which, in order to provide a region in the hierarchical sense amplifier HSA in which to dispose the hierarchical switches HSW 5 and 6 , the hierarchical switches HSW 1 and 3 are disposed on the submat SMAT 1 and the hierarchical switches HSW 2 and 4 are disposed on the submat SMAT 2 , but this mode of embodiment is not limited to this configuration. If there is spare space in the region in which the hierarchical sense amplifier HSA is disposed, the hierarchical switches HSW 1 to 4 may be disposed on the hierarchical sense amplifier HSA side as illustrated in FIG. 2 . Other points are the same as for the memory cell array region 10 illustrated in FIG. 2 , and therefore the same reference codes are appended to the same elements, and duplicate descriptions are omitted.

The hierarchical switch HSW 5 comprises an n-channel MOS transistor connected between the signal node N 1 of the hierarchical sense amplifier HSA and the global bit line GBLT, and a connection signal TG 5 is supplied to the gate electrode thereof. Further, the hierarchical switch HSW 6 comprises an n-channel MOS transistor connected between the signal node N 2 of the hierarchical sense amplifier HSA and the global bit line GBLT, and a connection signal TG 6 is supplied to the gate electrode thereof. Thus the hierarchical switches HSW 5 and HSW 6 are connected directly to the signal nodes N 1 and N 2 of the hierarchical sense amplifier HSA, and they can therefore connect the hierarchical sense amplifier HSA to the global bit line GBLT even if all the selection switches SELSW 1 to SELSW 4 are in the off state.

FIG. 10 is an operational waveform diagram used to describe the operation of the semiconductor device according to this mode of embodiment during a read operation. In FIG. 10 , the same reference codes have been appended to timings and periods corresponding to the timings and periods illustrated in FIG. 3 . This is also the case in FIG. 11 , FIG. 13 and FIG. 14 discussed hereinafter.

A period T 0 up to a time t 10 illustrated in FIG. 10 is a precharge period prior to the time at which the row access is performed. During the period T 0 , the selection signals SEL 1 to SEL 4 are all at the high level, and the connection signals TG 1 to TG 6 are all at the low level. In other words, the state is such that the local bit lines LBL 1 to LBL 4 are disconnected from the global bit line GBLT, and the local bit lines LBL 1 to LBL 4 are connected to the hierarchical sense amplifier HSA. Further, the equalizing signals BLEQ 0 and BLEQ 1 are both at the high level, and therefore the global bit line GBLT and the local bit lines LBL 1 to LBL 4 are all precharged to the intermediate potential VBLP.

If in this state the row address RA is input in synchronism with an active command, then the control circuit 18 and the row-system control circuit 11 illustrated in FIG. 1 begin the row access described hereinbelow. The following description describes an example in which the row address RA indicating the memory cell MC 1 illustrated in FIG. 9 is input. It should be noted that the following operation is executed mainly under the control of the control circuit 18 and the row-system control circuit 11 .

When the row address RA indicating the memory cell MC 1 is input, at the time t 10 the equalizing signal BLEQ 0 is changed to the low level, and the selection signals SEL 3 and SEL 4 are changed to the low level. By this means, the precharge state of the local bit lines LBL 1 to LBL 4 is released, and the local bit lines LBL 3 and LBL 4 are isolated from the hierarchical sense amplifier HSA. The local bit lines LBL 1 and LBL 2 remain in a state in which they are connected to the hierarchical sense amplifier HSA. This operation continues until a time t 11 . A period T 1 between the times t 10 and t 11 is a period for release of the precharge state.

At the time t 11 , the word line WL 1 changes from a VKK level to a VPP level. The cell capacitors C, which are constituents of the memory cells MC 1 and MC 3 , are thus connected respectively to the corresponding local bit lines LBL 1 and LBL 3 . If high-level and low-level data are being held in the memory cells MC 1 and MC 3 respectively, then charge sharing causes the electric potential of the local bit line LBL 1 to rise slightly from the intermediate potential VBLP, and the electric potential of the local bit line LBL 3 to fall slightly from the intermediate potential VBLP. During the corresponding period T 2 , the selection switch SELSW 1 is on and the selection switch SELSW 3 is off, and therefore the electric potential of the signal node N 1 rises, as indicated by the reference code A 1 . It should be noted that the electric potential of the signal node N 2 remains at the intermediate potential VBLP.

Next, before the sense activation signals SAP 0 and SAN 0 are activated at a time t 12 , the selection signals SEL 1 and SEL 2 are returned to the low level at a time t 111 . All the selection switches SELSW 1 to SELSW 4 thus enter the off state while an electric potential difference is being generated between the signal nodes N 1 and N 2 .

Then, at the time t 12 , the sense activation signals SAP 0 and SAN 0 are activated, and the electric potential difference generated between the signal nodes N 1 and N 2 is amplified. Therefore the signal node N 1 is driven to the power-supply potential VARY and the signal node N 2 is driven to the ground potential VSS. However, because at this point in time all the selection switches SELSW 1 to SELSW 4 are off, the electric potentials of the local bit lines LBL 1 to LBL 4 do not change, and are maintained at the initial electrical potentials immediately after reading. In other words, because the local bit lines LBL 1 and LBL 2 are not being driven at this point in time, noise resulting from variations in the electric potentials of the local bit lines LBL 1 and LBL 2 does not affect the adjacent local bit lines LBL 3 and LBL 4 .

Further, concurrent with the abovementioned sensing operation, the equalizing signal BLEQ 1 is changed to the low level, and therefore the precharge state of the global bit lines GBLT and GBLB is released. These operations continue until a time t 13 . A period T 3 between the times t 12 and t 13 is a period for amplification of the electric potential of the signal nodes N 1 and N 2 .

Then, at the time t 13 , the connection signal TG 5 is activated to the VPP level, turning the hierarchical switch HSW 5 on. The other connection signals TG 1 to TG 4 and TG 6 are maintained in an inactive state. By this means, the signal node N 1 is connected to the global bit line GBLT, and charge sharing takes place between the signal node N 1 and the global bit line GBLT. Therefore the electric potential of the global bit line GBLT rises, as indicated by the reference code A 2 . The electric potential of the other global bit line GBLB is maintained at the intermediate potential VBLP, and therefore an electric potential difference is generated between the signal nodes N 3 and N 4 of the global sense amplifier GSA.

At a time t 14 , the sense activation signals SAP 1 and SAN 1 are activated, and the electric potential difference generated between the signal nodes N 3 and N 4 is amplified. Therefore, as indicated by the reference code A 2 , the global bit line GBLT is driven to the power-supply potential VARY and the global bit line GBLB is driven to the ground potential VSS. However, at this point in time the local bit lines LBL 1 to LBL 4 are being maintained at the initial electrical potentials immediately after reading, and therefore the data read from the memory cells MC 1 and MC 3 have not been re-stored. The data are re-stored by means of the following procedure.

First, at a time t 141 the connection signal TG 5 is returned to the VSS level, thereby turning the hierarchical switch HSW 5 off Next, at a time t 15 the equalizing signal BLEQ 0 is activated. By this means, the signal nodes N 1 and N 2 in the hierarchical sense amplifier HSA are again precharged to the intermediate potential VBLP. This operation continues until a time t 16 . A period T 6 between the times t 15 and t 16 is a re-precharge period for re-storing of the data to the memory cell MC 3 .

Next, at the time t 16 the equalizing signal BLEQ 0 is deactivated and the selection signals SEL 3 and SEL 4 are changed to the high level. By this means, the selection switches SELSW 3 and SELSW 4 are turned on, and therefore the local bit lines LBL 3 and LBL 4 are respectively connected to the signal nodes N 1 and N 2 of the hierarchical sense amplifier HSA. Therefore, as indicated by the reference code A 1 , the electric potential of the signal node N 1 falls slightly from the intermediate potential VBLP.

Next, before the sense activation signals SAP 0 and SAN 0 are activated at a time t 17 , the selection signals SEL 3 and SEL 4 are returned to the low level at a time t 161 . Thus all the selection switches SELSW 1 to SELSW 4 again enter the off state while an electric potential difference is being generated between the signal nodes N 1 and N 2 .

Then, at a time t 17 , the sense activation signals SAP 0 and SAN 0 are activated, and the electric potential difference generated between the signal nodes N 1 and N 2 is amplified. Therefore the signal node N 1 is driven to the ground potential VSS and the signal node N 2 is driven to the power-supply potential VARY. However, because at this point in time all the selection switches SELSW 1 to SELSW 4 are off, the electric potentials of the local bit lines LBL 1 to LBL 4 do not change, and are maintained at the initial electrical potentials immediately after reading.

The state achieved by means of the operations discussed hereinabove is such that the data read from the memory cell MC 1 are held in the global sense amplifier GSA, and the data read from the memory cell MC 3 are held in the hierarchical sense amplifier HSA. However, at this point in time the data have not yet been re-stored. During this interval, a column access can be executed by inputting the column address CA in synchronism with a read command.

Then, during a period between a time t 171 and a time t 172 , the connection signal TG 1 and the selection signals SEL 3 and SEL 4 are activated. The hierarchical switch HSW 1 and the selection switches SELSW 3 and SELSW 4 are thus turned on, and therefore the data being held in the global sense amplifier GSA are re-stored to the memory cell MC 1 by way of the hierarchical switch HSW 1 , and the data being held in the hierarchical sense amplifier HSA are re-stored to the memory cell MC 3 by way of the selection switch SELSW 3 .

When a precharge command is subsequently issued, at a time t 18 the word line WL 1 is deactivated, all the selection signals SEL 1 to SEL 4 are set to the high level and all the selection signals TG 1 to TG 6 are set to the low level. Further, both equalizing signals BLEQ 0 and BLEQ 1 are set to the high level. In other words, the state returns to the same state as that up to the time t 10 , and the next row access can be executed.

The read operation in the semiconductor device according to this mode of embodiment is as described above. Thus in this mode of embodiment, the hierarchical sense amplifier HSA is activated while all the selection switches SELSW 1 to SELSW 4 have been set to the off state, and therefore the effects of signal noise between the local bit lines can be eliminated. It should be noted that in the example illustrated in FIG. 10 , the re-storing operation to the memory cell MC 1 is executed simultaneously with the re-storing operation to the memory cell MC 3 , but these operations need not be executed simultaneously.

FIG. 11 is an operational waveform diagram used to describe the operation of the semiconductor device according to this mode of embodiment during a write operation.

As illustrated in FIG. 11 , the write operation in the semiconductor device according to this mode of embodiment is essentially the same as the read operation illustrated in FIG. 10 . In the example illustrated in FIG. 11 , the write data are input at the time t 16 , thereby inverting the electric potentials of the global bit lines GBLT and GBLB. Thus in the re-storing operation performed in the period between the time t 171 and the time t 172 , the write data being held in the global sense amplifier GSA are written to the memory cell MC 1 by way of the hierarchical switch HSW 1 . It should be noted that in the example illustrated in FIG. 11 , the write operation to the memory cell MC 1 is executed simultaneously with the re-storing operation to the memory cell MC 3 , but these operations need not be executed simultaneously.

A third mode of embodiment of the present invention will now be described.

FIG. 12 is a circuit diagram used to describe the circuit configuration of the memory cell array region 10 according to the third mode of embodiment of the present invention.

As illustrated in FIG. 12 , the memory cell array region 10 according to this mode of embodiment differs from the memory cell array region 10 illustrated in FIG. 9 in that precharging transistors PTR 1 to PTR 4 have been added. Other points are the same as for the memory cell array region 10 illustrated in FIG. 9 , and therefore the same reference codes are appended to the same elements, and duplicate descriptions are omitted.

The precharging transistors PTR 1 to PTR 4 comprise n-channel MOS transistors connected respectively between the local bit lines LBL 1 to LBL 4 and wiring lines to which the intermediate potential VBLP is supplied, and precharging signals LPR 1 to LPR 4 are supplied to the gate electrodes thereof. The precharging transistors PTR 1 to PTR 4 are transistors for directly precharging the local bit lines LBL 1 to LBL 4 , and this mode of embodiment is characterized by the provision of said transistors.

FIG. 13 is an operational waveform diagram used to describe the operation of the semiconductor device according to this mode of embodiment during a read operation.

The read operation in this mode of embodiment is essentially the same as the operation described with reference to FIG. 10 , but as illustrated in FIG. 13 , the operation differs from the operation illustrated in FIG. 10 in that the connection signal TG 1 is activated in a period between a time t 142 and a time t 173 , the selection signals SEL 3 and SEL 4 are activated in a period between the time t 173 and a time t 174 , and the precharging signals PTR 1 to PTR 4 are activated in a period between a time t 175 and a time 176 . Other operations are the same as for the operation described with reference to FIG. 10 , and therefore duplicate descriptions are omitted.

In this mode of embodiment, because the connection signal TG 1 is activated in the period between the time t 142 and the time t 173 , the hierarchical switch HSW 1 turns on in this period. Re-storing to the memory cell MC 1 is thereby executed at this point in time. Further, because the selection signals SEL 3 and SEL 4 are activated in the period between the time t 173 and the time t 174 , the selection signals SEL 3 and SEL 4 are turned on in this period. Re-storing to the memory cell MC 3 is thereby executed at this point in time. It should be noted that in the example illustrated in FIG. 13 , the timing (time t 173 ) of the completion of the re-store to the memory cell MC 1 coincides with the timing (time t 173 ) of the start of the re-store to the memory cell MC 3 , but this point is not essential.

Then, when the precharging signals PTR 1 to PTR 4 are activated in the period between the time t 175 and the time t 176 , the precharging transistors PTR 1 to PTR 4 are turned on, and the local bit lines LBL 1 to LBL 4 are directly precharged to the intermediate potential VBLP. Thus, during the period up until a precharge command is issued, the local bit lines LBL 1 to LBL 4 are maintained at the intermediate potential VBLP, and the loss of data as a result of what is known as a floating body effect can therefore be prevented.

The floating body effect is a phenomenon whereby the leakage current increases in a floating body transistor having an SOI (Silicon on Insulator) construction, for example, and if this occurs in a memory cell transistor, there is a risk that the charge accumulated in the cell capacitor will be lost. The floating body effect becomes pronounced if the electric potentials of the local bit lines are potentials that differ from the intermediate potential VBLP, and therefore the loss of charge can be suppressed to the minimum by maintaining the local bit lines at the intermediate potential VBLP.

In other words, in the second mode of embodiment discussed hereinabove, during the period up until when the data are re-stored to the memory cells MC 1 and MC 3 , the data read from the memory cells MC 1 and MC 3 cause the electric potentials of the local bit lines LBL 1 and LBL 3 to differ from the intermediate potential VBLP. If this condition is maintained for an extended period of time there is a risk that the floating body effect will result in a loss of data from other memory cells connected to the local bit lines LBL 1 and LBL 3 , but in this mode of embodiment the local bit lines LBL 1 to LBL 4 are directly precharged to the intermediate potential VBLP using the precharging transistors PTR 1 to PTR 4 , before the precharge command is issued, and the loss of data as a result of the floating body effect can therefore be prevented.

It should be noted that it is not essential for the precharging transistors PTR 1 to PTR 4 to be turned on simultaneously, and the precharging transistors PTR 1 to PTR 4 may be controlled individually. For example, the precharging transistors PTR 1 and PTR 2 , and the precharging transistors PTR 3 and PTR 4 may be turned on or off with different timings.

Although not illustrated in the drawings, in the write operation in this mode of embodiment the write data should be written to the global sense amplifier GSA in the period between the time t 142 and the time t 173 .

FIG. 14 is an operational waveform diagram used to describe a modified example of the operation of the semiconductor device according to this mode of embodiment during a read operation.

The operation illustrated in FIG. 14 differs from the operation illustrated in FIG. 13 in that the operation to activate the connection signal TG 1 in the period between the time t 142 and the time t 173 and the operation to activate the selection signals SEL 3 and SEL 4 in the period between the time t 173 and the time t 174 , illustrated in FIG. 13 , are omitted. Other operations are the same as for the operations described with reference to FIG. 13 , and therefore duplicate descriptions are omitted.

In the operation illustrated in FIG. 14 , because the re-storing operation prior to the direct precharging of the local bit lines LBL 1 to LBL 4 has been omitted, the current consumption arising as a result of said operation can be reduced. It should be noted that with regard to the re-storing operation prior to the direct precharging of the local bit lines LBL 1 to LBL 4 , the re-storing operations to both memory cells MC 1 and MC 3 may be omitted, as illustrated in FIG. 14 , or the re-storing operation to only one of the memory cells may be omitted.

Preferred modes of embodiment of the present invention have been described hereinabove, but various modifications to the present invention may be made without deviating from the gist of the present invention, without limitation to the abovementioned modes of embodiment, and it goes without saying that these are also included within the scope of the present invention.

For example, in the first to third modes of embodiment described hereinabove, examples in which the present invention has been applied to a DRAM are described, but the scope of application of the present invention is not limited to this, and the present invention can also be applied to other types of memory-based devices, and can also be applied to logic-based devices which include a memory cell array region.

Further, in the first to third modes of embodiment described hereinabove, two pairs of local bit lines LBL are allocated to one hierarchical sense amplifier HSA, but the present invention is not limited to this configuration. Therefore one pair of local bit lines LBL may be allocated to one hierarchical sense amplifier HSA. Further, in the modes of embodiment described hereinabove, the local bit lines LBL forming a pair belong to mutually different submats, but the local bit lines LBL forming a pair may belong to the same submat as one another.

Further, there is no particular restriction to the specific circuit configuration of the hierarchical sense amplifier HSA in the present invention, and as illustrated in a generalized manner in FIG. 8 , any circuit configuration can be adopted. It should be noted that in FIG. 8 , elements having the same reference numbers as in the first mode of embodiment are the same as in the first mode of embodiment, and descriptions thereof are therefore omitted.

For example, a circuit can be employed as appropriate as the hierarchical sense amplifier HSA, provided that it is itself a sense amplifier capable of performing a re-storing operation, in other words a circuit of a type capable of amplifying a read signal on a selected local bit line LBL and feeding back the signal after amplification to said selected local bit line LBL.

Further, a description was given in which the hierarchical switches HSW 1 and HSW 2 are provided to the outside of the selection switches SELSW 1 and SELSW 2 , in other words on the side on which the local bit lines LBL 1 and LBL 2 exist, but the hierarchical switches HSW 1 and HSW 2 may be provided between the selection switches SELSW 1 and SELSW 2 and the hierarchical sense amplifier HSA. Further, in the first to third modes of embodiment described hereinabove, the hierarchical switches HSW 1 and HSW 2 are described as being used in common during reading and writing of data, but the hierarchical switches HSW 1 and HSW 2 may each be configured from a hierarchical switch for reading and a hierarchical switch for writing. In this case the configuration may be such that, as the hierarchical switches for reading and writing, an HSW 1 -Read and an HSW 1 -Write are provided on either side of the selection switch SELSW 1 , and an HSW 2 -Read and an HSW 2 -Write are provided on either side of the selection switch SELSW 2 .

10 Memory cell array region

11 Row-system control circuit

12 Column-system control circuit

13 Row address buffer

14 Column address buffer

15 Input/output control circuit

16 Data buffer

17 Command decoder

18 Control circuit

19 Mode register

C Cell capacitor

EQ 0 , EQ 1 Equalizing circuit

GBLT, GBLB Global bit line

GSA Global sense amplifier

HSA Hierarchical sense amplifier

HSW 1 to HSW 6 Hierarchical switch

LBL 1 to LBL 4 Local bit line

LIOT, LIOB Local I/O line pair

MC 1 to MC 4 Memory cell

N 1 to N 4 Signal node

PTR 1 to PTR 4 Precharging transistor

SELSW 1 to SELSW 4 Selection switch

SMAT 1 , SMAT 2 Submat

SN 1 , SN 3 Storage node

TR Cell transistor

WL 1 , WL 2 Word line

YSW Column switch