Passive equalizer

The present invention relates to a passive equalizer used as a waveform equalization circuit for recovering a waveform of a transmission signal degraded by a transmission loss, and particularly relates to a passive equalizer used for a transmission of an ultrafast serial signal exceeding 10 Gbit/s.

In the transmission of the ultrafast serial signal, a pulse width of a digital transmission signal is dynamically changed by data content. Therefore, such a transmission signal has a broad frequency component. Accordingly, when the transmission loss occurs, amplitude is easily attenuated when a pulse has a narrower pulse width, that is, when a pulse has a higher frequency component.

Particularly, 1 unit interval signal (UI signal) is a minimum pulse width signal generating a single pulse of “0” or “1” separately, and has a highest frequency and is strongly influenced by the transmission loss. Therefore, a phenomenon of a small amplitude is easily generated, compared with multiple UI signal such as 2UI signal generating two successive pulses of “0” and “1”, and 3UI signal generating three successive pulses of “0” and “1”, and so forth.

Thus, when only the 1UI signal has a small amplitude, the following case easily occurs: the 1UI signal cannot completely rise to a predetermined level when the 1UI signal is generated separately after the same level is continued.

Such a 1UI signal that cannot completely rise, is not recognized by a receiver IC in an electronic circuit, and a bit error of the transmission signal is likely to occur.

As a method of avoiding such a problem, it is effective to adjust the amplitude of the entire transmission signal to the amplitude of the 1UI signal, and recover the attenuation of the amplitude of the 1UI signal relatively.

For such a purpose, a technique of equalizing an amplitude so that the amplitude of a low frequency signal is close to the amplitude of the 1UI signal, by inserting so-called an “equalizer” in a transmission circuit, the equalizer having a propagation characteristic such that attenuation is more increased toward a lower frequency, as a means for adjusting the amplitude of a transmission signal.

As shown in the Research investigation report “No. 23 2008, p 603” (Non-patent document 1) by Telecommunications Advancement Foundation, a passive equalizer of a high-pass filter system is proposed, in which a resistance and an impedance element having a frequency characteristic are combined. An example of such an equalization circuit is shown in FIG. 17 .

Such a passive equalizer is a passive component, and is easily connected to an electronic circuit, and further can be easily constituted using commercially available discrete chip components, and therefore is supplied to the market as a product capable of responding to an ultrafast signal up to 12.5 Gbit/s.

Meanwhile, Japanese Patent Laid Open publication No. 2009-055284 (Patent document 1) teaches a passive equalizer configured to dispose differential lines so as to vertically face each other interposing a thin insulating layer. This is an application of the characteristic such that a transmission signal can easily pass through the coupling capacitance between upper and lower lines, when its frequency becomes higher.

Non-Patent Document

Non-patent document 1:

“Construction of an integrated circuit system utilizing a communication/signal processing technique for Multiple-Valued Code-Division Multiple Access Techniques for Intra-Chip Communication” by Telecommunications Advancement Foundation (Research investigation report No. 23 2008, p 603)

Patent Document

Patent document 1: Japanese Patent Laid Open Publication No. 2009-055284

Problem to be Solved by the Invention

However, when the circuit shown in the abovementioned non-patent document 1 is constituted of the commercially-available chip components and is configured to respond to a next-generation transmission speed of 25 G to 28 Gbit/s exceeding 10 Gbit/s, there is a problem that difference in properties occurs due to the stray inductance in the electrode of the chip components, and characteristics as designed cannot be obtained, or there is a problem that a capacitance value of the capacitor is likely to be critical.

Therefore, the capacitor of a desired capacitance value cannot always be available, and even if it can be available, the following problem is likely to occur: the characteristics are not stable under great influence of the tolerance at the time of mass production purchase. Therefore, the structure using the commercially-available chip components is not suitable for the purpose of a use for a transmission speed exceeding 10 Gbit/s.

Therefore, the passive equalizer having a monolithic structure such as a multilayer ceramic structure is desired.

However, the wavelength of a transmission signal is short in the use for the transmission speed of 25 G to 28 Gbit/s, and therefore if the structure of FIG. 17 is attempted to be realized by the multilayer ceramic structure so as to be a lumped constant circuit, another problem is likely to occur.

That is, the problem that a signal is reflected or attenuated by impedance mismatch, is likely to occur unless a capacitor electrode functions as a distributed constant line and the dimension and the shape of the electrode are suitable as a transmission line such as a coplanar line and a strip line.

Conversely, in a general multilayer ceramic structure which is not specific for a chip capacitor, when priority is put on a proper dimension of the transmission line, the following problem is likely to occur: a desired capacitance value cannot be obtained, thus making it difficult to design such a passive equalizer.

Meanwhile, the structure of patent document 1 has the following problem: although the configuration is simple and a correct impedance value and a capacitor capacitance are easily obtained, the transmission signal passes through a relatively broad band similarly to a general coupling capacitor due to the function of the upper and lower line patterns interposing the insulating layer as a capacitor electrode, thus making it difficult to obtain a desired frequency characteristic such that a transmission loss is selectively reduced in the frequency near the frequency of the 1UI signal.

In addition, this structure also has the following problem: direct current (DC) is cut-off, thus significantly attenuating the signal near the direct current, and in the transmission of the ultrafast serial signal, it is difficult to pass the transmission signal of a low frequency component in which the same logic level continues for a long time, and a bit error is generated in the transmission signal including many low frequency components.

In order to solve the abovementioned problem, the present invention is provided, and an object of the present invention is to provide the passive equalizer capable of responding to a transmission of a ultrafast serial signal, and particularly to a transmission signal of 25 G to 28 Gbit/s, and capable of obtaining excellent propagation characteristic even if a large dimensional error occurs in an internal electrode size.

Means for Solving the Problem

In order to solve the abovementioned problem, there is provided a passive equalizer according to claim 1 , including:

a first meander line formed on one surface of a dielectric layer, with one end as a signal input position and the other end connected to a first termination resistance;

a second meander line formed on a side facing the first meander line interposing the dielectric layer, along the first meander line so as to face the first meander line, with one end positioned at the other end side of the first meander line as a signal output position and the other end connected to a second termination resistance;

a first conductor line formed on a surface facing a formation surface of the second meander line with a space between them, with one end as the signal input position and the other end as the signal output position, and at least one portion divided in a middle; and

a first series resistance connected in series so as to connect a dividing section dividing the first conductor line.

There is provided the passive equalizer according to claim 2 of the present invention, wherein the first and second meander lines have a folding cycle in such a manner that a bending line is partially overlapped on a virtual median line crossing a middle part between the signal input position and the signal output position, and the first and second meander lines are formed into the same shape so as to have a line-symmetric relation each other, with a median line as a center.

There is provided the passive equalizer according to claim 3 of the present invention, wherein the first conductor line is a meander line.

There is provided the passive equalizer according to claim 4 of the present invention, including:

a second conductor line formed on a formation surface facing the formation surface of the first conductor line with a space between them, along the first conductor line so as to face the first conductor line, with one end as the signal input position and the other end as the signal output position, and at least one portion divided in a middle; and

a second series resistance connected in series so as to connect a dividing section dividing the second conductor line.

The passive equalizer according to claim 5 of the present invention, wherein the dividing section dividing the first and second conductor lines is formed at a position mutually away from the median line.

There is provided the passive equalizer according to claim 6 of the present invention, wherein the second conductor line is a meander line.

There is provided the passive equalizer according to claim of the present invention, wherein the first and second conductor lines are formed into the same shape so as to have a line-symmetric relation each other, with a median line as a center.

There is provided the passive equalizer according to claim 8 of the present invention, including:

a third meander line formed in a line-symmetric with respect to the first meander line on the formation surface of the first meander line in the dielectric layer, as a pair of differential transmission lines, with one end as an reverse phase signal input position showing a differential reverse polarity to the signal input position, and the other end connected to one end of a third termination resistance which is formed on the same formation surface as the formation surface of the first termination resistance;

a fourth meander line formed in a line-symmetric with respect to the second meander line on the formation surface of the second meander line, as a pair of differential transmission lines, with one end positioned at the other end side of the third meander line as the reverse phase signal output position, and the other end connected to one end of a fourth termination resistance which is formed on the same formation surface as the formation surface of the second termination resistance;

a third conductor line formed in a line-symmetric with respect to the first conductor line on the same formation surface as the formation surface of the first conductor line, as a pair of differential lines, with one end as the reverse phase signal input position and the other end as the reverse phase signal output position, and at least one portion divided in a middle; and

a third series resistance connected in series so as to connect the dividing section dividing the third conductor line.

There is provided the passive equalizer according to claim 9 of the present invention, wherein the first and second meander lines have a folding cycle in such a manner that a bending line is partially overlapped on a virtual median line crossing a middle part between the signal input position and the signal output position, and are formed into the same shape so as to have a line-symmetric relation each other, with a median line as a center.

There is provided the passive equalizer according to claim of the present invention, wherein the first and third conductor lines are meander lines.

There is provided the passive equalizer according to claim 11 of the present invention, including:

the second conductor line formed on a surface facing the first conductor line, along the first conductor line so as to face the first conductor line, with one end as the signal input position and the other end as the signal output position, and at least one portion divided in a middle;

a second series resistance connected in series so as to connect a dividing section dividing the second conductor line;

a fourth conductor line formed in a line-symmetric with respect to the second conductor line on the same formation surface as the formation surface of the second conductor line, as a pair of differential lines, with one end as the reverse phase signal input position and the other end as the reverse phase signal output position, and at least one portion divided in a middle; and

a fourth series resistance connected in series so as to connect the dividing section dividing the fourth conductor line.

There is provided the passive equalizer according to claim 12 of the present invention, wherein dividing sections dividing the first to fourth conductor lines are formed at positions away from each other from the median line.

There is provided the passive equalizer according to claim 13 of the present invention, wherein the second and fourth conductor lines are meander lines.

There is provided the passive equalizer according to claim 14 of the present invention, wherein the first and second conductor lines are formed into the same shape so as to have a line-symmetric relation each other, with a median line as a center.

According to the passive equalizer of claim 1 of the present invention, a signal of a high frequency passes between first and second facing meander lines with low loss and meanwhile a signal of a low frequency passes through the first conductor line and attenuated by the first series resistance, and such a passive equalizer is capable of easily functioning as an equalizer, responding to a transmission of an ultrafast serial signal, particularly responding to a transmission signal of 25 G to 28 Gbit/s, and capable of obtaining an excellent propagation characteristic even in a case that a great error occurs in the dimension of the internal electrode size.

According to the passive equalizer of claim 2 of the present invention, preferable characteristics can be easily obtained as the passive equalizer and a pattern can be shared so that a cost can be easily reduced.

According to the passive equalizer of claim 3 of the present invention, each kind of propagation characteristic can be easily adjusted.

According to the passive equalizer of claim 4 of the present invention, propagation characteristic of a signal of a low frequency can be easily adjusted.

According to the passive equalizer of claim 5 of the present invention, propagation characteristic of a signal of a high frequency can be easily adjusted.

According to the passive equalizer of claim 6 of the present invention, the second conductor line is constituted of a meander line, and therefore each kind of propagation characteristic can be easily adjusted.

According to the passive equalizer of claim 7 of the present invention, each kind of propagation characteristic can be easily adjusted, and therefore a circuit pattern can be shared so that the cost can be reduced.

The passive equalizer of claim 8 of the present invention functions as an equalizer for a differential signal.

The passive equalizer of claim 9 of the present invention is capable of easily obtaining a further preferable characteristic as an equalizer for the differential signal, and the circuit pattern can be shared so that the cost can be reduced.

According to the passive equalizer of claim 10 of the present invention, the first and third conductor lines are constituted as meander lines, and therefore each kind of propagation characteristic of the differential signal can be easily adjusted.

According to the passive equalizer of claim 11 of the present invention, propagation characteristic of the differential signal of a low frequency can be easily adjusted.

According to the passive equalizer of claim 12 of the present invention, propagation characteristic of the differential signal of a high frequency can be easily adjusted.

According to the passive equalizer of claim 13 of the present invention, the second and fourth conductor lines are constituted as meander lines, and therefore each kind of propagation characteristic of the differential signal can be easily adjusted.

According to the passive equalizer of claim 14 of the present invention, each kind of propagation characteristic of the differential signal can be easily adjusted, and a circuit pattern can be shared so that the cost can be reduced.

FIG. 1 is an exploded perspective view showing a passive equalizer according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit of the passive equalizer of FIG. 1 .

FIG. 3 is a frequency characteristic of the passive equalizer of FIG. 1 .

FIG. 4 is a pulse waveform chart under influence of a transmission loss inputted in the passive equalizer of FIG. 1 .

FIG. 5 is a pulse waveform chart of the passive equalizer of FIG. 1 .

FIG. 6 is a frequency characteristic of the equivalent circuit of FIG. 5 .

FIG. 7 is an exploded perspective view showing the passive equalizer according to another embodiment of the present invention.

FIG. 8 is a frequency characteristic of the passive equalizer of FIG. 7 .

FIG. 9 is an exploded perspective view showing a passive equalizer according to another embodiment of the present invention.

FIG. 10 is an equivalent circuit of the passive equalizer of FIG. 9 .

FIG. 11 is a frequency characteristic of the passive equalizer of FIG. 9 .

FIG. 12 is an exploded perspective view showing a passive equalizer according to another embodiment of the present invention.

FIG. 13 is a frequency characteristic of the passive equalizer of FIG. 12 .

FIG. 14 is an exploded perspective view showing a passive equalizer according to another embodiment of the present invention.

FIG. 15 is an equivalent circuit of the passive equalizer of FIG. 14 .

FIG. 16 is a frequency characteristic of the passive equalizer of FIG. 14 .

FIG. 17 is an equivalent circuit of a conventional passive equalizer.

Embodiments of the present invention will be described hereafter, with reference to the drawings.

FIG. 1 is an exploded perspective view showing the structure of a passive equalizer E of the present invention, in the form of a differential transmission line for example.

In FIG. 1 , each pair of meander lines (first and third meander lines) 1 A and 1 B, termination resistances (first and third termination resistances) 5 A and 5 B, and resistance connection pads 17 A, 17 B, 19 A, and 19 B are formed on one surface (upper surface in FIG. 1 ) of a rectangular plate-like dielectric layer (first dielectric layer) 9 A.

A pair of meander lines 1 A and 1 B are formed in a shape folded multiple times into a rectangular shape, between short sides that face each other in a longitudinal direction of the dielectric layer 9 A, and the meander lines 1 A and 1 B are formed, with a virtual line x-x′ as a center, which is the line passing through an intermediate position between the short sides so as to equally divide the dielectric layer 9 A into two parts.

One end of the meander line 1 A is connected to an input terminal 11 A described later to form a signal input position, and one end of the meander line 1 B is connected to an input terminal 11 B described later to form a signal input position.

The other end of the meander line 1 A is connected to a resistance connection pad 17 A formed near the longitudinal short side of the dielectric layer 9 A, and the other end of the meander line 1 B is connected to a resistance connection pad 17 B formed near the same short side.

One end of a strip-shaped termination resistance 5 A is connected to the resistance connection pad 17 A, and the other end of the termination resistance 5 A is connected to a resistance connection pad 19 A which is formed on a long side intermediate position along the longitudinal direction of the dielectric layer 9 A.

One end of a strip-shaped termination resistance 5 B which is similar to the termination resistance 5 A is connected to the resistance connection pad 17 B, and the other end of the termination resistance 5 B is connected to a resistance connection pad 19 B which is formed on the long side intermediate position along the longitudinal direction of the dielectric layer 9 A.

The resistance connection pad 19 A is connected to a ground terminal 15 A described later, and the resistance connection pad 19 B is connected to a ground terminal 15 B described later.

The termination resistances 5 A and 5 B are formed respectively by a print resistive film for example, so as to be folded-back from the other end of the meander lines 1 A and 1 B, along near the long side of the dielectric layer 9 A. A resistance value is not stable if an area overlapping on the conductors such as meander lines 1 A and 1 B is small. Therefore, each of the termination resistances 5 A and 5 B is preferably connected via such connection pads 17 A, 17 B, 19 A, and 19 B.

The meander lines 1 A and 1 B, termination resistances 5 A and 5 B, input terminals 11 A and 11 B, ground terminals 15 A and 15 B, resistance connection pads 17 A and 17 B, and resistance connection pads 19 A and 19 B are formed so as to be arranged symmetrically, with the virtual line x-x′ as a center, thereby forming a pair of the differential transmission lines.

A dielectric layer (third dielectric layer) 9 B made of the same material and having the same shape as the dielectric layer 9 A, is disposed so as to be laminated on a facing surface (lower surface in the figure) of the dielectric layer 9 A.

Each pair of meander lines (second and fourth meander lines) 1 C and 1 D, termination resistances (second and fourth termination resistances) 5 C and 5 D, and resistance connection pads 17 C, 17 D, 19 C, and 19 D are formed on one surface (upper surface in FIG. 1 ) of the dielectric layer 9 B.

A pair of meander lines 1 C and 1 D are formed in a shape folded multiple times into a rectangular shape, between short sides that face each other in a longitudinal direction of the dielectric layer 9 B, wherein the meander line 1 C and the meander line 1 A are faced each other and the meander line 1 D and the meander line 1 B are faced each other in nearly isometric, interposing the dielectric layer 9 A.

One end of the meander line 1 C is connected to an output terminal 13 A described later positioned at the other end side of the first meander line 1 A to form a signal output position. Similarly, one end of the meander line 1 D is connected to an output terminal 13 B described later.

The other end of the meander line 1 C is connected to a resistance connection pad 17 C, and the other end of the meander line 1 D is connected to a resistance connection pad 17 D.

One end of a strip-shaped termination resistance 5 C is connected to the resistance connection pad 17 C, and one end of a strip-shaped termination resistance 5 D is connected to the resistance connection pad 17 D.

The other end of the termination resistance 5 C is connected to a resistance connection pad 19 C which is formed on one long side intermediate position along the longitudinal direction of the dielectric layer 9 B. The other end of the termination resistance 5 D is connected to a resistance connection pad 19 D which is formed on the other long side intermediate position of the dielectric layer 9 B.

The termination resistances 5 C and 5 D are respectively formed along near the long side of the dielectric layer 9 B from the ends of the meander lines 1 C and 1 D. Resistance connection pads 19 C and 19 D are connected to the ground terminals 15 A and 15 B.

The meander lines 1 C and 1 D, termination resistances 5 C and 5 D, resistance connection pads 17 C and 17 D, and resistance connection pads 19 C and 19 D are also formed so as to be arranged in a line-symmetric pattern, with a virtual line x-x′ as a center, thus constituting a pair of the differential transmission line.

There is no necessity for making a coincidence between a folding cycle (fold-back pitch) of the meander lines 1 A and 1 B, and the folding cycle (fold-back pitch) of the meander lines 1 C and 1 D. Further, there is no necessity for making a uniform folding cycle (fold-back pitch) in the individual meander line.

A dielectric layer (second dielectric layer) 9 C made of the same material and having the same shape as the dielectric layer 9 B is disposed so as to be laminated under the dielectric layer 9 B.

Each pair of conductor lines (first and third conductor lines) 3 A and 3 B, series resistances (first and third series resistances) 7 A and 7 B, are formed on one surface (upper surface in FIG. 1 ) of the dielectric layer 9 C.

Conductor lines 3 A and 3 B are formed in the longitudinal direction of the dielectric layer 9 C so as to face the meander lines 1 C and 1 D interposing the dielectric layer 9 B. One end of the conductor line 3 A is connected to the input terminal 11 A, and the other end thereof is connected to the output terminal 13 A. Also, one end of the conductor line 3 B is connected to the input terminal 11 B, and the other end thereof is connected to the output terminal 13 B.

Conductor lines 3 A and 3 B are divided so as to be separated at an arbitrary position in the middle, and a series resistance 7 A is connected in series so as to connect the divided conductor lines 3 A, and a series resistance 7 B is connected in series so as to connect the divided conductor lines 3 B.

Thus, a low frequency signal including a direct current, transmits through this route via the series resistances 7 A and 7 B, thereby attenuating a DC signal.

A dielectric layer (fourth dielectric layer) 9 D made of the same material and having the same shape as the dielectric layer 9 A, is disposed above the dielectric layer 9 A so as to be laminated thereon.

The dielectric layer 9 D has a thickness thicker than other dielectric layers 9 A and 9 B as a cover layer, and input terminals 11 A and 11 B, and output terminals 13 A and 13 B are formed on corresponding both long sides along the longitudinal direction.

Ground terminals 15 A and 15 B are formed on both long sides, between input terminals 11 A, 11 B, and output terminals 13 A and 13 B.

FIG. 1 shows each constituent element in an exploded and perspective state, wherein one ends of the abovementioned meander lines 1 A and 1 B are connected to the input terminals 11 A and 11 B, and one ends of the abovementioned meander lines 1 C and 1 D are connected to the output terminal 13 A and 13 B, and the other ends of the termination resistances 5 A, 5 B, 5 C, and 5 D are connected to the ground terminals 15 A and 15 B.

When a passive equalizer E of the present invention is mounted on electronic equipment, the ground terminals 15 A and 15 B may usually be grounded to a power ground of a circuit. However, a signal line is sometimes connected to an external voltage line via a pull-up resistance so that amplitude center potential of the signal is fixed to a threshold value of IC, depending on a circuit configuration.

In order to achieve the abovementioned object, the ground terminals 15 A and 15 B may be connected to the external voltage line. Thus, the pull-up resistance can be omitted.

The dielectric layer 9 A is formed to be thinnest so that it is thinner than other dielectric layers 9 B, 9 C, and 9 D, thereby increasing an electromagnetic coupling between meander lines 1 A and 1 C, and between meander lines 1 B and 1 D.

The abovementioned dielectric layer 9 C also has a role of the cover layer, and therefore it is thicker than the dielectric layers 9 A and 9 B which are intermediate layers.

The abovementioned equalizer E having a pair of the differential transmission lines, is manufactured by a lamination ceramic process as described below for example.

That is, each conductor pattern is formed on each surface (upper surface in FIG. 1 ) of the dielectric layers 9 A to 9 C in a green sheet state by printing such as silver paste or silver-palladium paste, and each resistance is formed by printing such as resistance paste, and thereafter the dielectric layers 9 A to 9 C are superimposed on each other and the dielectric layer 9 D is superimposed on the dielectric layer 9 A so as to be integrally formed by laminating press, which are then cut into an individual size and co-fired.

Thereafter, input electrodes 11 A and 11 B, output electrodes 13 A and 13 B, and ground electrodes 15 A and 15 B are formed, connected, and completed as a chip component by coating a product side face, a lower surface pad position, and an upper surface pad position, with silver paste or silver-palladium paste, which are then calcined again.

FIG. 2 is an equivalent circuit of the structure of FIG. 1 . In the structure of the present invention, an LC series resonant circuit is constituted between upper and lower facing meander lines 1 A and 1 C, and between upper and lower facing meander lines 1 B and 1 D, and only resistance is appeared to be connected from the low frequency signal including a direct current (DC), so that a π-type attenuator is constituted by such a resonant circuit.

The abovementioned LC series resonant circuits are respectively connected in parallel to the series resistances 7 A and 7 B, and impedance at resonance frequency is minimized. Therefore, such a resonance frequency signal passes through the LC series resonant circuit with a low loss, by bypassing the series resistances 7 A and 7 B. That is, by setting the frequency of the 1UI signal so as to be the resonance frequency, only the signal of this frequency can be transmitted with a low loss, and a signal of other frequency is attenuated via the series resistances 7 A and 7 B.

Based on the abovementioned consideration on the equivalent circuit, the equalizer E is configured so that when a ultrafast digital differential signal is applied to the input electrodes 11 A and 11 B and outputted from the output electrodes 13 A and 13 B as a transmission signal, the signal of a high frequency passes through the facing meander lines 1 A and 1 C, and the facing meander lines 1 B and 1 D, by electromagnetic coupling between them.

Meanwhile, a signal of a low frequency passes through conductor lines 3 A and 3 B, which is then attenuated by the series resistances 7 A and 7 B inserted into the conductor lines 3 A and 3 B, thus obtaining a function as an equalizer. In addition, ground destinations of the termination resistances 5 A, 5 B, 5 C, and 5 D can be connected to a desired position such as a ground or a power supply line.

In the equalizer E with such a structure, the following structure is considered: the ultrafast digital differential signal is applied to the input electrodes 11 A and 11 B and outputted from the output electrodes 13 A and 13 B as a transmission signal. FIG. 3 shows the frequency characteristic obtained by electromagnetic field simulation.

In FIG. 3 , Sdd 11 -( 1 ) indicates a reflection characteristic of the differential signal, Sdd 21 -( 1 ) indicates a transmission characteristic of the differential signal, and GD 21 -( 1 ) indicates a group delay characteristic of a differential transmission signal. According to FIG. 3 , although a slight irregularity is observed in the group delay characteristic, the propagation characteristic shows a minimal loss at around 14 GHz.

Meanwhile, about 6 dB loss is observed near the direct current (DC), and minimal characteristic of the equalizer is obtained, for functioning as an equalizer for the transmission speed of 25 G to 28 Gbit/s. Reflection characteristic Sdd 11 -( 1 ) is also suppressed to −15 dB or less up to 17 GHz, and excellent impedance matching is obtained.

Therefore, whether or not waveform amplitude can be equalized, is confirmed by circuit simulation using the equalizer having the abovementioned characteristic.

FIG. 4 shows a positive-phase pulse waveform V (+) of 25 Gbit/s differential signal, a negative-phase pulse waveform V(−), and differential eye pattern V (Eye) in which the amplitude of only the 1UI signal is attenuated due to transmission loss. Thus, not only difference of amplitude, but also jitter is generated due to spread rising/falling edge.

FIG. 5 shows an output waveform observed when such a waveform signal is transmitted the equalizer having the characteristic of FIG. 3 , wherein although overall amplitude is attenuated, the jitter of the rising/falling edge is removed with disappearance of the difference of amplitude.

Thus, the passive equalizer E shown in FIG. 1 shows that it sufficiently functions as an equalizer by having the characteristic of FIG. 3 , even if there is a slight irregularity observed in the group delay characteristic.

Such a frequency characteristic of the circuit is obtained by circuit simulation applied to the equivalent circuit of FIG. 2 , as shown in FIG. 6 .

In FIG. 6 , each label shows the same meaning as the case of FIG. 3 , and shows a similar characteristic as FIG. 3 . Group delay characteristic GD 21 -( 2 ) is indicated by a smaller value than that of FIG. 3 . This is because the group delay characteristic is a precise value without a propagation delay time caused by terminal or a substrate land, etc.

In addition, when the characteristic of FIG. 6 is derived, the LC series resonance circuit section in the abovementioned equivalent circuit of FIG. 2 , is configured so that upper and lower inductor values are equal, and all capacitor values are set to be uniform, with a tap taken out from the center.

Thus, in the equivalent circuit of FIG. 2 , the LC series resonance circuit section has a balanced structure. Therefore, it can be considered that the following characteristic can be obtained: the resonance frequency is hardly dispersed, and there is no irregularity in the transmission characteristic Sdd 21 -( 2 ) and the group delay characteristic GD 21 -( 2 ).

Therefore, in an actual structure, it is expected that more excellent characteristic than the structure of FIG. 1 can be obtained by forming the upper and lower facing meander lines in the balanced structure.

FIG. 7 is an exploded perspective view showing another structure of the passive equalizer E according to the present invention, wherein upper and lower facing meander lines are balanced.

In FIG. 7 , meander lines 1 C and 1 A, and meander lines 1 D and 1 B have a line-symmetric pattern (mirror image), with median line y-y′ as a center, wherein the median line y-y′ is formed crossing the meander lines 1 A and 1 B in the intermediate position between input terminals (signal input positions) 11 A, 11 B, and output terminals (signal output positions) 13 A, 13 B.

Further, the folding-back cycle of the meander lines 1 A and 1 C is set to be uniform excluding a connection lead-out line of the end portion, so that the line at a folding-corner part is overlapped on the median line y-y′ in both meander lines 1 A and 1 C. That is, in both meander lines 1 A and 1 C, the folding cycle is overlapped not in the same phase, but in opposed phases.

With such a structure, a pair of the differential lines are formed and therefore meander lines 1 A and 1 B, and meander lines 1 C and 1 D are symmetric, and meander lines 1 C and 1 A, and meander lines 1 D and 1 B have a line-symmetric relation each other with median line y-y′ as a center, and folding-back cycle is established, which is overlapped in the opposed phases. The other structure is similar to FIG. 1 .

In addition, in the case of the line-symmetric patterns, one print mask for forming conductors such as meander lines, etc., can be shared by rotation of 180 degrees during pattern printing, so that a mask cost can be saved.

FIG. 8 shows the frequency characteristic of the equalizer E shown in FIG. 7 . Each label shows the same meaning as the case of FIG. 3 .

In FIG. 8 , Sdd 11 -( 7 ) indicates the reflection characteristic of the differential signal, Sdd 21 -( 7 ) indicates the transmission characteristic of the differential signal, and GD 21 -( 7 ) indicates the group delay characteristic of the differential transmission signal.

FIG. 8 shows that the irregularity of the characteristic is reduced, compared with FIG. 3 . Accordingly, although not shown, an eye pattern improvement effect equal to or greater than the effect of FIG. 5 can be realized.

Although the shapes of the meander lines 1 A to 1 D are significantly different between FIG. 7 and FIG. 1 , a similar characteristic can be obtained in both of them. Therefore, it can be said that there is a large tolerance in the shapes of the meander lines 1 A to 1 D for obtaining a desired characteristic.

Therefore, according to the passive equalizer E of the present invention, the characteristic is more easily stabilized than a case that the circuit of FIG. 17 is constituted by a discrete chip component.

FIG. 9 is an exploded perspective view showing another structure of the passive equalizer E of the present invention, wherein the conductor line for passing a low frequency signal, is formed in a two-layer structure.

In FIG. 9 , a new dielectric layer (fifth dielectric layer) 9 E is further inserted between the dielectric layers 9 B and 9 C, from the structure of FIG. 7 .

Conductor lines (second and fourth conductor lines) 3 C and 3 D and series resistances (second and fourth series resistances) 7 C and 7 D are formed on one surface (upper surface in FIG. 9 ) of the dielectric layer 9 E so as to have a relation equivalent to the line-symmetric relation of the conductor lines 3 A and 3 B and series resistances 7 A and 7 B on the dielectric layer 9 C, with median line y-y′ as a center.

In addition, series resistances 7 A and 7 B are connected to the conductor lines 3 A and 3 B at a position closer to the input terminals 11 A and 11 B from the median line y-y′, and series resistances 7 C and 7 D are connected to the conductor lines 3 C and 3 D at a position closer to the output terminals 13 A and 13 B from the median line y-y′.

As a result, a section where conductor lines 3 A and 3 C are faced each other between the series resistances 7 A and 7 C, and a section where conductor lines 3 B and 3 D are faced each other between the series resistances 7 B and 7 D, constitute a parallel-plate capacitor, and a high frequency signal can bypass the series resistances 7 A to 7 D by passing through the parallel-plate capacitor.

Thus, paths of the meander lines 1 A to 1 D and the path of the parallel-plate capacitor are used together as the path of the high frequency signal, thus making it possible to further reduce the loss of the high frequency signal. The other structure is the same as the structure of FIG. 7 .

Here, although the conductor lines 3 A and 3 B, and the series resistances 7 A and 7 B are not necessarily required to be symmetric, the conductor lines 3 C and 3 D, and the series resistances 7 C and 7 D can share a printing mask pattern if they have the line-symmetric relation each other, thus making it possible to reduce the cost required for the printing mask.

Further, the series resistances 7 A and 7 B, and the series resistances 7 C and 7 D are not necessarily required to be in a positional relation of separating from each other. However, for example when they are overlapped on each other at the same position on the median line y-y′, it is difficult for the conductor lines 3 A to 3 B to form a bypassing path for a high frequency wave, and therefore reduction of the loss of the high frequency signal cannot be expected.

Therefore, dividing sections dividing the conductor lines 3 A to 3 D are preferably formed at a position mutually away from the median line y-y′.

Nevertheless, a total value of the series resistances is adjusted by changing a dimension of a resistance film or changing a resistivity of a resistance paste between the series resistances 7 A and 7 B, and between the series resistances 7 C and 7 D for example, and attenuation of a low frequency signal including a direct current (DC) can be controlled with high precision.

FIG. 10 shows an equivalent circuit having the structure of FIG. 9 , and shows a structure in which capacitors formed between the facing conductor lines 3 A and 3 C, and between the facing conductor lines 3 B and 3 D, are connected in parallel to the series resistances 7 A to 7 D on the equivalent circuit, and shows that the high frequency signal can bypass the series resistances 7 A to 7 D.

FIG. 11 is a frequency characteristic of the equalizer E shown in FIG. 9 , wherein only the differential transmission characteristic Sdd 21 is shown for comparison with the characteristic of FIG. 8 .

In the differential transmission characteristic Sdd 21 -( 9 ) of the structure of FIG. 9 , a high frequency loss is slightly reduced, compared with the differential transmission characteristic Sdd 21 -( 7 ) of the structure of FIG. 7 .

FIG. 12 is an exploded perspective view showing another structure of the passive equalizer E according to the present invention, wherein a conductor line for passing a low frequency signal is also formed in a meander state.

In FIG. 12 , conductor lines 3 A to 3 D are set in a meander state, and the conductor lines 3 A and 3 B, and the conductor lines 3 C and 3 D have a line-symmetric relation each other with median line y-y′ as a center. However, they are faced each other at the folding-back cycle in the same phase, unlike the meander lines 1 A to 1 D. The other structure is the same as the structure of FIG. 9 .

FIG. 13 shows a frequency characteristic of the equalizer E shown in FIG. 12 . In FIG. 13 , Sdd 11 -( 12 ) shows a differential reflection characteristic in the structure of FIG. 12 , Sdd 21 -( 12 ) shows the differential transmission characteristic in the structure of FIG. 12 , and GD 21 -( 12 ) shows a differential group delay characteristic in the structure of FIG. 12 .

Further, although not shown in FIG. 11 , differential reflection characteristic Sdd 11 -( 9 ) and differential group delay characteristic GD 21 -( 9 ) in the structure of FIG. 9 are also shown for comparison.

In the structure of FIG. 12 , it is found that differential reflection characteristic Sdd 11 -( 12 ) is improved and the irregularity is more reduced than the differential group delay characteristic GD 21 -( 12 ).

In addition, although not shown, similar characteristic can be obtained even in a case that conductor lines 3 A and 3 B and conductor lines 3 C and 3 D are faced each other at a folding cycle in the opposed phase.

The passive equalizer E has been described above, which has a structure in which a line-symmetric circuit is independently disposed, with a virtual line (x-x′ in FIG. 1 ) as a center for dividing the differential line into two parts, while constituting a pair of the differential lines, to thereby form the differential transmission line.

This structure is the structure that can be used even in a single-ended use of removing or non-using either one of the two parts divided by the virtual line x-x′ which divides the differential line. And a ground terminal is required instead of this advantage convenience.

On the other hand, a conventional passive equalizer shown in FIG. 17 does not have ground terminals. And originally, a differential signal transmission can be transmitted without common grounds. Therefore, a component requiring a connection of the ground terminals cannot be mounted on a circuit portion having no common grounds, and this is not preferable.

Therefore, the passive equalizer E without ground terminals capable of avoiding such a problem, is shown for example.

FIG. 14 is an exploded perspective view showing another structure of the passive equalizer E of the present invention, which has a structure for a differential signal only, without ground terminals.

In FIG. 14 , ground terminals 15 A and 15 B, and resistance connection pads 19 A to 19 D are removed from the structure of FIG. 12 .

Thus, since the ground destination of the termination resistances 5 A to 5 D are eliminated, the termination resistances 5 A and 5 B are sequentially connected between the resistance connection pads 17 A and 17 B, and the termination resistances 5 C and 5 D are also sequentially connected between the resistance connection pads 17 C and 17 D, so as to be terminated between differential lines. The other structure is the same as the structure of FIG. 1 .

FIG. 15 is an equivalent circuit of FIG. 14 . The structure of FIG. 17 is the structure of a differential T-type attenuator in a direct current (DC) manner, and meanwhile the structure of FIG. 14 is the structure of a differential π-type attenuator in a direct current (DC) manner by connecting the termination resistance between a pair of the differential lines as shown in FIG. 15 .

FIG. 16 is a frequency characteristic of the equalizer E shown in FIG. 14 . FIG. 16 shows that all of the differential reflection characteristic Sdd 11 -( 14 ), the differential transmission characteristic SDD 21 -( 14 ), and the differential group delay characteristic GD 21 -( 14 ) have the characteristic equal to or higher than the characteristic of other structure.

As described above, explanation is given for the example of the present invention, such that the passive equalizer E is fabricated in a ceramic lamination process. However, the passive equalizer E is not necessarily required to be made of a ceramic material, if it is made of a dielectric substrate, and can be made of an insulating resin substrate such as a printed circuit board, etc.

Further, in the passive equalizer E of the present invention, the section dividing the conductor lines 3 A to 3 D is not limited to one, and one or more, namely at least one section may be formed, and the series resistances 7 A to 7 D may be inserted into each dividing section in series.

In the abovementioned embodiment of the present invention, connection pads 17 A to 17 D, and 19 A to 19 D are provided at connection parts of any one or all of the termination resistances 5 A to 5 D and series resistances 7 A to 7 D. Therefore these resistances can be stably connected.

Further, the structure of the passive equalizer E of the present invention is not limited to the structure as described above in which termination resistances 5 A and 5 B are formed on the same formation surfaces as the first and third meander lines 1 A and 1 B, termination resistances 5 C and 5 D are formed on the same formation surfaces as the second and fourth meander lines 1 C and 1 D, series resistances 7 A and 7 B are formed on the same formation surfaces as the first and third conductor lines 3 A and 3 B, and series resistances 7 C and 7 D are formed on the same formation surfaces as the second and fourth conductor lines.

It is also acceptable that termination resistances 5 A to 5 D, and series resistances 7 A to 7 D are formed on the formation surface of a dielectric layer, etc., different from the first to fourth meander lines 1 A to 1 D or conductor lines 3 A to 3 D, and they are connected to each other by via.

Thus, by constituting the termination resistances 5 A to 5 D and series resistances 7 A to 7 D by chip resistor and mounting them on a substrate surface by via, exchange to a resistor having an optimal resistance value is enabled while measuring the characteristic as needed.

Incidentally, the passive equalizer E of the present invention can be executed in a single ended transmission line.

Such a single ended transmission structure is considered from a basic structure of the passive equalizer E of the present invention, and it can be considered that the passive equalizer E forming the differential transmission line is configured so that two single ended transmission lines are disposed therein.

That is, the passive equalizer E has the structure including:

the dielectric layer (first dielectric layer) 9 A;

the meander line (first meander line) 1 A formed on the dielectric layer (first dielectric layer) 9 A, with one end as a signal input position and the other end connected to the termination resistance (first termination resistance) 5 A;

the meander line (second meander line) 1 C formed on the surface facing the meander line 1 A interposing the dielectric layer 9 A, along the meander line 1 A, and so as to face the meander line 1 A, with one end as a signal output position positioned on the other end side of the meander line 1 A, and the other end connected to the termination resistance (second termination resistance) 5 C formed on the surface facing the meander line 1 A interposing the dielectric layer 9 A;

the conductor line (first conductor line) 3 A formed on the formation surface facing the formation surface of the second meander line 1 C with a space between them, with one end as a signal input position and the other end as a signal output position, and at least one place divided in the middle; and

the series resistance (first series resistance) 7 A connected in series so as to connect the dividing section dividing the conductor line 3 A. The abovementioned dielectric layer 9 B is not necessarily required.

Such a single end transmission line can be executed by the structure similar to the abovementioned structures of FIG. 1 , FIG. 7 , FIG. 9 , and FIG. 12 , and the effect similar to the effect obtained from these structures, can be obtained.

Further, input/output terminals and a chip-shaped single component with ground terminals are used for the explanation in the abovementioned examples of the present invention.

However, not only the structure using the single component only, but also the following structure is acceptable: only the internal structure part of the passive equalizer E from which input/output terminals and ground terminals are removed is assembled into a circuit substrate, or even in a case of the chip-shaped component, the internal structure part of the equalizer E is integrated in a circuit having other function such as a delay line or a common mode filter for example, to obtain one chip component.

Further, the passive equalizer E may be fabricated through not only the ceramic lamination process but also a thin film process, and in this case, the internal structure part can be integrated in a semiconductor.

1 A Meander line (first meander line)

1 B Meander line (third meander line)

1 C Meander line (second meander line)

1 D Meander line (fourth meander line)

3 A Conductor line (first conductor line)

3 B Conductor line (third conductor line)

3 C Conductor line (second conductor line)

3 D Conductor line (fourth conductor line)

5 A Termination resistance (first termination resistance)

5 B Termination resistance (third termination resistance)

5 C Termination resistance (second termination resistance)

5 D Termination resistance (fourth termination resistance)

7 A Series resistance (first series resistance)

7 B Series resistance (third series resistance)

7 C Series resistance (second series resistance)

7 D Series resistance (fourth series resistance)

9 A Dielectric layer (first dielectric layer)

9 B Dielectric layer (third dielectric layer)

9 C Dielectric layer (second dielectric layer)

9 D Dielectric layer (fourth dielectric layer)

9 E Dielectric layer (fifth dielectric layer)

11 A, 11 B Input terminal

13 A, 13 B Output terminal

15 A, 15 B Ground terminal

17 A, 17 B, 17 C, 17 D, 19 A, 19 B, 19 C, 19 D Resistance connection pad

E Passive equalizer