Gate driver circuit, gate driving method, gate-on-array circuit, display device, and electronic product

This application is the U.S. national phase of PCT Application No. PCT/CN2014/076258 filed on Apr. 25, 2014, which claims a priority of the Chinese patent application No. 201310745360.X filed on Dec. 30, 2013, which is incorporated herein by reference in its entirety.

The present disclosure relates to the field of display technology, in particular to a gate driver circuit, a gate driving method, a gate-on-array circuit, a display device and an electronic product.

Currently, in the prior art, there is no GOA (gate-on-array, which means that a gate driver circuit is directly formed on an array substrate) circuit capable of providing Vth (threshold voltage) compensation for a pixel of an OLED (organic light-emitting diode) display panel, and only a pixel design with a Vth compensation function or a single-pulse GOA circuit is applied.

Usually, an OLED pixel design of a current-controlled mode is adopted, so the display evenness of the OLED display panel will be reduced due to the uneven Vth of the entire OLED display panel and a Vth shift generated after the long-term operation. In order to enhance an integration level of the OLED display panel and reduce the production cost, the use of an integrated gate driver technology is a trend of development in future. However, a peripheral driver circuit is desired for the OLED Vth compensation pixel design, and as a result, more requirements are put forward on the GOA circuit.

A main object of the present disclosure is to provide a gate driver circuit, a gate driving method, a GOA circuit, a display device, and an electronic device, so as to compensate for a threshold voltage of a pixel and drive the pixel simultaneously, thereby to improve an integration level.

In one aspect, the present disclosure provides a gate driver circuit connected to a row of pixel units, each pixel unit includes a pixel driving module and a light-emitting device connected to each other, the pixel driving module including a driving transistor, a driving module and a compensating module, the compensating module being connected to a gate scanning signal, and the driving module being connected to a driving control signal and a driving voltage, the gate driver circuit comprising: a row pixel controlling unit configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor; and a driving control unit configured to provide the driving control signal to the driving module so as to control the driving module to drive the light-emitting device.

During the implementation, the row pixel controlling unit includes a start signal input end, a first control clock input end, a second control clock input end, a reset signal input end, an input clock end, a carry signal output end, a cut-off control signal output end, an output level end, an output level pull-down control end, a gate scanning signal output end.

The row pixel controlling unit further includes:

a first pull-up node potential pull-up module configured to pull up a potential of a first pull-up node to a high level when a first control clock signal and a first start signal are at a high level; a first storage capacitor connected between the first pull-up node and the carry signal output end; a first pull-up node potential pull-down module configured to pull down the potential of the first pull-up mode to a first low level when a potential of a first pull-down node or a second pull-down node is a high level; a first control clock switch configured to enable the first control clock input end to be electrically connected to the first pull-down node when the first control clock signal is at a high level; a second control clock switch configured to enable the second control clock input end to be electrically connected to the second pull-down node when a second control clock signal is at a high level; a first pull-down node potential pull-down module configured to pull down the potential of the first pull-down node to the first low level when the potential of the first pull-up node or the second pull-down node is a high level; a second pull-down node potential pull-down module connected to the reset signal input end and configured to pull down the potential of the second pull-down node to the first low level when the potential of the first pull-up node or the first pull-down node is a high level; a first carry control module configured to enable the carry signal output end to be electrically connected to the second clock signal input end when the potential of the first pull-up node is a high level; a first carry signal pull-down module configured to pull down a potential of a carry signal to the first low level when the potential of the first pull-down node or the second pull-down node is a high level; a first cut-off control module configured to enable the second clock signal input end to be electrically connected to the cut-off control signal output end when the potential of the first pull-up node is a high level, and enable the cut-off control signal output end to be electrically connected to a second low level output end when the potential of the first pull-down node or the second pull-down node is a high level; a first feedback module configured to transmit a cut-off control signal to the first pull-up node potential pull-up module and the first pull-up node potential pull-down module when the carry signal is at a high level; a gate scanning signal control module configured to enable the second control clock input end to be electrically connected to the gate scanning signal output end when the potential of the first pull-up node is a high level; an input clock switch configured to enable the input clock end to be electrically connected to the output level pull-down control end when the potential of the first pull-up node is a high level; a gate scanning signal pull-down module configured to pull down a potential of the gate scanning signal to a second low level when the potential of the first pull-down node or the second pull-down node is a high level; an output level pull-down control module configured to pull down a potential of the output level pull-down control end to the second low level when the potential of the first pull-down node or the second pull-down node is a high level; an output level pull-up module configured to pull up an output level to a high level when the output level pull-down control end outputs the second low level; and an output level pull-down module configured to pull down the output level to the second low level when the output level pull-down control end outputs a high level.

During the implementation, the driving control unit includes: a second start signal input end, a third control clock input end, a fourth control clock input end, a driving control signal output end, and a driving control signal pull-down control end. The reset signal input end, the carry signal output end and the cut-off control signal output end are connected to the driving control unit.

The driving control unit further includes:

a second pull-up node potential pull-up module configured to pull up a potential of a second pull-up node to a high level when a third control clock signal and a second start signal are at a high level; a second storage capacitor connected between the second pull-up node and the carry signal output end; a second pull-up node potential pull-down module configured to pull down the potential of the second pull-up node to the first low level when the potential of the first pull-down node or the second pull-down node is a high level; a third control clock switch configured to enable the third control clock input end to be electrically connected to a third pull-down node when the third control clock signal is at a high level; a fourth control clock switch configured to enable the fourth control clock input end to be electrically connected to a fourth pull-down node when a fourth control clock signal is at a high level; a third pull-down node potential pull-down module configured to pull down a potential of the third pull-down node to the first low level when the potential of the second pull-up node or a potential of the fourth pull-down node is a high level; a fourth pull-down node potential pull-down module connected to the reset signal input end and configured to pull down the potential of the fourth pull-down node to the first low level when the potential of the second pull-up node or the third pull-down node is a high level; a second carry control module configured to enable the carry signal output end to be electrically connected to the fourth control clock input end when the potential of the second pull-up node is a high level; a second carry signal pull-down module configured to pull down the potential of the carry signal to the first low level when the potential of the third pull-down node or the fourth pull-down node is a high level; a second cut-off control module configured to enable the fourth control clock input end to be electrically connected to the cut-off control signal output end when the potential of the second pull-up node is a high level, and enable the cut-off control signal output end to be electrically connected to the second low level output end when the potential of the third pull-down node or the fourth pull-down node is a high level; a second feedback module configured to transmit the cut-off control signal to the second pull-up node potential pull-up module and the second pull-up node potential pull-down module when the carry signal is at a high level; a driving control submodule configured to enable the fourth control clock input end to be electrically connected to the driving control signal pull-down control end when the potential of the second pull-up node is a high level; a driving control signal pull-down control module configured to pull down a potential of the driving control signal pull-down control end to the second low level when the potential of the third pull-down node or the fourth pull-down node is a high level; a driving control signal pull-up module configured to pull up a potential of the driving control signal to a high level when the driving control signal pull-down control end outputs a high level; and a driving control signal pull-down module configured to pull down the potential of the driving control signal to the second low level when the driving control signal pull-down control end outputs a high level.

During the implementation, the first pull-up node potential pull-up module includes:

a first pull-up node potential pull-up transistor, a gate electrode and a first electrode of which are connected to the first start signal input end, and a second electrode of which is connected to the first feedback module; and a second pull-up node potential pull-up transistor, a gate electrode of which is connected to the first control clock input end, a first electrode of which is connected to the second electrode of the first pull-up node potential pull-up transistor, and a second electrode of which is connected to the first pull-up node.

The first pull-up node potential pull-down module includes:

a first pull-up node potential pull-down transistor, a gate electrode of which is connected to the first pull-down node, a first electrode of which is connected to the first pull-up node, and a second electrode of which is connected to the first feedback module; a second pull-up node potential pull-down transistor, a gate electrode of which is connected to the first pull-down node, a first electrode of which is connected to the second electrode of the first pull-up node potential pull-down transistor, and a second electrode of which is connected to the first low level; a third pull-up node potential pull-down transistor, a gate electrode of which is connected to the second pull-down node, a first electrode of which is connected to the first pull-up node, and a second electrode of which is connected to the first feedback module; and a fourth pull-node potential pull-down transistor, a gate electrode of which is connected to the second pull-down node, a first electrode of which is connected to the second electrode of the third pull-up node potential pull-down transistor, and a second electrode of which is connected to the first low level.

The first pull-down node potential pull-down module includes:

a first pull-down transistor, a gate electrode of which is connected to the first pull-up node, a first electrode of which is connected to the first pull-down node, and a second electrode of which is connected to the reset signal input end; a second pull-down transistor, a gate electrode of which is connected to the first pull-up node, a first electrode of which is connected to the second electrode of the first pull-down transistor, and a second electrode of which is connected to the first low level; and a third pull-down transistor, a gate electrode of which is connected to the second pull-down node, a first electrode of which is connected to the first pull-down node, and a second electrode of which is connected to the first low level.

The second pull-down node potential pull-down module includes:

a fourth pull-down transistor, a gate electrode of which is connected to the first pull-up node, a first electrode of which is connected to the second pull-down node, and a second electrode of which is connected to the reset signal input end; a fifth pull-down transistor, a gate electrode of which is connected to the first pull-up node, a first electrode of which is connected to the second electrode of the fourth pull-down transistor, and a second electrode of which is connected to the first low level; and a sixth pull-down transistor, a gate electrode of which is connected to the first pull-down node, a first electrode of which is connected to the second pull-down node, and a second electrode of which is connected to the first low level.

During the implementation, the first carry control module includes:

a first carry control transistor, a gate electrode of which is connected to the first pull-up node, a first electrode of which is connected to the second control clock input end, and a second electrode of which is connected to the carry signal output end.

The first carry signal pull-down module includes:

a first carry signal pull-down transistor, a gate electrode of which is connected to the first pull-down node, a first electrode of which is connected to the carry signal output end, and a second electrode of which is connected to the first low level; and a second carry signal pull-down transistor, a gate electrode of which is connected to the second pull-down node, a first electrode of which is connected to the carry signal output end, and a second electrode of which is connected to the first low level.

The first cut-off control module includes:

a first cut-off control transistor, a gate electrode of which is connected to the first pull-up node, a first electrode of which is connected to the second control clock input end, and a second electrode of which is connected to the cut-off control signal output end; a second cut-off control transistor, a gate electrode of which is connected to the first pull-down node, a first electrode of which is connected to the cut-off control signal output end, and a second electrode of which is connected to the first low level; and a third cut-off control transistor, a gate electrode of which is connected to the second pull-down node, a first electrode of which is connected to the cut-off control signal output end, and a second electrode of which is connected to the first low level.

The first feedback module includes:

a first feedback transistor, a gate electrode of which is connected to the carry signal output end, a first electrode of which is connected to the second electrode of the first pull-up node potential pull-up transistor, and a second electrode of which is connected to the cut-off control signal output end.

During the implementation, the gate scanning signal control module includes:

a gate scanning control transistor, a gate electrode of which is connected to the first pull-up node, a first electrode of which is connected to the second control clock signal, and a second electrode of which is connected to the gate scanning signal output end.

The gate scanning signal pull-down module includes:

a first output pull-down transistor, a gate electrode of which is connected to the first pull-down node, a first electrode of which is connected to the gate scanning signal output end, and a second electrode of which is connected to the second low level; and a second output pull-down transistor, a gate electrode of which is connected to the second pull-down node, a first electrode of which is connected to the gate scanning signal output end, and a second electrode of which is connected to the second low level.

The output level pull-up module includes:

an output level pull-up transistor, a gate electrode and a first electrode of which are connected to a high level, and a second electrode of which is connected to the output level end.

The output level pull-down control module includes:

a first pull-down control transistor, a gate electrode of which is connected to the first pull-down node, a first electrode of which is connected to the output level pull-down control end, and a second electrode of which is connected to the second low level; and a second pull-down control transistor, a gate electrode of which is connected to the second pull-down node, a first electrode of which is connected to the output level pull-down control end, and a second electrode of which is connected to the second low level.

The output level pull-down module includes:

an output level pull-down transistor, a gate electrode of which is connected to the output level pull-down control end, a first electrode of which is connected to the output level end, and a second electrode of which is connected to the second low level.

During the implementation, the second pull-up node potential pull-up module includes:

a third pull-up node potential pull-up transistor, a gate electrode and a first electrode of which are connected to the second start signal input end, and a second electrode of which is connected to the second feedback module; and a fourth pull-up node potential pull-up transistor, a gate electrode of which is connected to the third control clock input end, a first electrode of which is connected to the second electrode of the third pull-up node potential pull-up transistor, and a second electrode of which is connected to the second pull-up node.

The second pull-up node potential pull-down module includes:

a fifth pull-up node potential pull-down transistor, a gate electrode of which is connected to the third pull-down node, a first electrode of which is connected to the second pull-up node, and a second electrode of which is connected to the second feedback module; a sixth pull-up node potential pull-down transistor, a gate electrode of which is connected to the third pull-down node, a first electrode of which is connected to the second electrode of the fifth pull-up node potential pull-down transistor, and a second electrode of which is connected to the first low level; a seventh pull-up node potential pull-down transistor, a gate electrode of which is connected to the fourth pull-down node, a first electrode of which is connected to the second pull-up node, and a second electrode of which is connected to the second feedback module; and an eighth pull-up node potential pull-down transistor, a gate electrode of which is connected to the fourth pull-down node, a first electrode of which is connected to the second electrode of the seventh pull-up node potential pull-down transistor, and a second electrode of which is connected to the first low level.

The third pull-down node potential pull-down module includes:

a seventh pull-down transistor, a gate electrode of which is connected to the second pull-up node, a first electrode of which is connected to the third pull-down node, and a second electrode of which is connected to the reset signal input end; an eighth pull-down transistor, a gate electrode of which is connected to the second pull-up node, a first electrode of which is connected to the second electrode of the seventh pull-down transistor, and a second electrode of which is connected to the first low level; and a ninth pull-down transistor, a gate electrode of which is connected to the fourth pull-down node, a first electrode of which is connected to the third pull-down node, and a second electrode of which is connected to the first low level.

The fourth pull-down node potential pull-down module includes:

a tenth pull-down transistor, a gate electrode of which is connected to the second pull-up node, a first electrode of which is connected to the fourth pull-down node, and a second electrode of which is connected to the reset signal input end; an eleventh pull-down transistor, a gate electrode of which is connected to the second pull-up node, a first electrode of which is connected to the second electrode of the tenth pull-down transistor, and a second electrode is connected to the first low level; and a twelfth pull-down transistor, a gate electrode of which is connected to the third pull-down node, a first electrode of which is connected to the fourth pull-down node, and a second electrode of which is connected to the first low level.

During the implementation, the second carry control module includes:

a second carry control transistor, a gate electrode of which is connected to the second pull-up node, a first electrode of which is connected to the fourth control clock input end, and a second electrode of which is connected to the carry signal output end.

The second carry signal pull-down module includes:

a third carry signal pull-down transistor, a gate electrode of which is connected to the third pull-down node, a first electrode of which is connected to the carry signal output end, and a second electrode of which is connected to the first low level; and a fourth carry signal pull-down transistor, a gate electrode of which is connected to the fourth pull-down node, a first electrode of which is connected to the carry signal output end, and a second electrode of which is connected to the first low level.

The second cut-off control module includes:

a fourth cut-off control transistor, a gate electrode of which is connected to the second pull-up node, a first electrode of which is connected to the fourth control clock input end, and a second electrode of which is connected to the cut-off control signal output end; a fifth cut-off control transistor, a gate electrode of which is connected to the third pull-down node, a first electrode of which is connected to the cut-off control signal output end, and a second electrode of which is connected to the first low level; and a sixth cut-off control transistor, a gate electrode of which is connected to the fourth pull-down node, a first electrode of which is connected to the cut-off control signal output end, and a second electrode of which is connected to the first low level.

The second feedback module includes:

a second feedback transistor, a gate electrode of which is connected to the carry signal output end, a first electrode of which is connected to the second electrode of the third pull-up node potential pull-up transistor, and a second electrode of which is connected to the cut-off control signal output end.

During the implementation, the driving control submodule includes a driving control transistor, a gate electrode of which is connected to the second pull-up node, a first electrode of which is connected to the fourth control clock input end, and a second electrode of which is connected to the driving control signal pull-down control end.

The driving control signal pull-up module includes:

a driving control pull-up transistor, a gate electrode and a first electrode of which are connected to a high level, and a second electrode of which is connected to the driving control signal output end.

The driving control signal pull-down control module includes:

a first driving pull-down control transistor, a gate electrode of which is connected to the third pull-down node, a first electrode of which is connected to the driving control signal pull-down control end, and a second electrode of which is connected to the second low level; and a second driving pull-down control transistor, a gate electrode of which is connected to the fourth pull-down node, a first electrode of which is connected to the driving control signal pull-down control end, and a second electrode of which is connected to the second low level.

The driving control signal pull-down module includes:

a driving pull-down transistor, a gate electrode of which is connected to the driving control signal pull-down control end, a first electrode of which is connected to the driving control signal output end, and a second electrode of which is connected to the second low level.

During the implementation, the first control clock signal is of a phase reverse to a phase of the second control clock signal, and duty ratios of the first control clock signal, the second control clock signal and the first start signal are all 0.5. The third control clock signal is of a phase reverse to a phase of the fourth control clock signal, and duty ratios of the third control clock signal, the fourth control clock signal and the second start signal are all less than 0.5.

In another aspect, the present disclosure provides a gate driving method for use in the above-mentioned gate driver circuit, including:

within a clock cycle after a first start signal input end inputs a high level, outputting, by a gate scanning signal output end, a high level, and a phase of an output signal from an output level end being reverse to a phase of an input clock signal; and within a clock cycle after a second start signal input end inputs a high level, a phase of a driving control signal being reverse to a phase of a second start signal.

In yet another aspect, the present disclosure provides a GOA circuit including multiple levels of the above-mentioned gate driver circuits. Apart from a first-level gate driver circuit, a cut-off control signal output end of each level of gate driver circuit is connected to a reset signal input end of a previous-level gate driver circuit, and apart from a last-level gate driver circuit, a carry signal output end of each level of gate driver circuit is connected to a first start signal input end of a next-level gate driver circuit.

During the implementation, the input clock signal inputted to an (n+1) th -level gate driver circuit is of a phase reverse to a phase of the input clock signal inputted to an n th -level gate driver circuit. N is an integer greater than or equal to 1, and (n+1) is less than or equal to the number of levels of the gate driver circuits included in the GOA circuit.

In still yet another aspect, the present disclosure provides a display device including the above-mentioned gate driver circuit.

During the implementation, the display device is an OLED display device or a low temperature poly-silicon (LTPS) display device.

In still yet another aspect, the present disclosure provides an electronic product including the above-mentioned display device.

As compared with the prior art, according to the gate driver circuit, the gate driving method, the GOA circuit, the display device and the electronic device of the present disclosure, the row pixel controlling unit is configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for the threshold voltage of the driving transistor. In addition, the driving control unit is configured to provide the driving control signal to the driving module, so as to control the driving module to drive the light-emitting device. As a result, it is able to compensate for the pixel threshold voltage and drive the pixel simultaneously. In addition, by applying the gate driver circuit and the GOA circuit of the present disclosure to an OLED display panel, it is able to improve the integration level of the OLED display panel, thereby to reduce the protection cost.

FIG. 1A is a schematic view showing the connection of a gate driver circuit and a pixel unit according to one embodiment of the present disclosure;

FIG. 1B is a circuit diagram of a pixel driving module of the pixel unit connected to the gate driver circuit according to one embodiment of the present disclosure;

FIG. 1C is an operation sequence diagram of the pixel driving module in FIG. 1B ;

FIG. 2 is a block diagram showing a structure of the pixel driving unit of the gate driver circuit according to one embodiment of the present disclosure;

FIG. 3 is a circuit diagram of the pixel driving unit of the gate driver circuit according to one embodiment of the present disclosure;

FIG. 4 is a block diagram showing a structure of a driving control unit of the gate driver circuit according to one embodiment of the present disclosure;

FIG. 5 is a circuit diagram of the driving control unit of the gate driver circuit according to one embodiment of the present disclosure;

FIG. 6A is waveforms of a first start signal, a second start signal, a first control clock signal, a second control clock signal, an input clock signal inputted to an n th -level gate driver circuit and an input clock signal inputted to an (n+1) th -level gate driver circuit during the operation of a GOA circuit according to one embodiment of the present disclosure; and

FIG. 6B is an operation sequence diagram of the GOA circuit according to one embodiment of the present disclosure.

A gate driver circuit of the present disclosure is connected to a row of pixel units, each pixel unitincludes a pixel driving module and a light-emitting device connected to each other. The pixel driving module includes a driving transistor, a driving module and a compensating module, the compensating module is connected to a gate scanning signal, and the driving module is connected to a driving control signal and a driving voltage.

The gate driver circuit includes a row pixel controlling unit configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor; and a driving control unit configured to provide the driving control signal to the driving module so as to control the driving module to drive the light-emitting device.

According to the gate driver circuit of the present disclosure, the row pixel controlling unit is configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for the threshold voltage of the driving transistor. In addition, the driving control unit is configured to provide the driving control signal to the driving module, so as to control the driving module to drive the light-emitting device. As a result, the gate driver circuit capable of compensating for the pixel threshold voltage is obtained.

The gate driver circuit of the present disclosure may be applied to an OLED display panel, so as to improve an integration level of the OLED display panel, thereby to reduce the production cost.

As shown in FIG. 1A , each pixel unit includes a pixel driving module and an OLED connected to each other. A cathode of the OLED is connected to a low level ELVSS. The pixel driving module includes a driving transistor T 1 , a driving module 102 , and a compensating module 101 . The compensating module 101 is connected to a gate scanning signal GO_S 1 ( n ), and the driving module 102 is connected to a driving control signal GO_S 2 ( n ) and a driving voltage GO_ELVDD (n). The gate driver circuit includes a row pixel controlling unit 11 configured to provide the gate scanning signal GO_S 1 ( n ) to the compensating module 101 and provide the driving voltage GO_ELVDD (n) to the driving module 102 , so as to control the compensating module 101 to compensate for a threshold voltage of the driving transistor T 1 ; and a driving control unit 12 configured to provide the driving control signal GO_S 2 ( n ) to the driving module 102 so as to control the driving module 102 to drive the OLED.

As shown in FIG. 1B , the pixel driving module according to one embodiment includes the driving transistor T 1 , a compensating transistor T 2 , a driving control transistor T 3 , a first capacitor C 1 and a second capacitor C 2 . T 2 is included in the compensating module, and T 3 is included in a driving control module. A gate electrode of T 2 is connected to a gate scanning signal S 1 , a second electrode of T 2 is connected to a data signal DATA, a gate electrode of T 3 is connected to a driving control signal S 2 , a first electrode of T 3 is connected to an output level ELVDD, and a cathode of the OLED is connected to a level ELVSS.

FIG. 1C is an operation sequence diagram of the pixel driving module in FIG. 1B .

The present disclosure provides a GOA unit capable of cooperating with a Vth (threshold) compensation pixel design. The GOA unit can output two signals, one of which is a high-level pulse signal that may serve as the gate scanning signal (e.g., S 1 in FIG. 1 ), and the other of which is a low-level pulse signal that may serve as ELVDD (as shown in FIG. 1A ). Taking a commonly-used 3T2C threshold-compensated OLED pixel as an example, in order to drive the pixel, a low-level pulse signal S 2 is further desired so as to control the signal ELVDD. In a GOA circuit, the low-level pulse signal S 2 in an n th row may be used as the signal ELVDD in an (n+1) th row. By adjusting the sequence of the start signals and the clock signals, it is able to compensate for the threshold of the pixel and drive the pixel.

The gate driver circuit in this embodiment includes two portions, i.e., a left portion and a right portion, with respect to a display region of a panel. The row pixel controlling unit arranged on the left can provide the gate scanning signal GO_S 1 ( n ) and the driving voltage GO_ELVDD (n) to the pixel, while the driving control unit arranged on the right can provide the driving control signal GO_S 2 ( n ) to the pixel. By adjusting the start signals and clock signals for the left and right portions, it is able to compensate for the threshold of the pixel and drive the pixel.

As shown in FIG. 2 , in the gate driver circuit of the present disclosure, the row pixel controlling unit includes a first start signal input end STV 1 , a first control clock input end CLKA, a second control clock input end CLKB, a reset signal input end RESET (n), an input clock end CLKIN (n), a carry signal output end COUT (n), a cut-off control signal output end IOFF (n), an output level end GO_ELVDD (n), an output level pull-down control end G_VDD, a gate scanning signal output end GO_S 1 ( n ).

The row pixel controlling unit further includes:

a first pull-up node potential pull-up module 101 configured to pull up a potential of a first pull-up node Q 1 to a high level when a first control clock signal and a first start signal are at a high level; a first storage capacitor C connected between the first pull-up node Q 1 and the carry signal output end COUT (n); a first pull-up node potential pull-down module 102 configured to pull down the potential of the first pull-up mode Q 1 to a first low level VGL 1 when a potential of a first pull-down node QB 1 or a second pull-down node QB 2 is a high level; a first control clock switch 141 configured to enable the first control clock input end CLKA to be electrically connected to the first pull-down node QB 1 when the first control clock signal is at a high level; a second control clock switch 142 configured to enable the second control clock input end CLKB to be electrically connected to the second pull-down node QB 2 when a second control clock signal is at a high level; a first pull-down node potential pull-down module 12 configured to pull down the potential of the first pull-down node QB 1 to the first low level VGL 1 when the potential of the first pull-up node Q 1 or the second pull-down node QB 2 is a high level; a second pull-down node potential pull-down module 13 connected to the reset signal input end RESET (n) and configured to pull down the potential of the second pull-down node QB 2 to the first low level VGL 1 when the potential of the first pull-up node Q 1 or the first pull-down node QB 1 is a high level; a first carry control module 151 configured to enable the carry signal output end COUT (n) to be electrically connected to the second clock signal input end CLKB when the potential of the first pull-up node Q 1 is a high level; a first carry signal pull-down module 152 configured to pull down a potential of a carry signal to the first low level VGL 1 when the potential of the first pull-down node QB 1 or the second pull-down node QB 2 is a high level; a first cut-off control module 161 configured to enable the second clock signal input end CLKB to be electrically connected to the cut-off control signal output end IOFF (n) when the potential of the first pull-up node Q 1 is a high level, and enable the cut-off control signal output end IOFF (n) to be electrically connected to a second low level output end VGL 2 when the potential of the first pull-down node QB 1 or the second pull-down node QB 2 is a high level; a first feedback module 162 configured to transmit a cut-off control signal to the first pull-up node potential pull-up module 101 and the first pull-up node potential pull-down module 102 when the carry signal is at a high level; a gate scanning signal control module 171 configured to enable the second control clock input end CLKB to be electrically connected to the gate scanning signal output end GO_S 1 ( n ) when the potential of the first pull-up node Q 1 is a high level; an input clock switch 181 configured to enable the input clock end CLKIN (n) to be electrically connected to the output level pull-down control end G_VDD when the potential of the first pull-up node Q 1 is a high level; a gate scanning signal pull-down module 172 configured to pull down a potential of the gate scanning signal to a second low level VGL 2 when the potential of the first pull-down node QB 1 or the second pull-down node QB 2 is a high level; an output level pull-up module 182 configured to pull up an output level to a high level when the output level pull-down control end G_VDD outputs the second low level VGL 2 ; an output level pull-down control module 183 configured to pull down a potential of the output level pull-down control end G_VDD to the second low level VGL 2 when the potential of the first pull-down node QB 1 or the second pull-down node QB 2 is a high level; and an output level pull-down module 184 configured to pull down the output level to the second low level VGL 2 when the output level pull-down control end G_VDD outputs a high level.

The row pixel controlling unit of the gate driver circuit in this embodiment includes two pull-down nodes, i.e., the first pull-down node QB 1 and the second pull-down node QB 2 , so as to pull down the output. During a non-output period, the first pull-down node QB 1 and the second pull-down node QB 2 are alternating and complementary to each other. As a result, it is able to reduce a threshold voltage shift and prevent the occurrence of a time interval when pulling down the output, thereby to improve the stability and reliability.

During the operation of the row pixel controlling unit of the gate driver circuit in this embodiment, it is able to compensate for the pixel threshold voltage by adjusting the first start signal, the first control clock signal, the second control clock signal and the input clock signal.

The transistor used in all the embodiments of the present disclosure may be a TFT or FET, or any other device having the same characteristics. In the embodiments of the present disclosure, in order to differentiate two electrodes of the transistor except a gate electrode, one of the electrodes is called as a source electrode, and the other is called as a drain electrode. In addition, the transistor may be an N-type or P-type transistor on the basis of its characteristics. It is readily conceivable for a person skilled in the art, without any creative effort, to implement the driver circuit of the present disclosure with the N-type or P-type transistors, and it also falls within the scope of the present disclosure.

In the driver circuit of the present disclosure, a first electrode of the N-type transistor may be a source electrode, and a second electrode thereof may be a drain electrode. A first electrode of the P-type transistor may be a drain electrode, and a second electrode thereof may be a source electrode.

To be specific, as shown in FIG. 3 , the first pull-up node potential pull-up module 101 of the gate driver circuit includes:

a first pull-up node potential pull-up transistor T 101 , a gate electrode and a first electrode of which are connected to the first start signal input end STV 1 , and a second electrode of which is connected to the first feedback module 162 ; and a second pull-up node potential pull-up transistor T 102 , a gate electrode of which is connected to the first control clock input end CLKA, a first electrode of which is connected to the second electrode of the first pull-up node potential pull-up transistor T 101 , and a second electrode of which is connected to the first pull-up node Q 1 .

The pull-up node potential pull-down module 102 includes:

a first pull-up node potential pull-down transistor T 201 , a gate electrode of which is connected to the first pull-down node QB 1 , a first electrode of which is connected to the first pull-up node Q 1 , and a second electrode of which is connected to the first feedback module 162 ; a second pull-up node potential pull-down transistor T 202 , a gate electrode of which is connected to the first pull-down node QB 1 , a first electrode of which is connected to the second electrode of the first pull-up node potential pull-down transistor T 201 , and a second electrode of which is connected to the first low level VGL 1 ; a third pull-up node potential pull-down transistor T 203 , a gate electrode of which is connected to the second pull-down node QB 2 , a first electrode of which is connected to the first pull-up node Q 1 , and a second electrode of which is connected to the first feedback module 162 ; and a fourth pull-up node potential pull-down transistor T 204 , a gate electrode of which is connected to the second pull-down node QB 2 , a first electrode of which is connected to the second electrode of the third pull-up node potential pull-down transistor T 203 , and a second electrode of which is connected to the first low level VGL 1 .

The first pull-down node potential pull-down module 12 includes:

a first pull-down transistor T 21 , a gate electrode of which is connected to the first pull-down node Q 1 , a first electrode of which is connected to the first pull-down node QB 1 , and a second electrode of which is connected to the reset signal input end RESET (n); a second pull-down transistor T 22 , a gate electrode of which is connected to the first pull-up node Q 1 , a first electrode of which is connected to the second electrode of the first pull-down transistor T 21 , and a second electrode of which is connected to the first low level VGL 1 ; and a third pull-down transistor T 23 , a gate electrode of which is connected to the second pull-down node QB 2 , a first electrode of which is connected to the first pull-down node QB 1 , and a second electrode of which is connected to the first low level VGL 1 .

The second pull-down node potential pull-down module 13 includes:

a fourth pull-down transistor T 31 , a gate electrode of which is connected to the first pull-up node Q 1 , a first electrode of which is connected to the second pull-down node QB 2 , and a second electrode of which is connected to the reset signal input end RESET (n);

a fifth pull-down transistor T 32 , a gate electrode of which is connected to the first pull-up node Q 1 , a first electrode of which is connected to the second electrode of the fourth pull-down transistor T 31 , and a second electrode of which is connected to the first low level VGL 1 ; and

a sixth pull-down transistor T 33 , a gate electrode of which is connected to the first pull-down node QB 1 , a first electrode of which is connected to the second pull-down node QB 2 , and a second electrode of which is connected to the first low level VGL 1 .

Referring to FIGS. 2 and 3 , the carry control module 151 includes:

a carry control transistor T 51 , a gate electrode of which is connected to the first pull-up node Q 1 , a first electrode of which is connected to the second control clock input end CLKB, and a second electrode of which is connected to the carry signal output end COUT (n).

The carry signal pull-down module 152 includes:

a first carry signal pull-down transistor T 521 , a gate electrode of which is connected to the first pull-down node QB 1 , a first electrode of which is connected to the carry signal output end COUT (n), and a second electrode of which is connected to the first low level VGL 1 ; and a second carry signal pull-down transistor T 522 , a gate electrode of which is connected to the second pull-down node QB 2 , a first electrode of which is connected to the carry signal output end COUT (n), and a second electrode of which is connected to the first low level VGL 1 .

The first cut-off control module 161 includes:

a first cut-off control transistor T 611 , a gate electrode of which is connected to the first pull-up node Q 1 , a first electrode of which is connected to the second control clock input end CLKB, and a second electrode of which is connected to the cut-off control signal output end IOFF (n); a second cut-off control transistor T 612 , a gate electrode of which is connected to the first pull-down node QB 1 , a first electrode of which is connected to the cut-off control signal output end IOFF (n), and a second electrode of which is connected to the first low level VGL 1 ; and a third cut-off control transistor T 613 , a gate electrode of which is connected to the second pull-down node QB 2 , a first electrode of which is connected to the cut-off control signal output end IOFF (n), and a second electrode of which is connected to the first low level VGL 1 .

The first feedback module 162 includes:

a first feedback transistor T 62 , a gate electrode of which is connected to the first carry signal output end COUT (n), a first electrode of which is connected to the second electrode of the first pull-up node potential pull-up transistor T 101 , and a second electrode of which is connected to the cut-off control signal output end IOFF (n).

As shown in FIG. 3 , the gate scanning signal control module 171 includes:

a gate scanning control transistor T 71 , a gate electrode of which is connected to the first pull-up node Q 1 , a first electrode of which is connected to the second control clock signal CLKB, and a second electrode of which is connected to the gate scanning signal output end GO_S 1 ( n ).

The gate scanning signal pull-down module 172 includes:

a first output pull-down transistor T 721 , a gate electrode of which is connected to the first pull-down node QB 1 , a first electrode of which is connected to the gate scanning signal output end GO_S 1 ( n ), and a second electrode of which is connected to the second low level VGL 2 ; and a second output pull-down transistor T 722 , a gate electrode of which is connected to the second pull-down node QB 2 , a first electrode of which is connected to the gate scanning signal output end GO_S 1 ( n ), and a second electrode of which is connected to the second low level VGL 2 .

The input clock switch 181 includes an input transistor T 81 , a gate electrode of which is connected to the first pull-up node Q 1 , a first electrode of which is connected to CLKIN (n), and a second electrode of which is connected to G_VDD.

The output level pull-up module 182 includes an output level pull-up transistor T 82 , a gate electrode and a first electrode of which are connected to the high level VDD, and a second electrode of which is connected to the output level end GO_ELVDD (n).

The output level pull-down control module 183 includes:

a first pull-down control transistor T 831 , a gate electrode of which is connected to the first pull-down node QB 1 , a first electrode of which is connected to the output level pull-down control end G_VDD, and a second electrode of which is connected to the second low level VGL 2 ; and a second pull-down control transistor T 832 , a gate electrode of which is connected to the second pull-down node QB 2 , a first electrode of which is connected to the output level pull-down control end G_VDD, and a second electrode of which is connected to the second low level VGL 2 .

The output level pull-down module 184 includes:

an output level pull-down transistor T 84 , a gate electrode of which is connected to the output level pull-down control end G_VDD, a first electrode of which is connected to the output level end GO_ELVDD (n), and a second electrode of which is connected to the second low level VGL 2 .

During the implementation, the first control clock signal is complementary to the second control clock signal.

As shown in FIG. 3 , the first control clock switch 141 includes a first control transistor T 41 , a gate electrode and a first electrode of which are connected to CLKA, and a second electrode of which is connected to QB 1 . The second control clock switch 142 includes a second control transistor T 42 , a gate electrode and a first electrode of which are connected to CLKB, and a second electrode of which is connected to QB 2 . The first storage capacitor C 1 is connected between Q and COUT (n).

In the embodiment as shown in FIG. 3 , T 101 , T 102 , T 42 , T 201 , T 202 , T 203 and T 204 are P-type transistors, while T 21 , T 22 , T 31 , T 32 , T 41 , T 51 , T 521 , T 522 , T 611 , T 612 , T 613 , T 62 , T 71 , T 721 , T 722 , T 81 , T 82 , T 831 , T 832 and T 84 are N-type transistors. In the other embodiments, various transistors may be adopted, as long as they can achieve the same control effects of turning on and turning off.

As shown in FIG. 4 , the driving control unit includes a second start signal input end STV 2 , a third control clock input end CLKC, a fourth control clock input end CLKD, a driving control signal output end GO_S 2 ( n ) and a driving control signal pull-down control end G_S 2 . The driving control unit is connected to the reset signal input end RESET (n), the carry signal output end COUT (n) and the cut-off control signal output end IOFF (n), respectively.

The driving control unit further includes:

a second pull-up node potential pull-up module 103 configured to pull up a potential of a second pull-up node Q 2 to a high level when a third control clock signal and a second start signal are at a high level; a second storage capacitor C 2 connected between the second pull-up node Q 2 and the carry signal output end COUT (n); a fourth pull-up node potential pull-down module 104 configured to pull down the potential of the second pull-up node Q 2 to the first low level VGL 1 when a potential of a third pull-down node QB 3 or a fourth pull-down node QB 4 is a high level; a third control clock switch 143 configured to enable the third control clock input end CLKC to be electrically connected to the third pull-down node QB 3 when the third control clock signal is at a high level; a fourth control clock switch 144 configured to enable the fourth control clock input end CLKD to be electrically connected to the fourth pull-down node QB 4 when a fourth control clock signal is at a high level; a third pull-down node potential pull-down module 14 configured to pull down the potential of the third pull-down node QB 3 to the first low level VGL 1 when the potential of the second pull-up node Q 2 or the fourth pull-down node QB 4 is a high level; a fourth pull-down node potential pull-down module 15 connected to the reset signal input end RESET (n) and configured to pull down the potential of the fourth pull-down node QB 4 to the first low level VGL 1 when the potential of the second pull-up node Q 2 or the third pull-down node QB 3 is a high level; a second carry control module 153 configured to enable the carry signal output end COUT (n) to be electrically connected to the fourth clock signal input end CLKD when the potential of the second pull-up node Q 2 is a high level; a second carry signal pull-down module 154 configured to pull down the potential of the carry signal to the first low level VGL 1 when the potential of the third pull-down node QB 3 or the fourth pull-down node QB 4 is a high level; a second cut-off control module 163 configured to enable the fourth clock signal input end CLKD to be electrically connected to the cut-off control signal output end IOFF (n) when the potential of the second pull-up node Q 2 is a high level, and enable the cut-off control signal output end IOFF (n) to be electrically connected to the second low level output end when the potential of the first pull-down node QB 1 or the second pull-down node QB 2 is a high level, the second low level output end outputting the second low level VGL 2 ; a second feedback module 164 configured to transmit the cut-off control signal to a second pull-up node potential pull-up module 103 and the second pull-up node potential pull-down module 104 when the carry signal is at a high level; a driving control submodule 191 configured to enable the fourth control clock input end CLKD to be electrically connected to the driving control signal pull-down control end G_S 2 when the potential of the second pull-up node Q 2 is a high level; a driving control signal pull-up module 192 configured to pull up the potential of the driving control signal to the high level VDD when the driving control signal pull-down control end G_S 2 outputs a high level;

a driving control signal pull-down control module 193 configured to pull down a potential of the driving control signal pull-down control end G_S 2 to the second low level VGL 2 when the potential of the third pull-down node QB 3 or the fourth pull-down node QB 4 is a high level; and

a driving control signal pull-down module 194 configured to pull down the potential of the driving control signal to the second low level VGL 2 when the driving control signal pull-down control end G_S 2 outputs a high level.

The driving control unit of the gate driver circuit in this embodiment includes two pull-down nodes, i.e., the third pull-down node QB 3 and the fourth pull-down node QB 4 , so as to pull down the output. During a non-output period, the third pull-down node QB 3 and the fourth pull-down node QB 4 are alternating and complementary to each other. As a result, it is able to reduce a threshold voltage shift and prevent the occurrence of a time interval when pulling down the output, thereby to improve the stability and reliability.

During the operation of the gate driving unit of the gate driver circuit in this embodiment, it is able to drive the pixel by adjusting the second start signal, the third control clock signal and the fourth control clock signal.

Here, the types of the transistors used in all the embodiments of the present disclosure are not particularly defined. In other words, the transistor may be a TFT or FET, or any other device having the same characteristics. In the embodiments of the present disclosure, in order to differentiate two electrodes of the transistor except a gate electrode, one of the electrodes is called as a source electrode, and the other is called as a drain electrode. In addition, the transistor may be an N-type or P-type transistor on the basis of its characteristics. It is readily conceivable for a person skilled in the art, without any creative effort, to implement the driver circuit of the present disclosure with the N-type or P-type transistors, and it also falls within the scope of the present disclosure.

In the driver circuit of the present disclosure, a first electrode of the N-type transistor may be a source electrode, and a second electrode thereof may be a drain electrode. A first electrode of the P-type transistor may be a drain electrode, and a second electrode thereof may be a source electrode.

To be specific, as shown in FIG. 5 , in the driving control unit of the gate driver circuit in this embodiment, the second pull-up node potential pull-up module 103 includes:

a third pull-up node potential pull-up transistor T 103 , a gate electrode and a first electrode of which are connected to the second start signal input end STV 2 , and a second electrode of which is connected to the second feedback module 164 ; and a fourth pull-up node potential pull-up transistor T 104 , a gate electrode of which is connected to the third control clock input end CLKC, a first electrode of which is connected to the second electrode of the third pull-up node potential pull-up transistor T 103 , and a second electrode of which is connected to the second pull-up node Q 2 .

The second pull-up node potential pull-down module 104 includes:

a fifth pull-up node potential pull-down transistor T 205 , a gate electrode of which is connected to the third pull-down node QB 3 , a first electrode of which is connected to the second pull-up node Q 2 , and a second electrode of which is connected to the second feedback module 164 ; a sixth pull-up node potential pull-down transistor T 206 , a gate electrode of which is connected to the third pull-down node QB 3 , a first electrode of which is connected to the second electrode of the third pull-up node potential pull-down transistor T 203 , and a second electrode of which is connected to the first low level VGL 1 ; a seventh pull-up node potential pull-down transistor T 207 , a gate electrode of which is connected to the fourth pull-down node QB 4 , a first electrode of which is connected to the second pull-up node Q 2 , and a second electrode of which is connected to the second feedback module 164 ; and an eighth pull-up node potential pull-down transistor T 208 , a gate electrode of which is connected to the fourth pull-down node QB 4 , a first electrode of which is connected to the second electrode of the seventh pull-up node potential pull-down transistor T 207 , and a second electrode of which is connected to the first low level VGL 1 .

The third pull-down node potential pull-down module 14 includes:

a seventh pull-down transistor T 27 , a gate electrode of which is connected to the second pull-up node Q 2 , a first electrode of which is connected to the third pull-down node QB 3 , and a second electrode of which is connected to the reset signal input end RESET (n); an eighth pull-down transistor T 28 , a gate electrode of which is connected to the second pull-up node Q 2 , a first electrode of which is connected to the second electrode of the seventh pull-down transistor T 27 , and a second electrode of which is connected to the first low level VGL 1 ; and a ninth pull-down transistor T 29 , a gate electrode of which is connected to the third pull-down node QB 4 , a first electrode of which is connected to the third pull-down node QB 3 , and a second electrode of which is connected to the first low level VGL 1 .

The fourth pull-down node potential pull-down module 15 includes:

a tenth pull-down transistor T 51 , a gate electrode of which is connected to the second pull-up node Q 2 , a first electrode of which is connected to the second pull-down node QB 2 , and a second electrode of which is connected to the carry signal input end RESET (n); an eleventh pull-down transistor T 52 , a gate electrode of which is connected to the second pull-up node Q 2 , a first electrode of which is connected to the second electrode of the fourth pull-down transistor T 31 , and a second electrode of which is connected to the first low level VGL 1 ; and a twelfth pull-down transistor T 53 , a gate electrode of which is connected to the third pull-down node QB 3 , a first electrode of which is connected to the fourth pull-down node QB 4 , and a second electrode of which is connected to the first low level VGL 1 .

As shown in FIG. 5 , the second carry control module 153 includes:

a second carry control transistor T 52 , a gate electrode of which is connected to the second pull-up node Q 2 , a first electrode of which is connected to the fourth control clock input end CLKD, and a second electrode of which is connected to the carry signal output end COUT (n).

The second carry signal pull-down module 154 includes:

a third carry signal pull-down transistor T 541 , a gate electrode of which is connected to the third pull-down node QB 3 , a first electrode of which is connected to the carry signal output end COUT (n), and a second electrode of which is connected to the first low level VGL 1 ; and a fourth carry signal pull-down transistor T 542 , a gate electrode of which is connected to the fourth pull-down node QB 4 , a first electrode of which is connected to the carry signal output end COUT (n), and a second electrode of which is connected to the first low level VGL 1 .

The second cut-off control module 163 includes:

a fourth cut-off control transistor T 631 , a gate electrode of which is connected to the second pull-up node Q 2 , a first electrode of which is connected to the fourth control clock input end CLKD, and a second electrode of which is connected to the cut-off control signal output end IOFF (n); a fifth cut-off control transistor T 632 , a gate electrode of which is connected to the third pull-down node QB 3 , a first electrode of which is connected to the cut-off control signal output end IOFF (n), and a second electrode of which is connected to the first low level VGL 1 ; and a sixth cut-off control transistor T 633 , a gate electrode of which is connected to the fourth pull-down node QB 4 , a first electrode of which is connected to the cut-off control signal output end IOFF (n), and a second electrode of which is connected to the first low level VGL 1 .

The second feedback module 164 includes:

a second feedback transistor T 64 , a gate electrode of which is connected to the carry signal output end COUT (n), a first electrode of which is connected to the second electrode of the third pull-up node potential pull-up transistor T 103 , and a second electrode of which is connected to the cut-off control signal output end IOFF (n).

As shown in FIG. 5 , the driving control submodule 191 includes a driving control transistor T 91 , a gate electrode of which is connected to the second pull-up node Q 2 , a first electrode of which is connected to the fourth control clock input end CLKD, and a second electrode of which is connected to the driving control signal pull-down control end G_S 2 .

The second driving control signal pull-up module 192 includes:

a driving control pull-up transistor T 92 , a gate electrode and a first electrode of which are connected to the high level VDD, and a second electrode of which is connected to the driving control signal output end GO_S 2 ( n ).

The driving control signal pull-down control module 193 includes:

a first driving pull-down control transistor T 931 , a gate electrode of which is connected to the third pull-down node QB 3 , a first electrode of which is connected to the driving control signal pull-down control end G_S 2 , and a second electrode of which is connected to the second low level VGL 2 ; and a second driving pull-down control transistor T 932 , a gate electrode of which is connected to the fourth pull-down node QB 4 , a first electrode of which is connected to the driving control signal pull-down control end G_S 2 , and a second electrode of which is connected to the second low level VGL 2 .

The driving control signal pull-down module 194 includes:

a driving pull-down transistor T 94 , a gate electrode of which is connected to the driving control signal pull-down control end G_S 2 , a first electrode of which is connected to the driving control signal output end GO_S 1 ( n ), and a second electrode of which is connected to the second low level VGL 2 .

During the implementation, the first control clock signal is complementary to the second control clock signal.

As shown in FIG. 5 , the third control clock switch 143 includes a third control transistor T 43 , a gate electrode and a first electrode of which is connected to CLKC, and a second electrode of which is connected to QB 3 . The fourth control clock switch 144 includes a fourth control transistor T 44 , a gate electrode and a first electrode of which are connected to CLKD, and a second electrode of which is connected to QB 4 . The second storage capacitor C 2 is connected between Q 2 and COUT 2 ( n ).

In the embodiment as shown in FIG. 5 , T 103 , T 104 , T 44 , T 205 , T 206 , T 207 , T 208 , T 53 and T 29 are all P-type transistors, while T 27 , T 28 , T 51 , T 52 , T 43 , T 52 , T 541 , T 542 , T 631 , T 632 , T 633 , T 64 , T 91 , T 92 , T 931 , T 932 and T 94 are all N-type transistors. In the other embodiments, various transistors may be adopted, as long as they can achieve the same control effects of turning on and turning off.

As shown in FIG. 6A , the first control clock signal inputted by CLKA is of a phase reverse to the second control clock signal inputted by CLKB, and duty ratios of the first control clock signal, the second control clock signal and the first start signal inputted by STV 1 are all 0.5. The third control clock signal inputted by CLKC is of a phase reverse to the fourth control clock signal inputted by CLKD, and duty ratios of the third control clock signal, the fourth control clock signal and the second start signal inputted by STV 1 are all less than 0.5.

As shown in FIG. 6B , the phase relationship between GO_S 1 ( n ) and GO_S 2 ( n ) is identical to that between S 1 and S 2 in FIG. 1C .

The present disclosure further provides a gate driving method for use in the gate driver circuit, including the steps of:

within a clock cycle after a first start signal input end inputs a high level, outputting, by a gate scanning signal output end, a high level, and a phase of an output signal from an output level end being reverse to that of an input clock signal; and within a clock cycle after a second start signal input end inputs a high level, a phase of a driving control signal being reverse to that of a second start signal.

The present disclosure further provides a GOA circuit including multiple levels of the above-mentioned gate driver circuits. Apart from a first-level gate driver circuit, a cut-off control signal output end of each level of gate driver circuit is connected to a reset signal input end of a previous-level gate driver circuit, and apart from a last-level gate driver circuit, a carry signal output end of each level of gate driver circuit is connected to a first start signal input end of a next-level gate driver circuit.

During the implementation, the input clock signal CLKIN 1 inputted to an (n+1) th -level gate driver circuit is of a phase reverse to the input clock signal CLKIN 2 inputted to an n th -level gate driver circuit. N is an integer greater than or equal to 1, and (n+1) is less than or equal to the number of levels of the gate driver circuits included in the GOA circuit.

FIG. 6A is waveforms of STV 1 , STV 2 , CLKA, CLKB, CLKC, CLKD, CLKIN 1 and CLKIN 2 during the operation of the gate driver circuit according to one embodiment of the present disclosure, and FIG. 6B is waveforms of GO_S 1 ( n ), GO_S 1 ( n +1), GO_ELVDD (n), GO_ELVDD (n+1), GO_S 2 ( n ) and GO_S 2 ( n +1) outputted by the GOA circuit according to one embodiment of the present disclosure.

In the GOA circuit of the present disclosure, the carry signal outputted from a previous-level gate driver circuit is connected to the first start signal input end of an adjacent next-level gate driver circuit. Hence, the control clock signals are inputted to the row pixel controlling unit and the driving control unit of each level of gate driver circuit, respectively, so as to pull up the carry signal to a high level through the control clock signal for controlling the row pixel controlling unit and the control clock signal for controlling the driving control unit, thereby to increase a pre-charge time for the storage capacitors. The gate driver circuit of the present disclosure may be applied to an OLED display device or an LTPS display device.

The present disclosure further provides a display device including the above-mentioned gate driver circuit. The display device may be an OLED or LTPS display device.

The present disclosure further provides an electronic product including the above-mentioned display device. The structure and the operational principle of the display device included in the electronic product are identical to those mentioned in the above embodiments, and they will not be repeated herein. In addition, the structures of the other components of the electronic product may refer to those mentioned in the prior art, and they will not be particularly defined herein. The electronic product may be any product or member having a display function, such as household appliance, communication facility, engineering facility and electronic entertainment product.

The above are merely the preferred embodiments of the present disclosure. It should be noted that, a person skilled in the art may make further improvements and modifications without departing from the principle of the present disclosure, and these improvements and modifications shall also fall within the scope of the present disclosure.