Display apparatus

The application is a U.S. National Phase Entry of International Application No. PCT/CN2013/085700, filed on Oct. 22, 2013, designating the United States of America and claiming priority to Chinese Patent Application No. 201310329744.3, filed on Jul. 31, 2013. The present application claims priority to and the benefit of all the above-identified applications and all of the above-identified applications are incorporated by reference herein in their entireties.

The present disclosure relates to the field of display technology, and particularly to a display apparatus.

In the design of an existing display apparatus such as a liquid crystal display, gate drivers are typically integrated on an array substrate. For a small size display (usually referring to a display smaller than or equal to 19 inches), a structure of integrating gate drivers on a single side would be employed, that is, the gate drivers are only integrated on one end of the gate control lines of the array substrate. However, for a large size display (usually referring to a display larger than 19 inches), a structure of integrating gate drivers on both sides would be employed, that is, the gate drivers are integrated on both ends of the gate control lines of the array substrate. The reason is that the large size panel has a large size, long wiring and high resolution, and the resulting large load (including large resistance and large parasitic capacitance) would delay the gate signal, such that the delayed gate signal would result in negative effects such as insufficient charging of the pixels, non-uniform pictures, and the like. Therefore, all the large size panels as known employ the design of integrating gate drivers on both sides, that is, identical gate drivers are integrated on both ends of the gate control lines. As shown in FIG. 1 , the gate driver comprises a plurality of gate driving units 1 , the input terminals of the gate driving units 1 are connected to gate timing sequence signal lines Ck 1 , Ck 2 , Ck 3 and Ck 4 respectively, and the output terminals are connected to the (n−1) th , the n th , the (n+1) th and the (n+2) th rows of gate control lines respectively to drive the (n−1) th , the n th , the (n+1) th and the (n+2) th rows of gate control lines respectively. However, such a design makes the gate drivers occupy a large space, and makes the frame of the liquid crystal panel need more space, which affects the product size.

Embodiments of the present disclosure provide a display apparatus capable of reducing space occupied by gate drivers and reducing the product size.

A display apparatus provided by an embodiment of the present disclosure comprises a plurality of rows of gate control lines and a plurality of gate driving units, and further comprises a plurality of compensation units, and any of the compensation units is connected to the output terminals of two gate driving units and connected to one row of gate control line.

Optionally, the compensation unit comprises a first TFT and a second TFT; the source of the first TFT and the source of the second TFT are connected together and serve as a gate timing sequence signal input terminal of the compensation unit; the drain of the first TFT and the drain of the second TFT are connected together and serve as a driving output terminal of the compensation unit; the gate of the first TFT serves as a first control terminal of the compensation unit; the gate of the second TFT serves as a second control terminal of the compensation unit.

Optionally, the gate timing sequence signal input terminal of the compensation unit is connected to one row of gate timing sequence signal line; the driving output terminal of the compensation unit is connected to one row of gate control line; the first control terminal of the compensation unit is connected to the output terminal of one of the two gate driving units, and the second control terminal of the compensation unit is connected to the output terminal of the other one of the two gate driving units.

Optionally, the gate driving unit and the compensation unit are both integrated on the array substrate of the display apparatus.

Optionally, the display apparatus is a liquid crystal display.

Optionally, both ends of the first row of gate control line and the last row of gate control line of the a plurality of row of gate control lines are connected to gate driving units; except the first row of gate control line and the last row of gate control line, one end of other rows of gate control lines is connected to a compensation unit and the other end is connected to a gate driving unit, and the ends at the same side of two adjacent rows of gate control lines among said other rows of gate control lines are connected to gate driving units and compensation units respectively.

Optionally, the compensation unit connected to one end of any row of gate control line among said other rows of gate control lines is connected to the output terminals of the gate driving units connected to its adjacent previous and next rows of gate control lines, and the compensation unit drives the gate control line connected thereto based on the output of the gate driving units connected to the previous and next rows of gate control lines.

Optionally, among said other rows of gate control lines, the left end of an odd row of gate control line is connected to a gate driving unit, the right end of the odd row of gate control line is connected to a compensation unit, the left end of an even row of gate control line is connected to a compensation unit, and the right end of the even row of gate control line is connected to a gate driving unit.

Optionally, among said other rows of gate control lines, the right end of an odd row of gate control line is connected to a gate driving unit, the left end of the odd row of gate control line is connected to a compensation unit, the right end of an even row of gate control line is connected to a compensation unit, and the left end of the even row of gate control line is connected to a gate driving unit.

According to the display apparatus of embodiments of the present disclosure, the space occupied by gate drivers is dramatically reduced and the product size of the display apparatus is effectively reduced by changing the conventional structure of dual gate driving units for two sides to a new structure of a single gate driving unit for two sides plus a compensation unit.

FIG. 1 is a schematic structural diagram for gate driving as known;

FIG. 2 is a schematic structural connection diagram of a compensation unit of a display apparatus according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a display apparatus according to an embodiment of the present disclosure; and

FIG. 4 is a waveform of gate timing sequence signals outputted from gate timing sequence signal lines according to an embodiment of the present disclosure.

In the following, the present disclosure will be described in detail in connection with the figures and embodiments.

It is noted that, in the description of embodiments of the present disclosure, orientational or positional relations indicated by “up”, “down”, “left”, “right” or the like are the orientational or positional relations shown in the figures, and are only for purpose of simplified descriptions for facilitating the description of embodiments of the present disclosure, not for indicating or implying that the described apparatus or elements must have specific orientations. Therefore, they should be construed to limit the present disclosure.

As shown in FIG. 2 , Ck 1 , Ck 2 , Ck 3 and Ck 4 are gate timing sequence signal lines of a display apparatus, and 1 represents gate driving units. The display apparatus provided by an embodiment of the present disclosure comprises gate control lines and multiple gate driving units 1 , and further comprises multiple compensation units 2 . The compensation unit 2 is connected to the output terminals of two gate driving units 1 and connected to the gate control lines. The compensation unit 2 drives the gate control line connected thereto based on the output signals of the two gate driving units 1 to shift and transfer the gate signals to the gate control line.

The compensation unit 2 comprises a first Thin Film Transistor (TFT) T 1 and a second TFT T 2 ; the source of the first TFT T 1 is connected to the source of the second TFT T 2 and serves as a gate timing sequence signal input terminal of the compensation unit 2 ; the drain of the first TFT T 1 is connected to the drain of the second TFT T 2 and serves as a driving output terminal of the compensation unit 2 ; the gate of the first TFT T 1 serves as a first control terminal of the compensation unit 2 ; the gate of the second TFT T 2 serves as a second control terminal of the compensation unit 2 . The gate timing sequence signal input terminal of the compensation unit 2 is connected to the gate timing sequence signal line, the driving output terminal of the compensation unit 2 is connected to the gate control line, the first control terminal of the compensation unit 2 is connected to the output terminal of one of the two gate driving units 1 , and the second control terminal of the compensation unit 2 is connected to the output terminal of the other one of the two gate driving units 1 .

It is noted that, since the source and the drain of the TFT adopted herein are symmetric, the source and the drain thereof are exchangeable. In embodiment of the present disclosure, in order to distinguish the two electrodes other than the gate, one of the two electrodes is referred to as source, and the other electrode is referred to as drain. If the source is adopted as the signal input terminal, the drain is adopted as the signal output terminal, and vice versa.

Typically, the gate driving units 1 and the compensation units 2 are both integrated on the array substrate of the display apparatus. In this case, the size of the array substrate can be reduced effectively likewise.

The display apparatus can be a liquid crystal display or other display apparatus.

Since the compensation unit needs to be connected with two gate driving units for operation, in practice, the display apparatus comprises multiple rows of the gate control lines. Both ends of the first row of gate control line and the last row of gate control line of the multiple rows of gate control lines are connected to a gate driving unit; except for the first row of gate control line and the last row of gate control line, one end of other rows of gate control lines is connected to a compensation unit 2 and the other end is connected to a gate driving unit 1 , and the ends at the same side of two adjacent rows of gate control lines among said other rows of gate control lines are connected to gate driving units 1 and compensation units 2 respectively, in other words, the ends at the same side of said other rows of gate control lines are configured to connected with alternate gate driving units 1 and compensation units 2 . For example, among said other rows of gate control lines, the left end of an odd row of gate control line is connected to a gate driving unit 1 , the right end of the odd row of gate control line is connected to a compensation unit 2 , the left end of an even row of gate control line is connected to a compensation unit 2 , and the right end of the even row of gate control line is connected to a gate driving unit 1 ; as an alternative, among said other rows of gate control lines, the right end of the odd row of gate control line is connected to a gate driving unit 1 , the left end of the odd row of gate control line is connected to a compensation unit 2 , the right end of the even row of gate control line is connected to a compensation unit 2 , and the left end of the even row of gate control line is connected to a gate driving unit 1 . In the above technical solutions, the compensation unit 2 connected to one end of any row of gate control line among said other rows of gate control lines is connected to the output terminals of the gate driving units 1 connected to the adjacent previous and next rows of gate control lines, and the compensation unit 2 drives the gate control line connected thereto based on the output of the gate driving units 1 connected to the previous and next rows of gate control lines.

In order to better understand embodiments of the present disclosure, the specific structure and the operational principle of a display apparatus according to an embodiment of the present disclosure will be further described by means of one embodiment in the following.

As shown in FIG. 3 , the display apparatus of the embodiment comprises 6 rows of gate control lines, wherein L 1 -L 6 represent the first to sixth rows of gate control lines respectively, Ck 1 -Ck 4 represent 4 gate timing sequence signal lines respectively. The waveform of the gate timing sequence signals of the gate timing sequence signal lines Ck 1 , Ck 2 , Ck 3 , Ck 4 is shown in FIG. 4 . Both ends of the first row of gate control line and the sixth row of gate control line among the 6 rows of gate control lines are connected with gate driving units 1 ; except the first row of gate control line and the sixth row of gate control line, one end of other rows (i.e., rows L 2 -L 5 ) of gate control lines is connected to a compensation unit 2 and the other end is connected to a gate driving unit 1 , and the ends at the same side of two adjacent rows of gate control lines among said other rows (i.e., rows L 2 -L 5 ) of gate control lines are connected to gate driving units 1 and compensation units 2 respectively. The compensation unit 2 connected to one end of any row of gate control line among said other rows (i.e., rows L 2 -L 5 ) of gate control lines is connected to the output terminals of the gate driving units 1 connected to the adjacent previous and next rows of gate control lines, and the compensation unit 2 drives the gate control line connected thereto based on the output of the gate driving units 1 connected to the previous and next rows of gate control lines.

The compensation unit 2 comprises a first TFT T 1 and a second TFT T 2 ; the source of the first TFT T 1 is connected to the source of the second TFT T 2 and serves as a gate timing sequence signal input terminal of the compensation unit 2 ; the drain of the first TFT T 1 is connected to the drain of the second TFT T 2 and serves as a driving output terminal of the compensation unit 2 ; the gate of the first TFT T 1 serves as a first control terminal of the compensation unit 2 ; the gate of the second TFT T 2 serves as a second control terminal of the compensation unit 2 . The gate timing sequence signal input terminal of the compensation unit 2 is connected to a gate timing sequence signal line, the driving output terminal of the compensation unit 2 is connected to the gate control line, the first control terminal of the compensation unit 2 is connected to the output terminal of one of the two gate driving units 1 , and the second control terminal of the compensation unit 2 is connected to the output terminal of the other one of the two gate driving units 1 .

Now, the operational principle of the compensation unit 2 will be described by taking the compensation unit 2 at the left end of row L 2 as an example. As shown in FIG. 3 and FIG. 4 , because the gate timing sequence signal input terminal of the compensation unit 2 is connected to the gate timing sequence signal line Ck 2 in the second row, the driving output terminal is connected to the second row of gate control line, the first control terminal is connected to the output terminal of the gate driving unit 1 at the left end of the first row, and the second control terminal is connected to the output terminal of the gate driving unit 1 at the left end of the third row, the gate driving unit 1 at the left end of the first row and the gate control unit 1 at the left end of the third row can control the ON/OFF of T 1 and T 2 alternately, such that Ck 2 is connected to the second row of gate control line to drive the second row of gate control line.

In the above embodiments, the space occupied by the gate drivers is dramatically reduced and the product size of the display apparatus is effectively reduced by changing the conventional structure of dual gate driving units 1 for two sides to a new structure of a single gate driving unit 1 for two sides plus a compensation unit 2 .

The above descriptions are only for describing the embodiments of the present disclosure, but not for limiting the present disclosure in any way. Those skilled in related arts can make various changes and variations to the embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent technical solutions also belong to the scope of the present disclosure. The protection scope of the present disclosure should be defined by the claims.