Light detection device having a semiconductor light detection element, a mounting substrate, a glass substrate and a plurality of through-hole electrodes electrically connected to quenching resistors

The present invention relates to a light detection device.

There is a known photodiode array (semiconductor light detection element) having a plurality of avalanche photodiodes operating in Geiger mode, quenching resistors connected in series to the respective avalanche photodiodes, and signal lines to which the quenching resistors are connected in parallel (e.g., cf. Patent Literature 1). In this photodiode array, when an avalanche photodiode forming a pixel detects a photon to induce Geiger discharge, a pulsed signal is obtained by action of the quenching resistor connected to the avalanche photodiode. Each avalanche photodiode counts a photon. For this reason, with incidence of multiple photons at the same timing, we can also find out the number of incident photons in accordance with an output charge amount or signal intensity of all output pulses.

Patent Literature

Patent Literature 1: Japanese Patent Application Laid-Open Publication No. 2011-003739

Technical Problem

In the above-described semiconductor light detection element, the quenching resistors are connected in parallel to the signal lines, and for this reason, the avalanche photodiodes are also connected in parallel to each other. In the case of the semiconductor light detection element having the plurality of avalanche photodiodes connected in parallel, distances of interconnections (signal lines) for guiding signals output from the respective avalanche photodiodes (which will be referred to hereinafter as “interconnection distances”) can be different among pixels (avalanche photodiodes). The different interconnection distances among pixels lead to different temporal resolutions among pixels due to influence of resistances and capacitances of the interconnections.

It is an object of the present invention to provide a light detection device capable of achieving further improvement in temporal resolution, while suppressing the difference of temporal resolutions among pixels.

Solution to Problem

The present invention provides a light detection device comprising: a semiconductor light detection element having a semiconductor substrate including first and second principal surfaces opposed to each other; a mounting substrate arranged as opposed to the semiconductor light detection element and having a third principal surface opposed to the second principal surface of the semiconductor substrate; and a glass substrate arranged as opposed to the semiconductor light detection element and having a fourth principal surface opposed to the first principal surface of the semiconductor substrate, wherein the semiconductor light detection element includes a plurality of avalanche photodiodes operating in Geiger mode and formed in the semiconductor substrate, quenching resistors connected in series to the respective avalanche photodiodes and arranged on the first principal surface side of the semiconductor substrate, and a plurality of through-hole electrodes electrically connected to the quenching resistors and formed so as to penetrate the semiconductor substrate from the first principal surface side to the second principal surface side, wherein the mounting substrate includes a plurality of first electrodes arranged corresponding to the respective through-hole electrodes on the third principal surface side, and a signal processing unit electrically connected to the plurality of first electrodes and configured to process output signals from the respective avalanche photodiodes, wherein the through-hole electrodes and the first electrodes are electrically connected through bump electrodes, and wherein a side surface of the semiconductor substrate and a side surface of the glass substrate are flush with each other.

In the present invention, the plurality of through-hole electrodes electrically connected to the quenching resistors and penetrating the semiconductor substrate from the first principal surface side to the second principal surface side are formed in the semiconductor substrate of the semiconductor light detection element, and the through-hole electrodes of the semiconductor light detection element and the first electrodes of the mounting substrate are electrically connected through the bump electrodes. This configuration allows the interconnection distances of the respective pixels to be set extremely short and thus allows values thereof to be equalized without significant variation. Therefore, it remarkably suppresses the influence of resistances and capacitances of the interconnections and thus achieves further improvement in temporal resolution.

In the present invention, the glass substrate arranged as opposed to the semiconductor light detection element enhances the mechanical strength of the semiconductor substrate. Since the side surface of the semiconductor substrate and the side surface of the glass substrate are flush with each other, dead space is reduced.

In the present invention, a principal surface of the glass substrate opposed to the fourth principal surface may be flat. In this case, it is extremely easy to perform installation of a scintillator onto the glass substrate.

In the present invention, the through-hole electrodes may be located in regions among the avalanche photodiodes. In this case, it is feasible to prevent reduction in fill factor in each pixel.

In the present invention, the semiconductor light detection element may further include second electrodes electrically connected to the corresponding through-hole electrodes and arranged on the second principal surface side of the semiconductor substrate, and the first electrodes and the second electrodes may be connected through the bump electrodes. In this case, it is feasible to certainly implement connection between the first electrodes and the second electrodes through the bump electrodes.

In the present invention, each avalanche photodiode may have: the semiconductor substrate of a first conductivity type a first semiconductor region of a second conductivity type formed on the first principal surface side of the semiconductor substrate; a second semiconductor region of the second conductivity type formed in the first semiconductor region and having a higher impurity concentration than the first semiconductor region; and a third electrode arranged on the first principal surface side of the semiconductor substrate and electrically connecting the second semiconductor region and the quenching resistor, and the second electrode may be formed on a region corresponding to the second semiconductor region on the second principal surface. In this case, it is feasible to set the size of the second electrode relatively large. This configuration allows us to more certainly implement the connection between the first electrodes and the second electrodes through the bump electrodes and to enhance the mechanical strength of the connection.

In the present invention, a plurality of quenching resistors may be electrically connected to the through-hole electrode. In this case, the through-hole electrode is shared among pixels, which reduces the number of through-hole electrodes formed in the semiconductor substrate. This configuration suppresses reduction in mechanical strength of the semiconductor substrate.

In the present invention, interconnection distances from the respective avalanche photodiodes through the corresponding quenching resistors to the through-hole electrode may be equal. In this case, reduction in temporal resolution is prevented even in the configuration wherein the through-hole electrode is shared among pixels.

Advantageous Effect of Invention

The present invention provides the light detection device capable of achieving further improvement in temporal resolution, while suppressing the difference of temporal resolutions among pixels.

FIG. 1 is a schematic perspective view showing a light detection device according to an embodiment of the present invention.

FIG. 2 is a drawing for explaining a sectional configuration of the light detection device according to the present embodiment.

FIG. 3 is a schematic plan view of a semiconductor light detection element.

FIG. 4 is a schematic plan view of the semiconductor light detection element.

FIG. 5 is a circuit diagram of the light detection device.

FIG. 6 is a schematic plan view of a mounting substrate.

FIG. 7 is a drawing for explaining a manufacturing process of the light detection device according to the present embodiment.

FIG. 8 is a drawing for explaining the manufacturing process of the light detection device according to the present embodiment.

FIG. 9 is a drawing for explaining the manufacturing process of the light detection device according to the present embodiment.

FIG. 10 is a drawing for explaining the manufacturing process of the light detection device according to the present embodiment.

FIG. 11 is a drawing for explaining the manufacturing process of the light detection device according to the present embodiment.

FIG. 12 is a drawing for explaining the manufacturing process of the light detection device according to the present embodiment.

FIG. 13 is a drawing for explaining the manufacturing process of the light detection device according to the present embodiment.

FIG. 14 is a schematic plan view of a semiconductor light detection element.

The preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the description the same elements or elements with the same functionality will be denoted by the same reference signs, without redundant description.

A configuration of the light detection device 1 according to the present embodiment will be described with reference to FIGS. 1 to 6 . FIG. 1 is a schematic perspective view showing the light detection device according to the present embodiment. FIG. 2 is a drawing for explaining a sectional configuration of the light detection device according to the present embodiment. FIGS. 3 and 4 are schematic plan views of a semiconductor light detection element. FIG. 5 is a circuit diagram of the light detection device. FIG. 6 is a schematic plan view of a mounting substrate.

The light detection device 1 , as shown in FIGS. 1 and 2 , has a semiconductor light detection element 10 , a mounting substrate 20 , and a glass substrate 30 . The mounting substrate 20 is arranged as opposed to the semiconductor light detection element 10 . The glass substrate 30 is arranged as opposed to the semiconductor light detection element 10 . The semiconductor light detection element 10 is arranged between the mounting substrate 20 and the glass substrate 30 .

The semiconductor light detection element 10 consists of a photodiode array PDA. The photodiode array PDA has a semiconductor substrate 1 N of a rectangular shape on the plan view. The semiconductor substrate 1 N includes a principal surface 1 Na and a principal surface 1 Nb opposed to each other. The semiconductor substrate 1 N is an N-type (first conductivity type) semiconductor substrate comprised of Si.

The photodiode array PDA includes a plurality of avalanche photodiodes APD formed in the semiconductor substrate 1 N. Connected in series to each avalanche photodiode APD, as also shown in FIG. 3 , is a quenching resistor R 1 . One avalanche photodiode APD constitutes one pixel in the photodiode array PDA. While each avalanche photodiode APD is connected in series to the corresponding quenching resistor R 1 , all the avalanche photodiodes are connected in parallel and a reverse bias voltage is applied thereto from a power supply. Output currents from the avalanche photodiodes APD are detected by a below-described signal processing unit SP. FIG. 3 is drawn without illustration of an insulating layer L 1 shown in FIG. 2 , for clarity of structure.

Each individual avalanche photodiode APD has a P-type (second conductivity type) first semiconductor region 1 PA and a P-type (second conductivity type) second semiconductor region 1 PB. The first semiconductor region 1 PA is formed on the principal surface 1 Na side of the semiconductor substrate 1 N. The second semiconductor region 1 PB is formed in the first semiconductor region 1 PA and has a higher impurity concentration than the first semiconductor region 1 PA. The planar shape of the second semiconductor region 1 PB is, for example, a polygonal shape (octagon in the present embodiment). The depth of the first semiconductor region 1 PA is larger than that of the second semiconductor region 1 PB.

The semiconductor substrate 1 N has N-type (first conductivity type) semiconductor regions 1 PC. The semiconductor regions 1 PC are formed on the principal surface 1 Na side of the semiconductor substrate 1 N. The semiconductor regions 1 PC prevent PN junctions formed between the N-type semiconductor substrate 1 N and the P-type first semiconductor regions 1 PA from being exposed to through holes TH in which below-described through-hole electrodes TE are arranged. The semiconductor regions 1 PC are formed at positions corresponding to the through holes TH (through-hole electrodes TE).

Each avalanche photodiode APD, as shown in FIG. 3 , has an electrode E 1 and an electrode E 3 . The electrode E 1 and electrode E 3 are arranged each on the principal surface 1 Na side of the semiconductor substrate 1 N. The electrode E 1 is electrically connected to the second semiconductor region 1 PB. The electrode E 3 is arranged through the insulating layer L 1 on the semiconductor substrate 1 N outside the second semiconductor region 1 PB, when viewed from the principal surface 1 Na side. The first semiconductor region 1 PA is electrically connected through the second semiconductor region 1 PB to the electrode E 1 .

The avalanche photodiode APD, as also shown in FIG. 4 , has an electrode (not shown) electrically connected to the semiconductor substrate 1 N, an electrode E 5 , and an electrode E 7 connected to the electrode E 5 , each of which is arranged on the principal surface 1 Nb side of the semiconductor substrate 1 N. The electrode E 5 is arranged through an insulating layer L 2 on the semiconductor substrate 1 N outside the second semiconductor region 1 PB, when viewed from the principal surface 1 Nb side. The electrode E 7 is arranged through the insulating layer L 2 on the semiconductor substrate 1 N overlapping with the second semiconductor region 1 PB, when viewed from the principal surface 1 Nb side. The electrode E 7 is arranged on a region corresponding to the second semiconductor region 1 PB on the principal surface 1 Nb. FIG. 4 is drawn without illustration of a passivation film PF shown in FIG. 2 , for clarity of structure.

The photodiode array PDA has the quenching resistors R 1 for the respective individual avalanche photodiodes APD. Each quenching resistor R 1 is arranged through the insulating layer L 1 on the semiconductor substrate 1 N outside the second semiconductor region 1 PB. The quenching resistor R 1 is arranged on the principal surface 1 Na side of the semiconductor substrate 1 N. The quenching resistor R 1 has one end connected to the electrode E 1 and the other end connected to the electrode E 3 .

The photodiode array PDA includes a plurality of through-hole electrodes TE. The through-hole electrodes TE are provided for the respective individual avalanche photodiodes APD. The through-hole electrodes TE are formed so as to penetrate the semiconductor substrate 1 N from the principal surface 1 Na side to the principal surface 1 Nb side. The through-hole electrodes TE are arranged in the through holes TH penetrating the semiconductor substrate 1 N. The insulating layer L 2 is also formed in the through holes TH. Therefore, the through-hole electrodes TE are arranged through the insulating layer L 2 in the through holes TH.

The through-hole electrode TE has one end connected to the electrode E 3 and the other end connected to the electrode E 5 . The quenching resistor R 1 is electrically connected through the electrode E 3 , the through-hole electrode TE, and the electrode E 5 to the electrode E 7 .

The through-hole electrode TE is arranged in a region among avalanche photodiodes APD on the plan view. In the present embodiment, the avalanche photodiodes APD are two-dimensionally arrayed in a matrix of M rows in a first direction and N columns in a second direction perpendicular to the first direction (M and N are natural numbers). The through-hole electrode TE is formed in the region surrounded by four avalanche photodiodes APD. Since the through-hole electrodes TE are provided for the respective avalanche photodiodes APD, they are two-dimensionally arrayed in the matrix of M rows in the first direction and N columns in the second direction.

The quenching resistors R 1 have the resistivity higher than that of the electrodes E 1 to which the quenching resistors R 1 are connected. The quenching resistors R 1 are comprised, for example, of polysilicon. An applicable method for forming the quenching resistors R 1 is a CVD

(Chemical Vapor Deposition) Process.

The electrodes E 1 , E 3 , E 5 , E 7 and the through-hole electrodes TE are comprised of metal such as aluminum. When the semiconductor substrate is made of Si, a frequently used electrode material is AuGe/Ni, as well as aluminum. Although it depends on process design, the electrodes E 5 , electrodes E 7 , and through-hole electrodes TE can be integrally formed. An applicable method for forming the electrodes E 1 , E 3 , E 5 , E 7 and the through-hole electrodes TE is a sputtering process.

A P-type impurity to be used in the case using Si is a group 3 element such as B and an N-type impurity to be used in the same case is a group 5 element such as N, P, or As. If the semiconductor light detection element is constructed by interchanging the N type and P type of semiconductor conductivity types with each other, the element can also function well. An applicable method for adding these impurities is a diffusion process or an ion implantation process.

A material available for the insulating layers L 1 , L 2 is SiO 2 or SiN. An applicable method for forming the insulating layers L 1 , L 2 in the case of the insulating layers L 1 , L 2 being made of SiO 2 is a thermal oxidation process or a sputtering process.

In the case of the above-described structure, the PN junctions are formed between the N-type semiconductor substrate 1 N and the P-type first semiconductor regions 1 PA, thereby forming the avalanche photodiodes APD. The semiconductor substrate 1 N is electrically connected to the electrode (not shown) formed on the back surface of the substrate 1 N and the first semiconductor regions 1 PA are connected through the second semiconductor regions 1 PB to the electrodes E 1 . The quenching resistor R 1 is connected in series to the avalanche photodiode APD (cf. FIG. 5 ).

In the photodiode array PDA, the individual avalanche photodiodes APD are made to operate in Geiger mode. In Geiger mode, a backward voltage (reverse bias voltage) larger than the breakdown voltage of the avalanche photodiodes APD is applied between anodes and cathodes of the avalanche photodiodes APD. A (−) potential V 1 is applied to the anodes and a (+) potential V 2 to the cathodes. The polarities of these potentials are relative ones, one of which can be the ground potential.

The anodes are the P-type first semiconductor regions 1 PA while the cathodes are the N-type semiconductor substrate 1 N. When light (photon) is incident into the avalanche photodiode APD, photoelectric conversion is effected inside the substrate to generate photoelectrons. Avalanche multiplication is effected in a region around the PN junction interface of the first semiconductor region 1 PA and a group of multiplied electrons flow toward the electrode formed on the back surface of the semiconductor substrate 1 N. Namely, with incidence of light (photon) into one pixel (avalanche photodiode APD) in the semiconductor light detection element 10 (photodiode array PDA), it is subjected to multiplication to be taken out as signal from the electrode E 7 .

The mounting substrate 20 , as also shown in FIGS. 2 and 13 , has a principal surface 20 a and a principal surface 20 b opposed to each other. The mounting substrate 20 has a rectangular shape on the plan view. The principal surface 20 a is opposed to the principal surface 1 Nb of the semiconductor substrate 1 N. The mounting substrate 20 includes a plurality of electrodes E 9 arranged on the principal surface 20 a side. The electrodes E 9 are arranged corresponding to the through-hole electrodes TE, as shown in FIG. 2 . Specifically, the electrodes E 9 are arranged on respective regions opposed to the electrodes E 7 , on the principal surface 20 a.

The side surfaces 1 Nc of the semiconductor substrate 1 N and the side surfaces 20 c of the mounting substrate 20 are flush with each other, as shown in FIGS. 1 and 2 . On the plan view, the outer edge of the semiconductor substrate 1 N and the outer edge of the mounting substrate 20 are coincident.

The electrodes E 7 and the electrodes E 9 are connected through bump electrodes BE. This makes the through-hole electrodes TE electrically connected through the electrodes E 5 , the electrodes E 7 , and the bump electrodes BE to the electrodes E 9 . Then, the quenching resistors R 1 are electrically connected to the electrodes E 9 through the electrodes E 3 , through-hole electrodes TE, electrodes E 5 , electrodes E 7 , and bump electrodes BE. The electrodes E 9 are also comprised of metal such as aluminum as the electrodes E 1 , E 3 , E 5 , E 7 and the through-hole electrodes TE are. The electrode material to be used may be, for example, AuGe/Ni, as well as aluminum. The bump electrodes BE are comprised, for example, of solder.

The mounting substrate 20 has a signal processing unit SP, as also shown in FIG. 5 . The mounting substrate 20 constitutes ASIC (Application Specific Integrated Circuit). Each electrode E 9 is electrically connected to the signal processing unit SP through an interconnection (not shown) formed in the mounting substrate 20 . The output signals from the respective avalanche photodiodes APD (semiconductor light detection element 10 ) are fed to the signal processing unit SP and then the signal processing unit SP processes the output signals from the respective avalanche photodiodes APD. The signal processing unit SP includes a CMOS circuit to convert the output signals from the respective avalanche photodiodes APD into digital pulses. The mounting substrate 20 is configured so as to include a circuit for recording time information, corresponding to each pixel (avalanche photodiode APD). The circuit to be used herein for recording time information is a time-to-digital converter (TDC: Time to Digital Convertor), or, a time voltage converter (TAC: Time to Amplitude Convertor), or the like. Because of this configuration, the difference of interconnection distances in the mounting substrate 20 does not affect the temporal resolution.

Passivation films PF with openings formed at the positions corresponding to the bump electrodes BE are arranged on the principal surface 1 Nb side of the semiconductor substrate 1 N and on the principal surface 20 a side of the mounting substrate 20 . The passivation films PF are comprised, for example, of SiN. An applicable method for forming the passivation films PF is a CVD process.

The glass substrate 30 has a principal surface 30 a and a principal surface 30 b opposed to each other. The glass substrate 30 has a rectangular shape on the plan view. The principal surface 30 a is opposed to the principal surface 1 Nb of the semiconductor substrate 1 N. The principal surface 30 b is flat. In the present embodiment, the principal surface 30 a is also flat. The glass substrate 30 and the semiconductor light detection element 10 are optically connected to each other with an optical adhesive OA. The glass substrate 30 may be directly formed on the semiconductor light detection element 10 .

Although illustration is omitted, a scintillator is optically connected to the principal surface 30 b of the glass substrate 30 with an optical adhesive. Scintillation light from the scintillator passes through the glass substrate 30 to enter the semiconductor light detection element 10 .

The side surfaces 1 Nc of the semiconductor substrate 1 N and the side surfaces 30 c of the glass substrate 30 are flush with each other, as also shown in FIG. 1 . On the plan view, the outer edge of the semiconductor substrate 1 N and the outer edge of the glass substrate 30 are coincident.

Next, a manufacturing process of the above-described light detection device 1 will be described with reference to FIGS. 7 to 13 . FIGS. 7 to 13 are drawings for explaining the manufacturing process of the light detection device according to the present embodiment.

First, the semiconductor substrate 1 N in which the portions corresponding to the photodiode array PDA (first semiconductor regions 1 PA, second semiconductor regions 1 PB, insulating layer L 1 , quenching resistors R 1 , electrodes E 1 , and electrodes E 3 ) are formed is prepared (cf. FIG. 7 ). The semiconductor substrate 1 N is prepared in the form of a semiconductor wafer wherein there are a plurality of portions corresponding to photodiode arrays PDA formed.

Next, the glass substrate 30 is bonded to the prepared semiconductor substrate 1 N through the optical adhesive OA (cf. FIG. 8 ). This process results in optically connecting the glass substrate 30 and the semiconductor light detection element 10 to each other. The glass substrate 30 is also prepared in the form of a glass substrate preform including a plurality of glass substrates 30 as the semiconductor substrate 1 N is.

Next, the semiconductor substrate 1 N is thinned from the principal surface 1 Nb side (cf. FIG. 9 ). An applicable method for thinning the semiconductor substrate 1 N is a mechanical polishing process or a chemical polishing process.

Next, the through holes TH for arranging the through-hole electrodes TE are formed on the semiconductor substrate 1 N (cf. FIG. 10 ). An applicable method for forming the through holes TH is one suitably selected from a dry etching process and a wet etching process.

Next, portions corresponding to the photodiode array PDA (through-hole electrodes TE, electrodes E 5 , and electrodes E 7 ) are formed on the semiconductor substrate 1 N in which the through-hole electrodes TH have been formed (cf. FIG. 11 ).

Next, the passivation film PF with the openings formed at the positions corresponding to the bump electrodes BE is formed on the principal surface 1 Nb side of the semiconductor substrate 1 N, and then the bump electrodes BE are formed (cf. FIG. 12 ). This process completes a configuration wherein the semiconductor light detection element 10 and the glass substrate 30 are arranged as opposed. Prior to the formation of the bump electrodes BE, UBM (Under Bump Metal) is formed in regions exposed from the passivation film PF on the electrodes E 7 . The UBM is comprised of a material that achieves superior electrical and physical connection with the bump electrodes BE. An applicable method for forming the UBM is an electroless plating process. An applicable method for forming the bump electrodes BE is a technique for mounting solder balls or a printing process.

Next, the semiconductor light detection element 10 with the glass substrate 30 arranged thereon and the mounting substrate 20 prepared separately are bump-connected to each other (cf. FIG. 13 ). This process results in obtaining a configuration wherein the mounting substrate 20 is arranged as opposed to the semiconductor light detection element 10 to which the glass substrate 30 is arranged as opposed. In the mounting substrate 20 , the bump electrodes BE are formed at the positions corresponding to the electrodes E 9 on the principal surface 20 a side. The mounting substrate 20 is also prepared in the form of a semiconductor wafer wherein a plurality of mounting substrates 20 are formed.

Next, a laminate body consisting of the glass substrates 30 (glass substrate preform), the semiconductor light detection elements 10 (semiconductor wafer), and the mounting substrates 20 (semiconductor wafer) is cut by dicing. This makes the side surfaces 1 Nc of the semiconductor substrate 1 N, the side surfaces 20 c of the mounting substrate 20 , and the side surfaces 30 c of the glass substrate 30 flush with each other. The individual light detection devices 1 are obtained through these processes.

In the present embodiment, as described above, the through-hole electrodes TE electrically connected to the quenching resistors R 1 and penetrating the semiconductor substrate 1 N from the principal surface 1 Na side to the principal surface 1 Nb side are formed in the semiconductor substrate 1 N of the semiconductor light detection element 10 (photodiode array PDA). The through-hole electrodes TE of the semiconductor light detection element 10 and the electrodes E 9 of the mounting substrate 20 are electrically connected through the bump electrodes BE. This configuration allows the interconnection distances from the respective pixels (avalanche photodiodes APD) to be set extremely short, and allows values thereof to be equalized without significant variation. Therefore, it remarkably suppresses the influence of resistances and capacitances of the interconnections from the respective pixels and thus achieves further improvement in temporal resolution.

In the present embodiment, the glass substrate 30 arranged as opposed to the semiconductor light detection element 10 enhances the mechanical strength of the semiconductor substrate 1 N. Particularly, it is extremely effective in the case where the semiconductor substrate 1 N is thinned.

The side surfaces 1 Nc of the semiconductor substrate 1 N and the side surfaces 30 c of the glass substrate 30 are flush with each other. This configuration reduces dead space. The side surfaces 1 Nc of the semiconductor substrate 1 N and the side surfaces 20 c of the mounting substrate 20 are also flush with each other. This configuration further reduces dead space.

The principal surface 30 b of the glass substrate 30 is flat. This configuration makes it extremely easy to perform the installation of the scintillator onto the glass substrate 30 .

In the present embodiment, the through-hole electrodes TE are located in the regions among the avalanche photodiodes APD. This configuration prevents reduction in fill factor in each pixel.

The semiconductor light detection element 10 includes the electrodes E 7 electrically connected to the corresponding through-hole electrodes TE and arranged on the principal surface 1 Nb side of the semiconductor substrate 1 N and, the electrodes E 7 and the electrodes E 9 are connected through the bump electrodes BE. This configuration allows the connection between the electrodes E 7 and the electrodes E 9 through the bump electrodes BE to be implemented with certainty.

Each avalanche photodiode APD has the semiconductor substrate 1 N, the first semiconductor region 1 PA, the second semiconductor region 1 PB, and the electrode E 1 electrically connecting the second semiconductor region 1 PB and the quenching resistor R 1 , and the electrode E 7 is formed on the region corresponding to the second semiconductor region 1 PB on the principal surface 1 Nb. This configuration allows us to set the size of the electrode E 7 relatively large. As a consequence of this, it is feasible to more certainly implement the connection between the electrode E 7 and the electrode E 9 through the bump electrode BE and to enhance the mechanical strength of the connection.

The above described the preferred embodiment of the present invention, and it should be noted that the present invention is by no means limited to the aforementioned embodiment and can be modified in many ways without departing from the scope and spirit of the invention.

One quenching resistor R 1 is electrically connected to one through-hole electrode TE, but they do not always have to be limited to this configuration. As shown in FIG. 14 , a plurality of quenching resistors (e.g., four quenching resistors) 1 R may be electrically connected to one through-hole electrode TE. In this case, the through-hole electrode TE is shared among pixels, which decreases the number of through-hole electrodes TE formed in the semiconductor substrate 1 N. This configuration suppresses reduction in mechanical strength of the semiconductor substrate 1 N. The number of quenching resistors electrically connected to one through-hole electrode TE does not have to be limited to “4” but may be “3” or less, or may be “5” or more.

When a plurality of quenching resistors R 1 are electrically connected to one through-hole electrode TE, the interconnection distances from the respective avalanche photodiodes APD through the quenching resistors R 1 to the through-hole electrode TE are preferably equal. In this case, the reduction in temporal resolution is also prevented in the configuration wherein the through-hole electrode TE is shared among pixels.

The shapes of the first and second semiconductor regions 1 PA, 1 PB do not have to be limited to the aforementioned shapes but may be other shapes (e.g., a circular shape or the like). The number (the number of rows and the number of columns) and arrangement of the avalanche photodiodes APD (second semiconductor regions 1 PB) do not have to be limited to those described above.

The present invention is applicable to the light detection devices for detecting weak light.

1 light detection device; 1 N semiconductor substrate; 1 Na, 1 Nb principal surfaces; 1 Nc side surface; 1 PA first semiconductor region; 1 PB second semiconductor region; 10 semiconductor light detection element; 20 mounting substrate; 20 a , 20 b principal surfaces; 20 c side surface; 30 glass substrate; 30 a , 30 b principal surfaces; 30 c side surface; APD avalanche photodiode; BE bump electrode; E 1 , E 3 , E 5 , E 7 , E 9 electrodes; PDA photodiode array; R 1 quenching resistor; SP signal processing unit; TE through-hole electrode.