Array substrate, display device and control method thereof

Embodiments of the present invention relate to an array substrate, a display device and a control method thereof.

With the continuous development of display technology, liquid crystal displays (LCDs) have dominated the flat-panel display field. Pixels in an LCD are arranged in an array; each pixel is generally divided into three pixel units, namely red, green and blue (RGB) pixel units; and each pixel unit is cooperatively controlled by a gate line and a data line.

The number of gate lines in the LCD is equal to the number of pixel rows. For instance, in a common half-size video graphics array (HVGA) type LCD, the number of pixels is 480×320, and therefore 480 gate lines must be provided. The gate lines must be connected to a gate line driver from a side of a display area. In order to reduce the width of the gate lines, a double-side routing process is usually adopted, namely lines are provided on two sides of the display area; 240 gate lines are disposed on each side; and hence a frame width of 2.5 mm is needed for performing a wiring process.

An alternate routing process may be further provided on the basis of the double routing process, namely two sides of the display area are respectively configured in two layers for wiring, and hence the frame width can be reduced to about 1.7 mm. But in this way, because adjacent wirings have resistance difference therebetween, the defect of horizontal lines (H-line) will occur in the display process of the LCD, and hence the display effect can be disadvantageously affected.

Embodiments of the present invention provide an array substrate, a display device and a control method thereof, which can solve the problem that the display effect is affected by H-lines in a narrow-frame LCD.

In one aspect, the present invention provides an array substrate, which comprises a plurality of gate lines and a plurality of data lines which are intercrossed to define pixels arranged in arrays; the plurality of gate lines include n gate line groups and n+1 main gate lines; each gate line group includes a first gate line and a second gate line which are adjacent to each other; the first gate line is provided corresponding to a first pixel group, and the second gate line is provided corresponding to a second pixel group; the first pixel group includes a plurality of first pixel units arranged in a row; each first pixel unit includes a first transistor; the second pixel group includes a plurality of second pixel units arranged in a row; the second pixel unit includes a second transistor and a switching element; both the first gate line and the second gate line in the i th gate line group are connected with the i th main gate line; a gate electrode of the first transistor in the first pixel unit corresponding to the first gate line in the i th gate line group is connected with the first gate line; a source electrode of the first transistor is connected with a corresponding data line; a drain electrode of the first transistor is connected with the pixel unit; a gate electrode of the second transistor in the second pixel unit corresponding to the second gate line in the i th gate line group is connected with one end of the switching element in the pixel unit; a source electrode of the second transistor is connected with a corresponding data line; a drain electrode of the second transistor is connected with a pixel electrode of the pixel unit; and another end of the switching element in the second pixel unit corresponding to the second gate line in the i th gate line group is connected with a main gate line in the (i+1) th row or any gate line in the (i+1) th gate line group and configured to control on/off operation of the second transistor in the second pixel unit in the i th gate line group, in which both i and n are integers, and 1≦i≦n.

For instance, the switching element is a thin-film transistor (TFT); a gate electrode of the TFT is connected with the second gate line of the i th gate line group; a source electrode of the TFT is connected with the main gate line in the (i+1) th row or any gate line in the (i+1) th gate line group; and a drain electrode of the TFT is connected with the gate electrode of the second transistor in the pixel unit in which the TFT is disposed.

Moreover, for instance, the TFT is an N-type TFT.

For instance, the (n+1) th main gate line is connected with or merged to the first main gate line.

In another aspect, the present invention provides a display device, which comprises the foregoing array substrate. The gate lines in the array substrate respectively control the rows of pixel units in the display device.

In still another aspect, the present invention provides a control method of the display device: in a scanning process of the i th main gate line, in a first time period, the i th main gate line and the (i+1) th main gate line are at a high level, and meanwhile data signals of the second pixel group corresponding to the second gate line in the i th gate line group are outputted by the data lines in the display device; and in a second time period, the i th main gate line is at a high level, and meanwhile data signals of the first pixel group corresponding to the first gate line in the i th gate line group are outputted by the data lines in the display device, in which both i and n are integers, and 1≦i≦n.

The array substrate provided in the embodiment of the present invention comprises n gate line groups, wherein each gate line group includes two adjacent gate lines, namely 2n gate lines are provided in total; but only n+1 main gate lines are required to be disposed on a side of a display area, so that the number of routings on the side of the display area is almost a half of the total amount of the gate lines; and hence the frame width of the LCD can be reduced and the poor display effect of H-lines cannot occur.

Simple description will be given below to the accompanying drawings of the embodiments to provide a more clear understanding of the technical proposals of the embodiments of the present invention. It will be obvious to those skilled in the art that the drawings described below only involve some embodiments of the present invention but are not intended to limit the present invention.

FIG. 1 is a schematic diagram of an array substrate provided by a first embodiment of the present invention;

FIG. 2 is a timing chart of a control method provided in the first embodiment of the present invention;

FIG. 3 is a schematic diagram of an array substrate provided by a second embodiment of the present invention; and

FIG. 4 is a timing chart of a control method provided in the second embodiment of the present invention.

For more clear understanding of the objectives, technical proposals and advantages of the embodiments of the present invention, clear and complete description will be given below to the technical proposals of the embodiments of the present invention with reference to the accompanying drawings of the embodiments of the present invention. It will be obvious to those skilled in the art that the preferred embodiments are only partial embodiments of the present invention but not all the embodiments. All the other embodiments obtained by those skilled in the art without creative efforts on the basis of the embodiments of the present invention illustrated shall fall within the scope of protection of the present invention.

Unless otherwise defined, the technical or scientific terms used herein have normal meanings understood by those skilled in the art. The words “first”, “second” and the like used in the description and the claims of the patent application of the present invention do not indicate sequence, amount or importance but are only used for distinguishing different components. Similarly, the words “a”, “an”, “the” and the like also do not indicate the amount but only indicate at least one. The word “comprise”, “include” or the like only indicates that an element or a component before the word contains elements or components listed after the word and equivalents thereof, not excluding other elements or components. The words “coupled”, “connected” and the like are not limited to physical or mechanical connection but may include electrical connection, either directly or indirectly. The words “on”, “under”, “left”, “right” and the like only indicate the relative position relationship which is correspondingly changed when the absolute position of a described object is changed.

As illustrated in FIG. 1 , the array substrate provided in the embodiment of the present invention may be applied in an LCD. The array substrate comprises a plurality of gate lines and a plurality of data lines D; the plurality of gate lines include n gate line groups and n+1 main gate lines G 1 to Gn+1; the gate lines and the data lines are intercrossed each other to define a plurality of pixels arranged in an array; each main gate line is connected to a gate line driver of the LCD; each gate line group includes a first gate line and a second gate line which are adjacent to each other; the first gate line is provided corresponding to a first pixel group; the second gate line is provided corresponding to a second pixel group; the first pixel group includes a plurality of first pixel units arranged in a row; each first pixel unit includes a first transistor T 1 which is connected to a pixel electrode of the first pixel unit and controls whether to charge the pixel electrode; the second pixel group includes a plurality of second pixel units arranged in a row; the second pixel unit includes a second transistor T 2 and a switching element T 3 ; and the transistor T 2 is connected to a pixel electrode of the second pixel unit and controls whether to charge the pixel electrode. As illustrated in FIG. 1 , two adjacent pixel units in each column of the pixel units of the LCD are correspondingly provided with the transistors T 1 , T 2 and a switching element T 3 and each connected with the data line D corresponding to the pixel column respectively.

Both the first gate line and the second gate line in the i th gate line group are connected with the i th main gate line Gi. The first gate line and the second gate line in the first gate line group are respectively the first row of gate line g 1 and the second row of gate line g 2 in the LCD; the first gate line and the second gate line in the second gate line group are respectively the third row of gate line g 3 and the fourth row of gate line g 4 in the LCD, and so on. If the array substrate comprises n gate line groups, the LCD comprises 2n rows of gate lines.

In the first pixel unit corresponding to the first gate line in the i th gate line group, a gate electrode of the transistor T 1 is connected with the first gate line; a source electrode of the T 1 is connected with a corresponding data line D; and a drain electrode of the T 1 is connected with a corresponding pixel electrode (a square portion in the figure).

In the second pixel unit corresponding to the second gate line in the i th gate line group, a gate electrode of the transistor T 2 is connected with one end of the switching element T 3 in the pixel unit; a source electrode of the T 2 is connected with a corresponding data line D; and a drain electrode of the T 2 is connected with a pixel electrode of the pixel unit.

In the second pixel unit corresponding to the second gate line in the i th gate line group, one end of the switching element T 3 is connected with (i+1) th main gate line or any gate line in the (i+1) th gate line group, and another end is connected with the gate electrode of the transistor T 2 and configured to control the on/off operation of the T 2 in the second pixel unit of the i th gate line group.

For instance, the switching element T 3 is a TFT and is preferably an N-type TFT. The connection mode of the switching element T 3 is, for instance, as follows: a gate electrode of the element T 3 is connected with the second gate line in the i th gate line group; a drain electrode of the element T 3 is connected with the gate electrode of the transistor T 2 in the pixel unit in which the element T 3 is disposed; and a source electrode of the T 3 is connected with a main gate line in the (i+1) th row or any gate line in the (i+1) th gate line group. For instance, when i=n, the source electrode of the element T 3 is connected with the (i+1) th main gate line (namely the (n+1) th main gate line); and when 1≦i≦n−1, the source electrode of the element T 3 is connected with the first gate line or the second gate line in the (i+1) th gate line group. In this way, if the gate electrode of the transistor T 2 in the i th gate line group is required to be at a high level, the drain electrode of the element T 3 in the i th gate line group must be at a high level, namely the main gate lines Gi and Gi+1 must be at a high level at the same time.

In another implementation, the source electrode of the element T 3 may be connected with the second gate line in the i th gate line group and the gate electrode of the element T 3 may be connected with the main gate line in the (i+1) th row or any gate line in the (i+1) th gate line group, as long as the gate electrode of the transistor T 2 in the i th gate line group is at a high level when the main gate line Gi and Gi+1 are at a high level at the same time.

An embodiment of the present invention further provides a display device employing an LCD. The LCD comprises the array substrate provided in the embodiment of the present invention; and various gate lines in the array substrate respectively control various rows of pixel units in the LCD. The LCD, for instance, comprises an opposing substrate (e.g., a color filter substrate). The opposing substrate and the array substrate are arranged opposite to each other to form a liquid crystal cell filled with liquid crystal materials. The LCD, for instance, may further comprise a light source, e.g., a backlight.

An embodiment of the present invention further provides a control method of the display device. The control method is, for instance, as follows.

In the scanning process of the i th main gate line, in the first time period, the i th main gate line and the (i+1) th main gate line are at a high level. At this point, one end of the switching element in the second pixel unit corresponding to the second gate line in the i th gate line group, which end is connected with the main gate line in the (i+1) th row (or any gate line in the (i+1) th gate line group), is at a high level, so that the gate electrode of the second transistor in the second pixel unit is at a high level, namely the second transistor is switched on under the control of the switching element. At this point, data signals of the second pixel group corresponding to the second gate line in the i th gate line group can be outputted by the data lines to charge pixel electrodes of the pixel units in the row.

In the second time period, only the i th main gate line is at a high level, and thus the gate electrode of the first transistor in the i th gate line group is at a high level. At this point, data signals of the first pixel group corresponding to the first gate line in the i th gate line group are outputted by data lines to charge the pixel electrodes of the pixel units in the row.

The display control of the display device can be achieved with the above method by the recurrence of i increased from 1 to n. The specific examples in the scanning process will be described below with reference to the accompanying drawings.

As illustrated in FIG. 2 , in the scanning process of the i th main gate line, in the first time period t 1 , the i th main gate line Gi and the (i+1) th main gate line Gi+1 are at a high level. When i=1, namely the main gate lines G 1 and G 2 are at a high level, at this point, both the gate electrodes and the source electrodes of the switching elements T 3 in the first gate line group are at a high level, so that the drain electrodes of the elements T 3 are also at a high level, and hence the gate electrodes of the transistors T 2 in the first gate line group are at a high level, namely the transistors T 2 are switched on under the control of the switching elements; and meanwhile the data signals of the second pixel group corresponding to the second gate line (namely the second row of pixel units corresponding to g 2 ) in the first gate line group are outputted by the data lines D to charge the pixel electrodes in the second row of pixel units.

Of course, at this point, the gate electrodes of the transistors T 1 in the first gate line group and the gate electrodes of the transistors T 1 in the second gate line group are also at a high level, and hence the first row of pixel units and the third row of pixel units are also charged with the same data signals as those for the second row of pixel units. However, the first row of pixel units will be recharged with correct data signals in the subsequent second time period t 2 ; and similarly, the third row of pixel units will be recharged with correct data signals in the subsequent fourth time period t 4 . Therefore, the final display effect of the first row of pixels and the third row of pixels will not be affected.

In the second time period t 2 , only the main gate line G 1 is at a high level, and hence the gate electrodes of the transistors T 1 in the first gate line group are at a high level; and meanwhile the data signals of the first pixel group corresponding to the first gate line (namely the first row of pixel units corresponding to g 1 ) in the first gate line group are outputted by the data lines D to charge the pixel electrodes in the first row of pixel units.

In the third time period t 3 (equivalent to another first time period when i=2), the main gate lines G 2 and G 3 are at a high level, at this point, both the gate electrodes and the source electrodes of the switching elements T 3 in the second gate line group are at a high level, so that the drain electrodes of the switching elements T 3 are also at a high level, and hence the gate electrodes of the transistors T 2 in the second gate line group are at a high level; and meanwhile data signals of the second pixel group corresponding to the second gate line (namely the fourth row of pixel units corresponding to g 4 ) in the second gate line group are outputted by the data lines D to charge the pixel electrodes in the fourth row of pixel units.

In the fourth time period t 4 (equivalent to another second time period when i=2), only the main gate line G 2 is at a high level, and hence the gate electrodes of the transistors T 1 in the second gate line group are at a high level; and meanwhile the data signals of the first pixel group corresponding to the first gate line (namely the third row of pixel units corresponding to g 3 ) in the second gate line group are outputted by the data lines D to charge pixel electrodes in the third row of pixel units.

The display control of the display device can be achieved with the above method by the recurrence of i from 1 to n.

The array substrate provided in the embodiment of the present invention comprises n gate line groups and each gate line group comprises two adjacent gate lines, namely the display device comprises 2n gate lines in total and can be controlled by the control method also provided in the embodiment of the present invention. In this way, only n+1 main gate lines are required to be disposed on one side of the display area, and hence the number of routings on the side of the display area is almost a half of the total amount of the gate lines, and consequently the frame width of the LCD can be reduced. For instance, as for an HVGA type LCD, 480 gate lines are disposed in a gate electrode drive circuit on an array substrate of the LCD (n=240); only 241 main gate lines are required to be disposed on the side of a display area; with double routing, 120 main gate lines are required to be disposed on one side of the display area and 121 main gate lines are required to be disposed on the other side, and therefore the frame width can be reduced to be 1.7 mm or so. Moreover, the defect of H-lines caused by the alternate routing in the prior art can be overcome.

Moreover, if the defect of the H-lines is ignored, the technical proposal provided in the embodiment of the present invention may also adopt the alternate routing described in the prior art to arrange the gate lines and the gate electrode driver. In this case, the frame width can be further reduced to be less than 1.2 mm.

It should be noted that: in the embodiment of the present invention, as illustrated in FIG. 1 , the preceding gate line in each gate line group is defined to be the first gate line and the subsequent gate line is defined to be the second gate line, but the embodiment of the present invention is not limited thereto and the positions of the first gate line and the second gate line in the gate line group are changeable. In that way, for instance, exchange is performed based on the situation as shown in FIG. 1 , in the first gate line group, the first gate line becomes the second row of gate line g 2 in the LCD while the second gate line becomes the first row of gate line g 1 in the LCD. Also, in the second gate line group, the first gate line becomes the fourth row of gate line g 4 in the LCD while the second gate line becomes the third row of gate line g 3 in the LCD. In this way, the driving process can be achieved in the sequence of the gate lines g 1 , g 2 , g 3 . . . g2n in the display control process, so that the pixel electrodes in the rows of pixel units can be charged in normal sequence.

The array substrate of the embodiment is basically the same as that of the embodiment 1, with the difference as follows: as illustrated in FIG. 3 , in the embodiment, the n+1 main gate line is connected with the first main gate line G 1 . In this way, the main gate lines Gn+1 and G 1 can be controlled together. The timing chart of the main gate line G 1 (also Gn+1) may be as shown in FIG. 4 . In two time periods prior to the first time period t 1 in the embodiment 1, namely in the time period t2n−1 and t2n of the last scanning process, the main gate line G 1 is cooperative with the main gate line Gn, so that pixel electrodes in the 2n−1 row of pixel units and the 2n row of pixel units can be charged.

The array substrate of the embodiment is basically the same as that of the embodiment 1, with the difference as follows: in the embodiment, the (n+1) th main gate line Gn+1 is merged to the first main gate line G 1 , namely the main gate lines Gn+1 and G 1 are combined into one main gate line indicated as G 1 , and hence the gate electrodes (or the source electrodes) of the switching elements T 3 in the n th gate line group are still connected with the second gate line in the n th gate line group but the source electrodes (or the gate electrodes) of the switching elements T 3 in the n th gate line group should be connected to the main gate line G 1 , for instance, may be connected to the first gate line or the second gate line in the first gate line group. At this point, the timing chart of the main gate line G 1 (namely Gn+1) may be still as shown in FIG. 4 .

The control method in the embodiment 2 may also be applied here. In addition, one main gate line may be further reduced. For instance, in the HVGA type LCD, only 120 main gate lines are required to be disposed on both sides of the display area respectively, and hence the routing symmetry on both sides of the display area can be improved.

The foregoing is only the preferred embodiments of the present invention and not intended to limit the scope of protection of the present invention. The scope of protection of the present invention should be defined by the appended claims.