Integrated limiter and active filter

The present invention relates to the field of current control for a load, and in particular to an arrangement that provides a current limiter, load dump protection and integrated active filter.

Remote powering, wherein the power supply is located at a distance from the load, and connected over standard cabling, requires attention to particular factors. For simplicity, the power supply will be herein denoted a power sourcing equipment (PSE) and the load to be powered will be a called a powered device (PD). Firstly, detection by the PSE that a compatible PD is connected prior to supplying power is typically desirable. Secondly, limitation of the amount of current that may be drawn from the PSE over the cabling is preferred so as to provide protection for the PSE and for the cabling in event of a short circuit, or near short circuit at the PD side.

In the event of remote powering in an automobile, additional issues include load dump protection and the varying input voltage with ripple. The term load dump protection in an automotive environment is generally understood to mean protection of the load against extreme voltage transients in the event of disconnection of the battery while the alternator is sending out a charging current. In such a case the voltage output by the alternator may rise from a nominal voltage of about 14 V to a voltage in excess of 100 V for up to 500 msec.

Automotive power supply systems may exhibit a varying direct current (DC) output voltage, based on load, engine speed and battery condition. The varying output voltage may further exhibit some ripple voltage, which may be exhibit a very wide frequency spectrum, including low sub-bass frequency components and frequencies in the megahertz plus ranges. In the event that only a single wire pair is utilized for both power and data transfer, filtering of the high frequency ripple is necessary to avoid data interference. Additionally, such an active filter will reduce the demands on any DC/DC converter in the system, thus allowing for reduced cost.

Accordingly, it is a principal object of the present invention to overcome at least some of the disadvantages of the prior art. This is provided by an integrated arrangement providing current limiting, load dump protecting and active high frequency filtering around a single transistor, particularly a field effect transistor (FET) and more particularly a metal oxide semiconductor FET (MOSFET).

A first control circuit is provided in communication with a current sensor, the first control circuit arranged to control the single transistor so as to govern current flow there through so as not to exceed a predetermined value. A second control circuit is providing in communication with the output node, the second control circuit arranged to control the single transistor so as to limit the voltage appearing at the output node so as not to exceed a reference value. A third control circuit is provided to generate the reference value for the second control circuit. The third control circuit provides a reference value which: may not exceed a predetermined maximum value, thereby providing load dump protection; and is varied in accordance with the average received input voltage so as to reduce power loss across the single transistor.

The present embodiments enable an integrated limiter and active filter comprising: an input node; an output node; a transistor coupled between said input node and said output node; a first control circuit coupled to a control terminal of said transistor, said first control circuit arranged to limit an amount of current flowing through said output node to a first predetermined value, the first predetermined value responsive to a first reference signal; a second control circuit coupled to the control terminal of said transistor, said second control circuit arranged to limit the voltage appearing at said output node to a second predetermined value, the second predetermined value responsive to a second reference signal; and a third control circuit coupled to said input node and arranged to provide said second reference signal, said second reference signal responsive to the input voltage and to a predetermined maximum allowed output voltage.

In one embodiment, said third control circuit is arranged to set said second reference signal to a value equal to the minimum of: the input voltage at said input node determined over a predetermined period plus a predetermined offset; and a predetermined maximum value. In another embodiment the first reference signal is a ramped signal during a startup phase of the integrated limiter and active filter.

In one embodiment the integrated limiter and active filter further comprises a coupling and bias network, an output of said coupling and bias network coupled to a control terminal of said transistor, said coupling and bias network arranged to couple the output of each of first control circuit and said second control circuit to the control terminal of the transistor. In one further embodiment said coupling and bias network is further arranged to bias said transistor to be on when voltage at said input node is greater than voltage at said output node. In another further embodiment said first control circuit comprises a first differential amplifier arranged to compare a representation of the amount of current with the first reference signal, the output of said first differential amplifier coupled to said control terminal of said transistor via said coupling and bias network. In yet another further embodiment said second control circuit comprises a second differential amplifier arranged to compare a representation of the voltage at said output node with the second reference signal, the output of said second differential amplifier coupled to said control terminal of said transistor via said coupling and bias network.

Independently the present embodiments enable a method of providing an integrated active filtering and current limiting for electrical power provided via a transistor, the method comprising: comparing a representation of an amount of current flow through the transistor with a first reference signal; comparing a representation of an output voltage associated with the transistor with a second reference signal; and controlling the transistor responsive to said comparison with the first reference signal and said comparison with the second reference signal such that said current flow representation does not exceed said first reference signal and said output voltage representation does not exceed said second reference signal.

In one embodiment the method further comprises providing the second reference signal responsive to the input voltage and to a predetermined maximum allowed output voltage so as to provide ripple rejection. In another embodiment the method further comprises providing the second reference signal responsive to the input voltage determined over a predetermined period plus a predetermined offset and a predetermined maximum value.

In one embodiment the method further comprises providing the first reference signal as a ramped signal during a startup phase. In another embodiment the method further comprises biasing said transistor to be on when voltage at said input node is greater than voltage at said output node.

Independently the present embodiments enable an integrated limiter and active filter comprising: an input node; an output node; a transistor coupled between said input node and said output node; a first control means coupled to a control terminal of said transistor, said first control means arranged to limit an amount of current flowing through said output node to a first predetermined value, the first predetermined value responsive to a first reference signal; a second control means coupled to the control terminal of said transistor, said second control means arranged to limit the voltage appearing at said output node to a second predetermined value, the second predetermined value responsive to a second reference signal; and a third control means coupled to said input node and arranged to provide said second reference signal, said second reference signal responsive to the input voltage and to a predetermined maximum allowed output voltage.

In one embodiment, said third control means is arranged to set said second reference signal to a value equal to the minimum of: the input voltage at said input node determined over a predetermined period plus a predetermined offset; and a predetermined maximum value. In another embodiment the first reference signal is a ramped signal during a startup phase of the integrated limiter and active filter.

In one embodiment the integrated limiter and active filter further comprises a coupling and bias network, an output of said coupling and bias network coupled to a control terminal of said transistor, said coupling and bias network arranged to couple the output of each of first control means and said second control means to the control terminal of the transistor. In one further embodiment said coupling and bias network is further arranged to bias said transistor to be on when voltage at said input node is greater than voltage at said output node. In another further embodiment said first control means comprises a first differential amplifier arranged to compare a representation of the amount of current with the first reference signal, the output of said first differential amplifier coupled to said control terminal of said transistor via said coupling and bias network. In yet another further embodiment said second control means comprises a second differential amplifier arranged to compare a representation of the voltage at said output node with the second reference signal, the output of said second differential amplifier coupled to said control terminal of said transistor via said coupling and bias network.

Additional features and advantages of the invention will become apparent from the following drawings and description.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings in which like numerals designate corresponding elements or sections throughout.

With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice. In the accompanying drawing:

FIG. 1 illustrates a high level schematic diagram of an exemplary integrated limiter and active filter; and

FIG. 2 illustrates an exemplary method of providing an integrated active filtering and current limiting.

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is applicable to other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.

FIG. 1 illustrates a high level schematic diagram of an exemplary integrated limiter and active filter comprising a transistor M 1 ; a coupling and bias network 10 ; a first control circuit 20 ; a second control circuit 30 and a third control circuit 40 . Coupling and bias network 10 comprises: a bias voltage input lead, coupled to a bias voltage VCP; a resistor R 6 ; a capacitor C 1 ; a diode D 1 ; a resistor R 7 ; a breakdown diode D 2 ; and a first and a second transistor M 2 and M 3 , illustrated without limitation as NMOSFETs. First control circuit 20 comprises: a sense resistor R 1 ; a plurality of resistors R 2 , R 3 , R 4 and R 5 ; a differential amplifier U 1 ; and an optional compensation network COMP 1 . Second control circuit 30 comprises: a resistor R 8 ; a resistor R 9 ; a capacitor C 2 ; a differential amplifier U 2 ; and an optional compensation network COMP 2 . Third control circuit 40 preferably comprises an A/D converter internal thereto, and is arranged to receive a maximum reference voltage level, denoted VOUT_CLAMP_SET; and an offset voltage level, denoted: ACTIVE_FILTER_VDS_DROP_SET. A reference voltage is provided, denoted VREF 1 , which may be internally generated, or externally provided.

An input node, denoted VIN, is arranged to receive an input electrical power. Input node VIN is coupled to a first end of sense resistor R 1 , resistor R 2 and to the input of third control circuit 40 . A second end of resistor R 2 is coupled to a first end of resistor R 4 , to the non-inverting input of differential amplifier U 1 and to a first end of optional compensation network COMP 1 , and is denoted voltage VA. A second end of resistor R 4 is coupled to a common potential. A second end of sense resistor R 1 is coupled to a first end of resistor R 3 and to the drain of transistor M 1 . A second end of resistor R 3 is coupled to the inverting input of differential amplifier U 1 , and via resistor R 5 to a reference source denoted VREF 1 . The voltage at the non-inverting input of differential amplifier U 1 is denoted voltage VB.

The gate of transistor M 1 is coupled to the anode of diode D 1 , to a first end of resistor R 6 , to a first end of capacitor C 1 and to the cathode of breakdown diode D 1 , and is denoted voltage VG. A second end of resistor R 6 is coupled to a bias voltage VCP and a second end of capacitor C 1 is coupled to the common potential. The cathode of diode D 1 is coupled via resistor R 7 to the drains of each of transistors M 2 and M 3 , the voltage at the drains of transistors M 2 , M 3 denoted VCTRL. The sources of transistors M 2 and M 3 are coupled to the common potential. The gate of transistor M 2 is coupled to the output of differential amplifier U 1 and the gate of transistor M 3 is coupled to the output of differential amplifier U 2 .

The source of transistor M 1 is coupled to the anode of breakdown diode D 2 , to a first end of resistor R 8 and to a first end of capacitor C 2 , and is denoted VOUT, i.e. the output node. A second end of resistor R 8 is coupled to the non-inverting input of differential amplifier U 2 , to a first end of optional compensating network COMP 2 , and via resistor R 9 to the common potential. A second end of capacitor C 2 is coupled to the common potential. The output of control circuit 40 , denoted VREF 2 , is coupled to the inverting input of differential amplifier U 2 .

In operation, first control circuit 20 governs the amount of current flowing out of output node VOUT so that it does not exceed a predetermined value. Current flowing from the input node towards the output node passes through sense resistor R 1 , and produces a voltage drop there through, denoted VCS. Bias voltage VCP is set to a voltage higher than VIN, so as to allow M 1 to be turned on.

The voltage across sense resistor R 1 is measured by the resistor network comprising resistors: R 2 , R 3 , R 4 and R 5 which forms a differential measurement network. In a preferred embodiment R 2 =R 3 =R 4 =R 5 , the common value of which is denoted R. As a result U 1 senses across its input terminals a voltage which is correlated to the current through R 1 , which as indicated above is also the input and output current of M 1 . R 1 is illustrated at the input side of M 1 , however this is not meant to be limiting in any way, and in an alternative embodiment R 1 is arranged between the source of transistor M 1 and the output note VOUT, without exceeding the scope.

VREF 1 is coupled to the inverting input of U 1 via R 5 , and thus sets the maximum current through transistor M 1 , denoted IOUT_MAX, as:

IOUT_MAX=(VREF1/ R 1)*(1/ K− 1)  EQ. 1

where K is:

K=R 4/( R 2+ R 4)= R 5/( R 3+ R 5)  EQ. 2

Differential amplifier U 1 controls the drain voltage of M 2 , which results in control of the gate voltage VG of transistor M 1 . As long as VCS is reflective of a condition wherein the current through the output node is less than IOUT_MAX, the voltage at the inverting input of U 1 is higher than the voltage at the non-inverting input of U 1 , which results that the output of U 1 output is driven low, or close to the common potential, which drives transistor M 2 off. If transistor M 2 is off, the gate of transistor M 1 is biased to voltage VCP, and transistor M 1 is thus driven on.

As VCS increases towards a voltage reflective of IOUT_MAX, differential amplifier U 1 turns on transistor M 2 , which thus modulates gate voltage VG to prevent VCS from rising to reflect a voltage in excess of IOUT_MAX. Steady state is achieved when voltage VA is approximately equal to voltage VB. Optional compensation network COMP 1 is provided to provide loop stability. The above has been described in an embodiment wherein U 1 is utilized to control M 1 so as to act as a current limiter when the voltage drop across VCS is indicative that the current through M 1 approaches IOUT_MAX, however this is not meant to be limiting. In an alternate embodiment M 1 is set to open when the current though M 1 approaches IOUT_MAX, by latching U 1 for a predetermined period responsive to an output of third control circuit 40 (not shown). In such an embodiment compensation network COMP 1 is not required.

D 1 functions to prevent VOUT from becoming negative when VIN is connected to a negative voltage by blocking conduction of the body diodes of transistors M 2 and M 3 , which body diodes are forward biased in the event that VIN is connected to a negative potential as compared to the common potential. The reverse voltage path through the body diode of transistor M 1 is preferably handled by a reverse protection circuit (not shown); the values of R 8 and R 9 may be selected so as to cooperate with such a reverse protection circuit. R 7 is arranged to limit the current through transistors M 2 , M 3 when they are on. D 2 is arranged to protect the VGS of transistor M 1 from over voltage between VCP and Vout. D 1 and D 2 are optional, and may not always be required. In normal operation VCP is greater than VIN, preferably by a predetermined value sufficient to ensure complete turn on of transistor M 1 . In an exemplary embodiment, VCP is set to be 6-10 volts above VIN. In one embodiment VCP is generated via a charge pump device coupled to VIN via a diode. Preferably, the charge pump device is arranged such that in the event that VIN is reverse biased, the charge pump device does not allow for a negative voltage greater than a predetermined value, in relation to the common potential, to appear at VOUT.

Second control circuit 30 provides load dump protection via transistor M 1 . The control loop for differential amplifier U 2 is ORed with the control loop of differential amplifier U 1 by coupling and bias network 10 to provide dual control of transistor M 1 .

When VOUT*R 9 /(R 9 +R 8 ) is about VREF 2 the voltage loop of U 2 and transistor M 3 in cooperation with transistor M 1 limits VOUT so that VOUT does not exceed the value set by VREF 2 . C 2 is the output capacitor for VOUT.

R 6 and C 1 form a low pass filter so that in the event that VIN changes rapidly, which is followed by VCP, VG remains almost constant. VOUT is set by VG and as long as VG remains unchanged VOUT remains unchanged, irrespective of the change in VIN. Constraining VG to change slowly via the low pass filter of R 6 and C 1 ensures that rapid changes in VIN, faster than the response time of control circuitry 30 , are not passed to VOUT. Similarly, overshoot in the event of a large spike in VIN is avoided, and control circuitry 30 ensures that VOUT does not exceed the value set by VREF 2 .

VCP is preferably set to be greater than the maximum VIN plus the minimum required VGS for transistor M 1 to be on. Transistor M 1 is illustrates as an NMOS transistor, however a PMOS transistor may be implemented, with appropriate circuit elements and polarity without exceeding the scope.

In one embodiment, VREF 1 is slope controlled during startup so as to ensure a soft start for VOUT. Adding an initial slope to VREF 1 ensures that the current output at node VOUT slowly ramps up during startup, when a large capacitive load may appear across output node, thus preventing large inrush current.

Control circuit 40 adjusts VREF 2 to provide active filtering. In particular, the adjustment of VREF 2 functions to set VOUT to be below the minimum value of VIN for ripple rejection while maintaining the minimal, or near minimal, required voltage drop across M 1 so as to reduce power dissipation. The minimum value of VIN is described below, but is not meant to include values so low as to prevent proper operation of ultimate load circuitry. Control circuitry is in one embodiment provided with an A/D converter. VIN is sampled, and control circuitry 40 determines the minimum value of VIN, denoted VIN_MIN, preferably after filtering out any noise. In one non-limiting embodiment, VIN_MIN is determined responsive to a determination of the average voltage and the peak to peak ripple voltage.

Control circuitry 40 functions to generate VREF 2 to a value that will set Vout to be ≦VIN_MIN by setting VOUT to:

VOUT=VIN_MIN−VDS_MIN  EQ. 3

where VDS_MIN is a minimum safety margin to ensure that all ripple is rejected. Setting VOUT in accordance with EQ. 3 ensures that any ripple voltage on VIN is rejected by M 1 and is not seen at VOUT. Additionally, setting VOUT in accordance with EQ. 3 minimized the power loss across transistor M 1 , since VOUT is set as close as practical to VIN_MIN so as to block any ripple from appearing at VOUT.

Parameters of VOUT can preferably be overridden by the user. In one embodiment, as illustrated, a value may be provided by a user at input ACTIVE_FILTER_VDS_DROP_SET of third control circuitry 40 . In the event that a value is presented at input ACTIVE_FILTER_VDS_DROP_SET of third control circuitry 40 , third control circuitry 40 is arranged to determine the average voltage of VIN, denoted VIN_AVG, and set VOUT via VREF 2 to be:

Alternately, third control circuitry 40 may be arranged to set VOUT to:

Third control circuitry 40 optionally additionally exhibits an input denoted VOUT_CLAMP_SET. This is a priority setting for VOUT and determines the maximum amount of VOUT that may be allowed by the setting of VREF 2 . Thus, VOUT_CLAMP_SET represents the output of VOUT in the event of load dump.