Liquid crystal display device

This application claims priority to and the benefit of Korean Patent Application No. 10-2014-0020516, filed on Feb. 21, 2014 in the Korean Intellectual Property Office, the content of which is incorporated herein by reference in its entirety.

1. Field

The following description relates to a liquid crystal display device.

2. Description of the Related Art

A liquid crystal display, which is one of the display devices that have been widely used (utilized), is a display device that can adjust the quantity of penetrating light by applying a voltage to two opposite electrodes (a pixel electrode and a common electrode) and thereby controlling an arrangement of liquid crystal molecules of a liquid crystal layer interposed between the two electrodes.

Typically, the liquid crystal display device is configured to maintain a distance between two substrates such that a liquid crystal layer is provided between the two substrates. For this configuration, a spacer is formed between the two substrates. However, since the spacer is bonded to one of the two substrates through an adhesive, a manufacturing process of the liquid crystal display device may be complicated, and the cost may be increased.

In order to simplify a manufacturing process of the liquid crystal display device and reduce the cost, a liquid crystal display device including a cavity on one substrate to provide a space for forming a liquid crystal layer, instead of a spacer between two substrates, has been developed.

In order to improve the visibility, the liquid crystal display device has been developed such that one pixel is divided into two sub-pixels, and a voltage of high level and a voltage of low level are applied to the two sub-pixels, respectively, to differ the alignment direction of liquid crystal molecules in one pixel. To that end, the liquid crystal display device includes a plurality of thin film transistors or the like, and the structure including a plurality of thin film transistors or the like narrows an opening area through which light is transmitted. Thus, there may be a limit to an increase in aperture ratio of the liquid crystal display device.

Aspects of the present inventive concept are directed toward a liquid crystal display device capable of increasing an aperture ratio while improving the visibility, and also reducing or minimizing the loss of transmittance.

However, aspects of the present invention are not restricted to the one set forth herein. The above and other aspects of the present invention will become more apparent to one of ordinary skill in the art to which the present invention pertains by referencing the detailed description of embodiments of the present invention given below.

In one embodiment of the present invention, a liquid crystal display device includes: a substrate including a plurality of pixels, each pixel having a first sub-pixel and a second sub-pixel; a pixel electrode on the substrate and including a first pixel electrode in a region corresponding to the first sub-pixel and a second pixel electrode in a region corresponding to the second sub-pixel; a common electrode on the substrate and including a first common electrode spaced (spaced apart) from the first pixel electrode and a second common electrode spaced from the second pixel electrode; and a thin film transistor on the substrate and electrically connected to the first pixel electrode and the second pixel electrode.

A same data voltage may be applied to the first pixel electrode and the second pixel electrode, wherein a first common voltage is applied to the first common electrode, and wherein a second common voltage different from the first common voltage is applied to the second common electrode.

Each of the first common voltage and the second common voltage may have a swing of 1V in irregular units of frames.

The first pixel electrode and the second pixel electrode may have an area ratio of 1:1.

The liquid crystal display device may further include: a plurality of gate lines on the substrate, extending in a first direction and spaced from each other in a second direction intersecting (crossing) the first direction; a plurality of common lines on the substrate and in parallel to the gate lines; and a plurality of data lines on the substrate, spaced from the gate lines, extending in the second direction, and spaced from each other in the first direction, wherein among the plurality of common lines, odd-numbered common lines are electrically connected to the first common electrode, and even-numbered common lines are electrically connected to the second common electrode.

The first sub-pixel may be above a first gate line of the plurality of gate lines in the second direction, and the second sub-pixel may be below the first gate line in the second direction.

A second gate line of the plurality of gate lines may be at a next stage of the first gate line (next to and at a set distance away from the first gate line), a first sub-pixel is above the second gate line (in a plane view of the liquid crystal display device), and a second sub-pixel is below the second gate line, and wherein the first common electrode or the second common electrode is a single (one piece) electrode on a second pixel electrode of the second sub-pixel below the first gate line and a first pixel electrode of the first sub-pixel above the second gate line.

Each of the first common electrode and the second common electrode may have a structure horizontally extending in the first direction.

The thin film transistor may include a gate electrode connected to each of the gate lines, a source electrode connected to each of the data lines, and a drain electrode connected to the first pixel electrode and the second pixel electrode, and wherein the liquid crystal display device may further include: a first contact hole to electrically connect the first pixel electrode and the second pixel electrode to the drain electrode; a second contact hole to electrically connect the first common electrode to the odd-numbered common lines; a third contact hole to electrically connect the second common electrode to the even-numbered common lines; and a liquid crystal layer between the first pixel electrode and the first common electrode, and between the second pixel electrode and the second common electrode.

In another embodiment of the present invention, a liquid crystal display device includes: a substrate including a plurality of pixels, each pixel having a first sub-pixel and a second sub-pixel; a plurality of gate lines on the substrate extending in a first direction and spaced from each other in a second direction intersecting (crossing) the first direction, and a plurality of common lines on the substrate in parallel to the gate lines; a gate insulating layer on the substrate to cover the gate lines and the common lines; a plurality of data lines on the gate insulating layer extending in the second direction and spaced from each other in the first direction; and an insulating layer on the gate insulating layer to cover the data lines; a pixel electrode including a first pixel electrode in a region corresponding to the first sub-pixel and a second pixel electrode in a region corresponding to the second sub-pixel on the insulating layer; a common electrode on the insulating layer and spaced from the pixel electrode, a cavity between the common electrode and the pixel electrode, the common electrode including a first common electrode extending in the first direction to overlap with the first pixel electrode and a second common electrode extending in the first direction to overlap with the second pixel electrode; and a thin film transistor on the substrate and electrically connected to the first pixel electrode and the second pixel electrode.

A same data voltage may be applied to the first pixel electrode and the second pixel electrode, wherein a first common voltage is applied to the first common electrode, and wherein a second common voltage different from the first common voltage is applied to the second common electrode.

Each of the first common voltage and the second common voltage may have a swing (a change in voltage) of 1V in irregular units of frames.

The first pixel electrode and the second pixel electrode may have an area ratio of 1:1.

The first sub-pixel may be above a first gate line of the plurality of gate lines in the second direction, and the second sub-pixel may be below the first gate line in the second direction.

A second gate line of the plurality of gate lines may be at a next stage of the first gate line, a first sub-pixel is above the second gate line, and a second sub-pixel is below the second gate line, and wherein the first common electrode or the second common electrode is a single electrode on a second pixel electrode of the second sub-pixel below the first gate line and a first pixel electrode of the first sub-pixel above the second gate line.

The liquid crystal display device may further include: a first protective layer between the insulating layer and the pixel electrode; a second protective layer on the common electrode; a covering layer on the first protective layer to include sidewalls to separate the plurality of pixels from each other in the first direction, and a roof above the sidewalls; a liquid crystal layer including liquid crystal molecules injected into the cavity (liquid crystal materials in the cavity); and a capping layer on the covering layer.

The covering layer may include a liquid crystal inlet in the first direction to overlap with the gate lines, and wherein the liquid crystal display device further includes a sealing film to seal the liquid crystal inlet.

The thin film transistor may include a gate electrode connected to each of the gate lines, a source electrode connected to each of the data lines, and a drain electrode connected to the first pixel electrode and the second pixel electrode.

The liquid crystal display device may further include: a first contact hole to expose the drain electrode through the first protective layer and the insulating layer; a second contact hole to expose a first protrusion on a first common line through the first protective layer, the insulating layer and the gate insulating layer; and a third contact hole to expose a second protrusion on a second common line through the first protective layer, the insulating layer and the gate insulating layer, wherein the first pixel electrode and the second pixel electrode are electrically connected to the drain electrode through the first contact hole, the first common electrode is electrically connected to the first common line through the second contact hole, and the second common electrode is electrically connected to the second common line through the third contact hole.

The first protrusion may be between first sub-pixels in the first direction, and the second protrusion may be between second sub-pixels in the first direction.

According to the embodiments of the present invention, at least the following effects can be obtained.

In the liquid crystal display device according to one embodiment of the present invention, by forming in one pixel and on one substrate a thin film transistor, a first pixel electrode and a second pixel electrode to which the same pixel voltage is applied, and a first common electrode and a second common electrode to which different common voltages are applied, it is possible to increase an aperture ratio while improving the visibility with a simple structure.

Further, in the liquid crystal display device according to one embodiment of the present invention, by controlling in one pixel a difference between a first voltage applied to a first sub-pixel and a second voltage applied to a second sub-pixel to about 1V or less, display quality can be improved by minimizing (reducing) the loss of transmittance, for example, the loss of transmittance at a high gray level.

The effects of the present invention are not limited to the above-described effects and other effects which are not described herein will become apparent to those skilled in the art from the following description.

The above and other aspects and features of the present inventive concept will become more apparent by describing in more detail example embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a schematic diagram of a liquid crystal display device according to one embodiment of the present invention;

FIG. 2 shows a layout of one pixel of FIG. 1 ;

FIG. 3 is a cross-sectional view taken along the line I-I′ of FIG. 2 ;

FIG. 4 is a cross-sectional view taken along the line II-II′ of FIG. 2 ;

FIG. 5 is a cross-sectional view taken along the line III-III′ of FIG. 2 ;

FIG. 6 is a cross-sectional view taken along the line IV-IV′ of FIG. 2 ;

FIG. 7 is a cross-sectional view taken along the line V-V′ of FIG. 2 ;

FIG. 8 is an equivalent circuit diagram of one pixel of FIG. 1 ;

FIG. 9 is a diagram for explaining voltages applied to the sub-pixels of FIG. 1 ;

FIG. 10 is a diagram showing the arrangement of voltages applied to the sub-pixels of FIG. 1 ;

FIG. 11 is a diagram showing the polarity of the pixel voltage applied to the sub-pixels and the arrangement of the common electrodes of FIG. 1 ;

FIG. 12 is a diagram showing an example of the first common voltage applied to the first common electrode of FIG. 1 ;

FIG. 13 is a diagram showing an example of the second common voltage applied to the second common electrode of FIG. 1 ; and

FIG. 14 is a graph showing a simulation of a voltage difference between the first sub-pixel and the second sub-pixel according to a gray scale in the liquid crystal display device of FIG. 1 .

Enhancements and features of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of example embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the scope of the present invention will only be defined by the appended claims, and equivalents thereof.

It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numbers indicate the same components throughout the specification. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the present invention refers to “one or more embodiments of the present invention.”

It will be understood that, although the terms “first”, “second”, “third”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Spatially relative terms, such as “below,” “beneath,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a liquid crystal display device according to one embodiment of the present invention, and FIG. 2 shows a layout of one pixel of FIG. 1 . FIG. 3 is a cross-sectional view taken along the line I-I′ of FIG. 2 , and FIG. 4 is a cross-sectional view taken along the line II-II′ of FIG. 2 . FIG. 5 is a cross-sectional view taken along the line III-III′ of FIG. 2 , and FIG. 6 is a cross-sectional view taken along the line IV-IV′ of FIG. 2 . FIG. 7 is a cross-sectional view taken along the line V-V′ of FIG. 2 .

Referring to FIGS. 1 to 7 , a liquid crystal display device 100 according to one embodiment of the present invention may include a substrate 105 , gate lines GL 1 , GL 2 , . . . , GLn, data lines DL 1 , DL 2 , . . . , DLm, common lines CL 1 , CL 2 , . . . , CLo, a gate insulating layer GIL, thin film transistors TFT, an insulating layer 110 , color filters CF, a black matrix BM, a first protective layer 115 , pixel electrodes PE, common electrodes CE, a second protective layer 120 , a covering layer 125 , a third protective layer 130 , an alignment film 135 , a liquid crystal layer LCL, a sealing film 140 and a capping layer 145 (e.g., FIGS. 1 to 4 ).

The substrate 105 may be a transparent insulating substrate, and include a plurality of pixels PX, each pixel having a first sub-pixel SPX 1 and a second sub-pixel SPX 2 .

The gate lines GL 1 , GL 2 , . . . , GLn are formed on the substrate 105 to extend in a first direction X and arranged to be spaced (spaced apart) from each other in a second direction Y intersecting (crossing) the first direction X. The gate lines GL 1 , GL 2 , . . . , GLn transmit a gate signal to the thin film transistors TFT. In this case, for example, the first sub-pixel SPX 1 of one pixel PX may be located above the first gate line GL 1 in the second direction Y, and the second sub-pixel SPX 2 may be located below the first gate line GL 1 in the second direction Y.

The data lines DL 1 , DL 2 , . . . , DLm may be formed on the substrate 105 to extend in the second direction Y, and arranged to be spaced from each other in the first direction X. The data lines DL 1 , DL 2 , . . . , DLm are insulated from the gate lines GL 1 , GL 2 , . . . , GLn to transmit a data signal to the thin film transistors TFT.

The common lines CL 1 , CL 2 , . . . , CLo are parallel to the gate lines GL 1 , GL 2 , . . . , GLn. Similarly to the gate lines GL 1 , GL 2 , . . . , GLn, the common lines CL 1 , CL 2 , . . . , CLo are formed to extend in the first direction X and arranged to be spaced from each other in the second direction Y. Among the common lines CL 1 , CL 2 , . . . , CLo, each of the odd-numbered common lines CL 1 , CL 3 , . . . may include a first protrusion CLp 1 protruding in the second direction Y, and each of the even-numbered common lines CL 2 , CL 4 , . . . may include a second protrusion CLp 2 protruding in the second direction Y (see FIGS. 2, 6 and 7 ). The common lines CL 1 , CL 2 , . . . , CLo apply a common voltage to the common electrodes CE.

The gate insulating layer GIL is formed of an insulating material to cover the gate lines GL 1 , GL 2 , . . . , GLn and the common lines CL 1 , CL 2 , . . . , CLo formed on the surface of the substrate 105 . For example, the gate insulating layer GIL may include silicon nitride or silicon oxide. Also, the data lines DL 1 , DL 2 , . . . , DLm may be formed on the gate insulating layer GIL.

The thin film transistor TFT includes a gate electrode GE, a semiconductor layer SM, a source electrode SE and a drain electrode DE.

The gate electrode GE may be formed to protrude toward the semiconductor layer SM from each of the gate lines GL 1 , GL 2 , . . . , GLn on the plane (on the same layer). The gate electrode GE may include any one of indium tin oxide (ITO), indium zinc oxide (IZO) and indium tin zinc oxide (ITZO). Further, the gate electrode GE may have a two-layer structure including a first electrode layer made of the aforementioned material and a second electrode layer. The second electrode layer may be formed of a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), tungsten (W), chromium (Cr), titanium (Ti), or an alloy including at least one of the metal materials.

The semiconductor layer SM is formed on the gate electrode GE while the gate insulating layer GIL is interposed therebetween. The semiconductor layer SM may include an active layer provided on the gate insulating layer GIL and an ohmic contact layer provided on the active layer. Also, the semiconductor layer SM may be formed between the data lines DL 1 , DL 2 , . . . , DLm and the gate insulating layer GIL.

The source electrode SE is formed to protrude from each of the data lines DL 1 , DL 2 , . . . , DLm and overlap with at least a portion of the gate electrode GE on the plane (when projected to the plane). The drain electrode DE is formed to be spaced from the source electrode SE and overlap with at least a portion of the gate electrode GE on the plane. The source electrode SE and the drain electrode DE may be made of metal such as copper (Cu), molybdenum (Mo), aluminum (Al), tungsten (W), chromium (Cr), titanium (Ti), or an alloy including at least one of the metal materials. In this case, the source electrode SE and the drain electrode DE each overlap with a part of the semiconductor layer SM in a region other than a spaced (gap) region between the source electrode SE and the drain electrode DE.

The insulating layer 110 may be formed on the gate insulating layer GIL, and include, for example, silicon nitride or silicon oxide.

Each of the color filters CF is formed on the insulating layer 110 to correspond to each pixel PX, for example, the first sub-pixel SPX 1 and the second sub-pixel SPX 2 . The color filter CF provides a color to the light transmitted through the liquid crystal layer LCL, and may be one of a red (R) filter, a green (G) filter and a blue (B) filter. However, the color filters CF are not limited to the above-mentioned color filters.

The black matrix BM is formed on the insulating layer 110 to correspond to the edge of each pixel PX, for example, the edge of the first sub-pixel SPX 1 and the edge of the second sub-pixel SPX 2 (see FIGS. 3 and 4 ). That is, the black matrix BM may be disposed so as to surround the color filters CF. The black matrix BM may overlap with the gate lines GL 1 , GL 2 , . . . , GLn, the data lines DL 1 , DL 2 , . . . , DLm, the common lines CL 1 , CL 2 , . . . , CLo and/or the thin film transistors TFT. The black matrix BM is formed of a light blocking material to block unnecessary light when implementing an image. For example, the black matrix BM may block light leakage caused by abnormal movement of liquid crystal molecules (materials) LC that may occur in the edge of the liquid crystal layer LCL, or color mixing that may occur in the edges of the color filters CF.

The first protective layer 115 may be formed on the color filters CF and the black matrix BM and serve to planarize the color filters CF and the black matrix BM. Further, the first protective layer 115 may protect the color filters CF and the black matrix BM. Accordingly, in a step of forming a cavity CV in which the liquid crystal molecules LC are injected, it is possible to reduce damage to the color filters CF and the black matrix BM due to an O 2 aching process for finally removing the remainder of a sacrificial layer in the cavity CV. The cavity CV may be formed by removing the sacrificial layer formed on the first protective layer 115 to correspond to each pixel PX, for example, the first sub-pixel SPX 1 and the second sub-pixel SPX 2 , after the covering layer 125 and the third protective layer 130 are formed.

The first protective layer 115 may be formed of at least one of SiNx, SiOx and SiOxNy. Also, a first contact hole th 1 may be formed to expose the drain electrode DE through the first protective layer 115 and the insulating layer 110 . Further, a second contact hole th 2 may be formed to expose the first protrusion CLp 1 of the odd-numbered common lines CL 1 , CL 3 , . . . through the first protective layer 115 , the insulating layer 110 and the gate insulating layer GIL. Further, a third contact hole th 3 may be formed to expose the second protrusion CLp 2 of the even-numbered common lines CL 2 , CL 4 , . . . through the first protective layer 115 , the insulating layer 110 and the gate insulating layer GIL.

The pixel electrode PE includes a first pixel electrode PE 1 formed in a region corresponding to the first sub-pixel SPX 1 and a second pixel electrode PE 2 formed in a region corresponding to the second sub-pixel SPX 2 on the basis of each pixel PX on the substrate 105 (see FIG. 2 ). The first pixel electrode PE 1 and the second pixel electrode PE 2 are physically separated from each other, for example, by the first gate line GL 1 and the first common line CL 1 . The first pixel electrode PE 1 and the second pixel electrode PE 2 are electrically connected to the drain electrode DE of the thin film transistor TFT (see FIG. 5 ), and the same pixel voltage is applied to the first pixel electrode PE 1 and the second pixel electrode PE 2 . The first pixel electrode PE 1 and the second pixel electrode PE 2 may have an area ratio of 1:1.

Each of the first pixel electrode PE 1 and the second pixel electrode PE 2 includes, on the plane, at least one stem electrode PEa, a plurality of branch electrodes PEb extending from the stem electrode PEa, and an extending electrode PEc extending from the end of the stem electrode PEa toward the drain electrode DE (see FIGS. 2 and 5 ). The branch electrodes PEb may be formed to extend in parallel in a set or predetermined direction, and may be spaced from each other at regular intervals. Further, the pixel electrode PE may further include a connection electrode PEd electrically connecting the extending electrode PEc of the first pixel electrode PE 1 to the extending electrode PEc of the second pixel electrode PE 2 . The connection electrode PEd may be electrically connected to the drain electrode DE through the first contact hole th 1 formed in the first protective layer 115 and the insulating layer 110 . The stem electrode PEa and the branch electrodes PEb may be arranged in various shapes without being limited to the shape shown in FIG. 2 . The pixel electrode PE may be formed of a transparent conductive material, e.g., indium tin oxide (ITO) or indium zinc oxide (IZO).

In addition, the second pixel electrode PE 2 of one pixel PX and the first pixel electrode PE 1 of another pixel PX of the pixels PX adjacent to each other in the second direction Y of the substrate 105 are disposed, for example, between the first gate line GL 1 and the second gate line GL 2 to be physically separated from each other.

The common electrode CE is formed to be spaced from the pixel electrode PE on the substrate 105 , for example, on the first protective layer 115 . Accordingly, the cavity CV is formed between the common electrode CE and the pixel electrode PE. The liquid crystal molecules LC are injected into the cavity CV to form the liquid crystal layer LCL. The common electrode CE may be formed of a transparent conductive material, e.g., indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode CE and the pixel electrode PE generate an electric field to control an alignment direction of the liquid crystal molecules LC.

The common electrode CE includes, on the basis of each pixel PX, a first common electrode CE 1 extending in the first direction X to overlap with the first pixel electrode PE 1 , and a second common electrode CE 2 extending in the first direction X to overlap with the second pixel electrode PE 2 (see FIG. 4 ). The first common electrode CE 1 and the second common electrode CE 2 are physically separated from each other while, for example, the first gate line GL 1 and the first common line CL 1 are interposed therebetween. The first common electrode CE 1 and the second common electrode CE 2 may be electrically connected to the first protrusion CLp 1 of the first common line CL 1 and the second protrusion CLp 2 of the second common line CL 2 , respectively, through the second contact hole th 2 and the third contact hole th 3 formed in the first protective layer 115 , the insulating layer 110 and the gate insulating layer GIL. Accordingly, different voltages are applied to the first common electrode CE 1 and the second common electrode CE 2 , respectively, from the first common line CL 1 and the second common line CL 2 . For example, a first common voltage applied to the first common electrode CE 1 may be 7V, and a second common voltage applied to the second common electrode CE 2 may be 8V.

Meanwhile, the second common electrode CE 2 is formed as a single electrode (in one piece) on the second pixel electrode PE 2 of one pixel PX and the first pixel electrode PE 1 of another pixel PX of the pixels PX adjacent to each other in the second direction Y of the substrate 105 . For example, the second common electrode CE 2 is formed as a single electrode (in one piece) on the second pixel electrode PE 2 and the first pixel electrode PE 1 disposed between the first gate line GL 1 and the second gate line GL 2 . In this case, the second common voltage of, e.g., 8V may be applied to the second common electrode CE 2 on the second pixel electrode PE 2 and the first pixel electrode PE 1 disposed between the first gate line GL 1 and the second gate line GL 2 . While an embodiment in which the second common electrode CE 2 is formed as a single electrode on the second pixel electrode PE 2 of one pixel PX and the first pixel electrode PE 1 of another pixel PX of the pixels PX adjacent to each other in the second direction Y of the substrate 105 has been described above, the first common electrode CE 1 may be formed as a single electrode.

The second protective layer 120 is formed on the common electrode CE to protect the common electrode CE. The second protective layer 120 may be formed of at least one of SiNx, SiOx and SiOxNy.

The covering layer 125 includes sidewalls 125 a formed to separate a plurality of pixels PX from each other in the first direction X of the substrate 105 , and a roof 125 b formed above the sidewalls 125 a to connect the sidewalls 125 a (see FIGS. 3 and 4 ). The covering layer 125 may be formed of an organic material. The covering layer 125 may further include a liquid crystal inlet EN formed in the first direction X of the substrate 105 and located in a portion overlapping with the gate lines GL 1 , GL 2 , . . . , GLn. The liquid crystal molecules LC may be injected into the cavity CV through the liquid crystal inlet EN.

The third protective layer 130 is formed on the covering layer 125 to protect the covering layer 125 . The third protective layer 130 may be formed of at least one of SiNx, SiOx and SiOxNy.

The alignment film 135 is formed on the pixel electrode PE and the common electrode CE in the cavity CV. The alignment film 135 may be formed of an alignment material such as polyamic acid, polysiloxane or polyimide.

The liquid crystal layer LCL is formed by injecting liquid crystal molecules into the cavity CV. The liquid crystal molecules may be aligned by the alignment film 135 .

The sealing film 140 is formed to seal a liquid crystal inlet of the cavity CV in the liquid crystal inlet EN (see FIG. 4 ). The sealing film 140 may be formed of a sealing material which does not react with the liquid crystal molecules LC injected into the cavity CV.

The capping layer 145 is formed on the third protective layer 130 , and may serve to planarize and protect the third protective layer 130 and the other configuration located below the third protective layer 130 . The capping layer 145 may be formed of an insulating material.

Although not shown, the liquid crystal display device 100 may further include a sealing layer formed on the capping layer 145 . By forming the sealing layer, it is possible to omit another substrate that is coupled to the substrate 105 on which the thin film transistors are formed in a comparable liquid crystal display device.

In the liquid crystal display device having the above-described structure, the thin film transistor TFT is turned on in response to the gate signal provided through the gate lines GL 1 , GL 2 , . . . , GLn. If the thin film transistor TFT is turned on, the data signal provided through the data lines DL 1 , DL 2 , . . . , DLm is provided to the pixel electrode PE through the thin film transistor TFT, and the common voltage provided through the common lines CL 1 , CL 2 , . . . , CLo is applied to the common electrode CE. Accordingly, an electric field is formed between the pixel electrode PE and the common electrode CE, and the liquid crystal of the liquid crystal layer LCL is driven according to the electric field, thereby displaying an image.

Next, the driving of the liquid crystal display device 100 will be described using (utilizing) one pixel PX.

FIG. 8 is an equivalent diagram of one pixel of FIG. 1 . FIG. 9 is a diagram for explaining voltages applied to the sub-pixels of FIG. 1 . FIG. 10 is a diagram showing the arrangement of voltages applied to the sub-pixels of FIG. 1 . FIG. Ills a diagram showing the polarity of the pixel voltage applied to the sub-pixels and the arrangement of the common electrodes of FIG. 1 . FIG. 12 is a diagram showing an example of the first common voltage applied to the first common electrode of FIG. 1 . FIG. 13 is a diagram showing an example of the second common voltage applied to the second common electrode of FIG. 1 .

Referring to FIG. 8 , one pixel PX may include the thin film transistor TFT, a first liquid crystal capacitor C LC1 , a second liquid crystal capacitor C LC2 , a first storage capacitor C ST1 , a second storage capacitor C ST2 , the first pixel electrode PE 1 (see FIG. 1 ), the second pixel electrode PE 2 (see FIG. 1 ), the first common electrode CE 1 (see FIG. 1 ), and the second common electrode CE 2 (see FIG. 1 ).

The thin film transistor TFT is turned on if a gate-on signal is applied thereto through the first gate line GL 1 . In this case, a data voltage (or a pixel voltage V p ) supplied through the first data line DL 1 is applied to the first pixel electrode PE 1 (see FIG. 1 ) and the second pixel electrode PE 2 (see FIG. 1 ) through the thin film transistor TFT. The pixel voltage V p may be, for example, 15V or 0V.

Then, a first common voltage V com1 is applied to the first common electrode CE 1 of FIG. 1 through the first common line CL 1 , and a second common voltage V com2 different from the first common voltage V com1 is applied to the second common electrode CE 2 of FIG. 1 through the second common line CL 2 . The first common voltage V com1 may be, for example, 7V, and the second common voltage V com2 may be, for example, 8V.

Then, a first voltage corresponding to a difference between the first common voltage V com1 and the pixel voltage V p applied to the first pixel electrode PE 1 of FIG. 1 is applied to the liquid crystal (the first liquid crystal capacitor C LC1 shown equivalently in FIG. 8 ), and a second voltage corresponding to a difference between the second common voltage V com2 and the pixel voltage V p applied to the second pixel electrode PE 2 of FIG. 1 is applied to the liquid crystal (the second liquid crystal capacitor C LC2 shown equivalently in FIG. 8 ). Thus, light is transmitted at a transmittance corresponding to the intensity of a first electrical field corresponding to the first voltage and a second electrical field corresponding to the second voltage. The first storage capacitor C ST1 and the second storage capacitor C ST2 may be used (utilized) as an auxiliary mechanisms to maintain the pixel voltage V p during one frame.

Referring to FIG. 9 , for example, if the pixel voltage V p is 15V, the first common voltage V com1 is 7V and the second common voltage V com2 is 8V, the first voltage may be 8V and the second voltage may be 7V. Accordingly, in one pixel PX, 8V (i.e., voltage of high level H) may be applied to the first sub-pixel SPX 1 , and 7V (i.e., voltage of low level L smaller than the voltage of high level H) may be applied to the second sub-pixel SPX 2 .

FIG. 10 illustrates that the voltage of the high level H and the voltage of the low level L is applied to each of the pixels PX. For this voltage application, the pixel voltage V p has the polarity as shown in FIG. 11 , and the first common electrodes CE 1 to which the first common voltage W com1 (e.g., 7V) is applied and the second common electrodes CE 2 to which the second common voltage V com2 (e.g., 8V) is applied are arranged as shown in FIG. 11 . In FIGS. 10 and 11 , R may refer to a red pixel emitting red light, G may refer to a green pixel emitting green light, and B may refer to a blue pixel emitting blue light. Further, “+” may refer to that the pixel voltage V p is a positive voltage, for example, 15V, relatively higher than the first common voltage V com1 and the second common voltage V com2 , and “−” may refer to that the pixel voltage V p is a negative voltage, for example, 0V, relatively lower than the first common voltage W com1 and the second common voltage V com2 .

As described above, by applying different voltages, i.e., the voltage of the high level H and the voltage of the low level L, to each pixel PX, the alignment direction of the liquid crystal molecules may vary in each pixel PX. Accordingly, the visibility of the liquid crystal display device 100 can be improved.

Meanwhile, if the same voltage is continuously applied to the liquid crystal, charges may be accumulated in the liquid crystal layer including the liquid crystal material. In this case, when the liquid crystal display device 100 is driven, a residual image may be formed on the substrate 105 on which the image is displayed. Thus, it is necessary to change the voltage applied to the liquid crystal material at an arbitrary time. To that end, referring to FIGS. 12 and 13 , in one pixel PX, the first common voltage V com1 may be applied to the first common electrode CE 1 of the first sub-pixel SPX 1 at a swing of 1V (e.g., swing or change from 7V to 8V), and the second common voltage V com2 may be applied to the second common electrode CE 2 of the second sub-pixel SPX 2 at a swing of 1V (e.g., swing or change from 8V to 7V). In this case, the swing of the first common voltage V com1 and the second common voltage V com2 may be achieved at irregular timings, for example, in irregular units of frames, to minimize or reduce degradation of the quality of the image.

Next, the transmittance of the liquid crystal display device according to one embodiment of the present invention will be described.

FIG. 14 is a graph showing a simulation of a voltage difference between the first sub-pixel and the second sub-pixel according to a gray scale in the liquid crystal display device of FIG. 1 .

Referring to FIG. 14 , in the liquid crystal display device 100 of FIG. 1 , a difference between the first voltage (i.e., voltage of the H level) of the first sub-pixel and the second voltage (i.e., voltage of the L level) of the second sub-pixel has a constant value of about 1V or less at a high gray level and a low gray level. At a low gray level, even if a difference between the first voltage of the first sub-pixel and the second voltage of the second sub-pixel is large, the loss of transmittance is not large. However, at a high gray level, the loss of transmittance is small when a difference between the first voltage of the first sub-pixel and the second voltage of the second sub-pixel is small. That is, in the liquid crystal display device 100 according to one embodiment of the present invention, since a difference between the first voltage of the first sub-pixel and the second voltage of the second sub-pixel is about 1V or less at a high gray level, the loss of transmittance is only about 1V or less. Thus, the loss of transmittance may not be recognized with the naked eye at a high gray level.

As described above, in the liquid crystal display device 100 according to one embodiment of the present invention, by forming in one pixel PX the thin film transistor TFT, the first pixel electrode PE 1 and the second pixel electrode PE 2 (to which the same pixel voltage V p is applied), and the first common electrode CE 1 and the second common electrode CE 2 (to which different common voltages V com1 and V com2 are applied) on one substrate, it is possible to increase an aperture ratio while improving the visibility with a simple structure.

Further, in the liquid crystal display device 100 according to one embodiment of the present invention, by controlling a difference between the first voltage (applied to the first sub-pixel SPX 1 ) and the second voltage (applied to the second sub-pixel SPX 2 ) in one pixel PX to about 1V or less, the display quality can be improved by reducing or minimizing the loss of transmittance, for example, the loss of transmittance at a high gray level.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the example embodiments without substantially departing from the principles of the present invention. Therefore, the disclosed example embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation. The scope of the present invention is only defined by the following claims, and equivalents thereof.