Method for a current mode buck-boost converter

The present document relates to DC-to-DC converters. In particular, the present document relates to current mode buck-boost converters with isolated buck and boost pulses.

Buck-Boost converters are used in applications where the desired output voltage (e.g. 3.3V) can be lower or higher than the input voltage (e.g. Vin=2.5V-5.5V). FIG. 1 prior art gives an example of a typical buck-boost switch configuration. This configuration is called non-inverting or positive buck-boost converter as the output voltage has the same sign as the input voltage.

In basic operating principle referring to FIG. 1 prior art, when both the switches 10 and 11 are in phase-1, the inductor L is connected to supplies and is charged with current and, when both the switches 10 and 11 are in phase-2, the inductor current I L charges the output capacitor 12 . The output voltage V versus input voltage V g as a function of duty cycle in this mode of operation is given by the equation (1):

Thus the converter is capable of achieving output voltages lower or higher than the input voltage.

FIG. 2 prior art gives the topology of an output stage of a synchronous buck-boost controller with integrated switches.

Referring back to basic operation of FIG. 1 prior art, in phase-1 switches M 1 and M 3 will be ON; switches M 2 and M 4 will be OFF; and in phase-2 switches M 2 and M 4 will be ON and switches M 1 and M 3 will be OFF.

Comparing the basic Buck-Boost operation with a typical Buck or Boost converter, we can list the following disadvantages:

4 switches change state at each cycle, thus switching loss is 2 times that of a typical Buck or Boost converter The average inductance current is significantly higher than the load current, given as:

I L =I LOAD /(1− D )(e.g. when D= 0.5, V in =V out , I L =2× I LOAD ),

which leads to

an increase in inductor current increase in resistive losses (e.g. for D=0.5 example, losses due to the equivalent series resistance of the inductor (R ESR,L ) will be 4 times that of a Buck converter.)

At phase-1 only the capacitor is sourcing the load, thus a low equivalent series resistance (ESR) of the capacitor is needed. Higher current ripple on the inductor.

The mentioned disadvantages can be reduced if we use separated Buck and Boost pulses, which means in a given cycle, either Buck switches M 1 and M 2 OR Boost switches M 3 and M 4 will be switching. During Buck mode switching M 3 will be OFF and M 4 will be ON, likewise during Boost mode switching M 1 will be ON and M 2 will be OFF.

An example of a Buck-Boost converter utilizing “separated Buck and Boost pulses” using voltage mode control is disclosed by U.S. Pat. No. 6,166,527 (to Trevor W. Barcelo). FIG. 3 prior art shows this implementation, wherein the control voltage 30 is compared with two adjacent saw tooth signals wherein boost signal 31 is fed into boost comparator 34 and buck signal 32 is fed into buck comparator 33 .

If the control voltage 30 is low, it will only be crossing the buck saw tooth signal 32 and only Buck switching will occur. Similarly if the control voltage is high, it will only be crossing the boost saw tooth signal 31 and only Boost switching will occur. An example of switching versus changing control voltage is given by FIG. 4 a illustrating PWM pulse generation for buck and boost operation using one control signal V ctrl 40 and two saw tooth signals.

The following parameters are used in FIGS. 4 a and 4 b:

G 1 is the buck switch control signal, which becomes low when the buck sawtooth crosses control voltage 40 .

G 2 is the boost switch control signal, which becomes low when the boost sawtooth crosses control voltage 42 .

VLx and VHx are typically defined by design specifications—e.g. input voltage range.

A similar technique is using two-shifted control voltages and a single saw tooth signal, as illustrated in FIG. 4 b illustrating PMW pulse generation for buck and boost operation using two control signals V buck _ ctrl 41 and V boost _ ctrl 42 and a single saw tooth signal. When the V buck _ ctrl 41 control signal crosses the saw tooth signal, Buck switching will occur, similarly when the V boost _ ctrl 42 control signal crosses the saw tooth signal, Boost switching takes place. In FIG. 4 b the amplitude of the saw tooth signal is equal to the control voltage shift. Thus in a given cycle either a Buck or Boost switching will occur.

As in Buck or Boost converters, current mode control (CMC) can also be used in Buck-Boost converters. And though CMC is more desirable for most applications, it has serious challenges if separated Buck and Boost pulses are required.

There have been examples of current mode control (CMC) Buck-Boost converters utilizing separated Buck and Boost pulses as disclosed in (Ma, Yanzhao, Jun Cheng, and Guican Chen. “A high efficiency current mode step-up/step-down DC-DC converter with smooth transition.” In ASIC (ASICON), 2011 IEEE 9th International Conference on, pp. 108-111. IEEE, 2011) and in (Ehrhart, Andreas, Bernhard Wicht, Moris Lin, Yung-Sheng Huang, Yu-Huei Lee, and Ke-Horng Chen “Adaptive Pulse Skipping and Adaptive Compensation Capacitance Techniques in Current-Mode Buck-Boost DC-DC Converters for Fast Transient Response”).

In both examples above the decision on staying in the Buck region or in the Boost region is given by checking the duty cycle as e.g. in the Ehrhardt et al. publication changing from Buck to Boost mode is decided when D Buck >90% (in the next switching cycle, Boost switching will take place), and changing from Boost to Buck mode is decided when D Boost <10%.

There is a serious disadvantage of changing modes with this technique, for example when changing from Buck mode to Boost mode, it will take significant time for the loop filter to settle to normal operation, which results in unacceptable output transients.

Furthermore another severe problem of prior art buck-boost converters is output voltage overshoot after mode changes.

A principal object of the present disclosure is to reduce switching losses of buck-boost converters.

A further principal object of the disclosure is to reduce resistive losses of buck-boost converters.

A further object of the disclosure is to avoid requiring a low ESR capacitor only.

A further object of the disclosure is to reduce current ripple of an inductor current.

A further object of the disclosure is to avoid output voltage overshoot of a buck-boost converter.

Furthermore an objective of the disclosure is to achieve a fast mode change from buck to boost mode and vice versa hence avoiding unacceptable output transients.

Moreover an objective of the disclosure is utilizing a Buck/Boost mode decision method with continuous control voltage for Buck and Boost mode therefore eliminating transients in the control loop between modes.

Another object of the disclosure is to suppress sub-harmonic oscillation of the buck/boost converter.

In accordance with the objects of this disclosure a method to improve performance of buck-boost converters has been achieved. The method disclosed comprises the steps of: (1) providing a buck-boost regulator configured to current sensing and to generating a slope ramp for a buck-side comparator, comprising an error amplifier, a buck mode comparator, a boost mode comparator, means to generate a control voltage of a boost-side comparator, and means to generate a buck mode duty cycle, (2) utilizing current mode control for the buck-boost converter, (3) using separated buck mode and boost mode pulses, and (4) utilizing a buck-boost mode decision method with a continuous control voltage for both modes.

In accordance with the objects of this disclosure a buck-boost converter with improved performance capable of generating separate Buck and Boost pulses, operating with current mode control and having a continuous control signal has been achieved. The buck-boost converter disclosed firstly comprises: a circuitry capable of current sensing and slope ramp generation of a buck-side comparator, a circuitry capable of error amplification comprising a loop filter, generating a control voltage, and operating a compensation network, and a circuitry capable of controlling a boost side comparator in relation to a buck mode control voltage according to an equation: V c,Boost =V c,Buck −ΔV c , wherein V c,Boost is a boost mode control voltage, V c,Buck is a buck mode control voltage, and ΔV c defines a reference threshold. Furthermore the buck-boost converter comprises a buck-side switching means capable of generating a buck duty cycle, a buck-side switch capable of generating buck pulses, and a circuitry capable of ensuring that the buck-side switch is ON during Boost mode. Moreover the buck-boost converter comprises a boost side switch capable of generating boost pulses, and a circuitry capable of sampling an output of said a buck-side switching means capable of generating a buck duty cycle in order to comparing the buck duty cycle with a reference buck duty cycle configured to decide whether a next pulse will be a Buck pulse or a Boost pulse.

The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein

FIG. 1 prior art shows a non-inverting buck-boost converter.

FIG. 2 prior art depicts a non-inverting buck-boost converter with integrated switches.

FIG. 3 prior art depicts a voltage mode control of a buck-boost converter.

FIG. 4 a prior art shows PMW pulse generation for buck and boost operation using one control signal and two saw tooth signals.

FIG. 4 b prior art shows PMW pulse generation for buck and boost operation using two control signal and one saw tooth signal.

FIG. 5 a shows a block diagram of a preferred embodiment of a buck-boost converter disclosed.

FIG. 5 b shows a timing diagram of comparing the buck duty cycle with a reference to decide whether the next pulse will be a Buck pulse or a Boost pulse.

FIG. 6 illustrates simulation results of the buck-boost converter operating in buck mode.

FIG. 7 shows simulation results of the buck-boost converter operating in boost mode.

FIG. 8 illustrates simulation results for wherein Vin is close to Vout and separated Buck and Boost pulses are observed.

FIG. 9 shows a flowchart of a method to improve the performance of buck-boost converters.

Methods and circuits are disclosed to achieve buck-boost converters with current mode control (CMC) and separated buck and boost pulses. If switching in buck mode and the buck duty cycle D BUCK is greater than a set reference duty cycle D SET , then in the next cycle boost mode switching will occur. Typical values for the reference duty cycle D SET may be between about 80 and 90%, depending on system requirements.

Furthermore if switching in boost mode and D Buck <D set , then in the next cycle Buck mode switching will occur. It is possible to track Buck comparator output and the related duty cycle, which is not in effect during Boost mode operation. Thus mode change decision will only be dependent on a single input D Buck .

Moreover the control loop of the buck-boost converters disclosed will incorporate a single loop filter and error amplifier, wherein control voltages for a buck comparator and a boost comparator will be related and defined with the following formula:

V c,Buck =V c,Boost +ΔV c

FIG. 5 a shows a block diagram of the principal features of a preferred embodiment of the disclosure. The buck boost converter disclosed comprises circuitry 51 to input a current sense and slope ramp to a buck-side comparator 50 , an error amplifier and compensation network 52 , a circuitry 53 with the control voltage of Boost-side comparator, related to Buck control voltage with V c,Boost =V c,Buck −ΔV c , which is a key feature of the disclosure, a circuitry 54 with a Buck side set- and reset flip-flop (SR_FF) 540 to generate a Buck duty cycle, a circuitry 55 to ensure that a buck switch 560 is ON during Boost mode, a circuitry 56 for current sense and buck switch 560 , a circuitry 57 for a Boost side reset-set flip-flop (RSFF) 570 to generate Boost duty cycle, a Boost switch 571 which is OFF during buck mode, and a circuitry 58 comprising two D-type flip-flops (FF) 580 and 581 to sample Buck FF output at points of time t=D set ·T, (e.g. comparing buck duty cycle with 0.9, wherein T signifies the cycle period), and decide whether the next pulse will be a Buck pulse or a Boost pulse. RS flip flop 570 and D-type flip-flops 580 and 581 may alternately be other flip-flop types.

FIG. 5 b shows a timing diagram of comparing the buck duty cycle with “set09” to sample “buck FFout” to decide whether the next pulse will be a Buck pulse or a Boost pulse.

Thus the system disclosed is capable of generating separated Buck and Boost pulses, operating with current mode control and having a continuous control signal.

The following paragraph explains a simple technique to define delta voltage ΔV c .

Assuming that the same control voltage has been generated for generation of a, for example, 90% duty cycle D for Buck and, again for example, 10% duty cycle D for Boost (another maximum duty cycle D for buck and minimum duty cycle D for Boost can be defined, as needed).

For current mode operation, at the time the Buck comparator changes output or when duty cycle D=0.9, in this example,

V C , buck = I sense , max , buck ⁢ R sense + D buck ⁢ V ramp , buck I sense , max , buck = I LOAD + V i ⁢ ⁢ n - V out L ⁢ D buck ⁢ T

and at the time the Boost comparator changes output or when duty cycle D=0.1, in this example

V C , boost = I sense , max , boost ⁢ R sense + D boost ⁢ V ramp , boost I sense , max , boost = I LOAD ( 1 - D boost ) + V i ⁢ ⁢ n L ⁢ D boost ⁢ T ,

where T is the cycle period. For the mentioned conditions, and for the sake of simplicity, it has been assumed that the boost duty cycle D boost is close to 0 and Vin is close to Vout, I sense,max in Buck and Boost modes will be similar, and

V C,buck −V C,boost =0.9 V ramp,buck −0.1 V rampboost =ΔV C

Thus we can relate both control voltages V cbuck and V cboost , wherein voltage shift ΔV C is implemented as a level shifter, e.g., as an ideal DC source in the block diagram of FIG. 5 a . The DC voltage shift can be implemented in various ways, for example as an IxR voltage drop or employing a level shifter block in the block diagram of FIG. 5 a.

Although other formulas can be utilized for ΔV C , a value far from optimal operation will create larger output voltage ripples when switching between modes which may lead to low frequency oscillation.

FIG. 6 illustrates simulation results for input voltage Vin=4.5V, output voltage Vout=3V and load current I LOAD =1 Å, switching frequency f SW =1 MHz. Since Vin>Vout, the system works only in Buck mode, with duty cycle D buck =0.76. As D buck <0.9 the Boost Nextsignal (bottom in FIG. 5 .) is logic zero, hence no Boost cycle is observed.

From top to bottom FIG. 6 shows the output voltage Vout, control voltage V cbuck , V rampbuck , the switching of the buck high side switch 560 , of the boost low side switch 571 and the buck/boost state decision signal BoostNext. All these signals can be located in the block diagram of FIG. 5 a . As mentioned above no boost cycle is observed.

FIG. 7 shows the simulation results for Vin=2.5V, Vout=3V and I LOAD =1 Å. Vin<Vout and the system works only in Boost mode, with D buck =1. As D buck >0.9 the BoostNext signal (bottom in FIG. 5 .) is always logic one, hence only Boost cycle is observed. During Boost mode, Buck high side switch is ON.

FIG. 8 shows the simulation results for Vin=3.5V, Vout=3V and I LOAD =1 Å. This is the case where the method disclosed shows the improvement versus prior art for system operation.

Vin is close to Vout and separated Buck and Boost pulses are observed—in this case one Boost cycle is followed by two Buck cycles. The Buck/Boost cycle combinations may vary with different operating conditions.

At t=191 us (start of frame), a Boost cycle takes place. After −0.8 us (0.8×T, f SW =1 MHz) V Cbuck crosses V ramp,buck =1 and hence V reset1 is set. V reset1 is set when V Cbuck crosses V ramp,buck As D buck <0.9 the next cycle is a Buck cycle. V reset2 is reset when V ramp,boost is lower than V cboost .

During this cycle D buck =0.86 and the next cycle is also Buck.

During the second Buck cycle D is 1 and the next cycle will be a Boost cycle.

Furthermore the circuit of FIG. 5 a has the ability to suppress sub-harmonic oscillation. Buck-Boost converters encounter high duty cycle operation in Buck mode, which requires extreme values for slope compensation for CMC (V in is typically close to V out ). However with this topology a high duty cycle Buck will be followed by a low duty cycle Boost cycle, which will force the system back to non-subharmonic operation.

FIG. 9 shows a flowchart of a method to improve buck-boost regulator performance.

A first step 90 depicts a provision of a buck-boost regulator configured to current sensing and to generate a slope ramp for a buck-side comparator, comprising an error amplifier, means to generate a control voltage of a boost-side comparator, and means to generate a buck mode duty cycle. The next step 91 shows utilizing current mode control for the buck-boost converter. The following step 92 describes using separated buck mode and boost mode pulses and the last step 93 depicts utilizing a buck-boost mode decision method with a continuous control voltage for both modes.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.