Semiconductor memory device and method of controlling the same

This application is based on and claims the benefit of priority from prior U.S. Provisional Patent Application No. 61/951,952, filed on Mar. 12, 2014, the entire contents of which are incorporated herein by reference.

Embodiments described in the present specification relate to a semiconductor memory device and a method of controlling the same.

In a nonvolatile semiconductor memory device such as a NAND type flash memory, a memory cell includes a control gate and a charge accumulation layer, and stores as data a magnitude of a threshold voltage of the memory cell that changes according to a charge accumulated in the charge accumulation layer. It is known that by setting a plurality of threshold voltages in the memory cell of the above-described semiconductor memory device, the semiconductor memory device is made capable of multi-level storage.

FIG. 1 is an overall block diagram of a semiconductor memory device according to a first embodiment.

FIG. 2 is a circuit diagram showing a detailed configuration of a memory cell array.

FIG. 3 includes schematic views showing threshold voltages of a memory cell during data write.

FIG. 4 is a graph showing a relationship between a verify voltage VLM in a lower page write and a fail bit number which is the number of memory cells that have failed in write.

FIG. 5 is a flowchart showing a data write method of the semiconductor memory device according to the first embodiment.

FIG. 6 is a graph showing threshold distributions of the memory cell after data write.

FIG. 7 is a flowchart showing a data write method of a semiconductor memory device according to a second embodiment.

FIG. 8 includes schematic views showing threshold voltages of a memory cell during data write of a semiconductor memory device according to another embodiment.

FIGS. 9A to 9B include cross-sectional schematic views each showing a configuration of the semiconductor memory device according to the first through second embodiments.

A semiconductor memory device according to an embodiment comprises: a nonvolatile memory cell capable of multi-level storage; and a control circuit that performs write control on the memory cell. The control circuit executes: a first write operation that performs a write on the memory cell to obtain a certain intermediate voltage distribution while performing a verify operation on the memory cell using a first verify voltage; a second write operation, executed after the first write operation, that performs a write on the memory cell having the intermediate voltage distribution to obtain a final voltage distribution corresponding to write data to the memory cell while performing a verify operation on the memory cell using a second verify voltage; and a change operation that changes a value of the first verify voltage according to the number of times of writes and the number of times of erases on the memory cell.

Embodiments will be described in detail below with reference to the drawings.

First Embodiment

First, a first embodiment will be described with reference to FIGS. 1 to 6 . FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to the first embodiment. The present semiconductor memory device is a NAND type flash memory adopting a four-level storage system. The present semiconductor memory device comprises a memory cell array 1 having a plurality of data-storing memory cells MC disposed in a matrix therein. The memory cell array 1 includes a plurality of bit lines BL and a plurality of word lines WL that intersect each other, and has the memory cell MC disposed at each of intersections of said bit lines BL and word lines WL. The memory cell MC has a stacked structure of a floating gate electrode which functions as a charge accumulation layer that accumulates a charge, and a control gate electrode which is connected to the word line WL. The memory cell MC is configured capable of electrically rewriting data by injection or release of charge into/from the floating gate electrode.

Connected to the memory cell array 1 are a column control circuit 2 for controlling a voltage of the bit line BL, and a row control circuit 3 for controlling a voltage of the word line WL. The column control circuit 2 reads data from the memory cell MC via the bit line BL and performs write of data to the memory cell MC via the bit line BL. The row control circuit 3 applies a voltage for write, read, and erase of data, to a gate electrode of the memory cell MC, via the word line WL.

Connected to the column control circuit 2 is a data input/output buffer 4 . Data of the memory cell MC read by the column control circuit 2 is outputted to an external host 9 from a data input/output terminal (external I/O) via the data input/output buffer 4 . Moreover, write data inputted to the data input/output terminal (external I/O) from the external host 9 is inputted to the column control circuit 2 via the data input/output buffer 4 , and is written to a designated memory cell MC.

Connected to the data input/output buffer 4 are an address register 5 and a command I/F 6 . The address register 5 outputs address information inputted from the data input/output buffer 4 , to the column control circuit 2 and the row control circuit 3 . The command I/F 6 is connected to a state machine 7 and the external host 9 , and sends/receives a control signal between these blocks. Connected to the state machine 7 are the memory cell array 1 , the column control circuit 2 , the row control circuit 3 , and the data input/output buffer 4 . The state machine 7 generates an internal control signal for controlling the memory cell array 1 , the column control circuit 2 , the row control circuit 3 , and the data input/output buffer 4 , based on an external control signal inputted from the host 9 via the command I/F 6 . The above-described various kinds of circuits including the column control circuit 2 and the row control circuit 3 function as a control circuit that controls a data write operation during data write to the later-described memory cell MC.

FIG. 2 is a circuit diagram showing a configuration of a part of the memory cell array 1 shown in FIG. 1 . The memory cell array 1 includes a plurality of memory units MU. The memory unit MU is configured from M (for example, M=16) memory cells MC_ 0 to MC_M−1 connected in series, and a first select gate transistor S 1 and a second select gate transistor S 2 connected to the two ends of these series-connected memory cells MC_ 0 to MC_M−1. One end of the first select gate transistor S 1 is connected to the bit line BL, and one end of the second select gate transistor S 2 is connected to a source line SRC. That is, the memory cells MC are arranged in series sandwiched by a plurality of select transistors (S 1 and S 2 ), at a region of intersection of the word line WL and the bit line BL.

Word lines WL_ 0 to WL_M−1 are connected to the control gate electrodes of the memory cells MC_ 0 to MC_M−1. The plurality of memory units MU are disposed in a direction of formation of the word line WL, and form one block BLKi. In the memory cell array 1 , erase of data is performed in a block BLK unit. Moreover, the plurality of memory cells MC commonly connected to one word line WL (reference symbol PG) forms one page or a plurality of pages. In the memory cell array 1 , write and read of data is performed simultaneously on the memory cells along one word line.

Next, an outline of a data storage system of the nonvolatile semiconductor memory device will be described. The nonvolatile semi conductor memory device is configured such that a threshold voltage of the memory cell MC can have four kinds of distributions. FIG. 3 , in a to c thereof, includes views showing a relationship between change in a threshold voltage distribution of the memory cell MC and two-bit four-level data stored in the memory cell MC during data write of the nonvolatile semiconductor memory device. The four-level data are specified by, for example, a negative threshold voltage distribution (erase distribution) E having a lowest level of voltage level, and threshold voltage distributions A, B, and C having higher voltage levels than that of the threshold voltage distribution E. In the present embodiment, the threshold voltage distributions E, A, B, and C are assumed to correspond to data “11”, “01”, “10”, and “00”, respectively.

First, as shown in a of FIG. 3 , before write, the memory cells included in the write-target block (refer to BLKi of FIG. 2 ) are all set to the erase state threshold voltage distribution (E) by data erase. This data erase is performed by, for example, applying a positive erase voltage (Vera, not illustrated in FIG. 3 ) to a well where the memory cell array 1 is formed, and setting a potential of all word lines WL of the selected block to 0 V, thereby releasing electrons from the floating gates of all memory cells MC.

Next, as shown in b of FIG. 3 , some of the memory cells MC in the erase state (E) undergo a lower page write (Lower Page Program) that raises their threshold voltage to an intermediate voltage distribution (LM). Then, a verify operation for verifying completion of the lower page write is performed by setting a verify voltage to a voltage VLM and applying said voltage between the gate and the source of the memory cell MC. If the memory cell MC conducts due to the verify voltage VLM, then write fail (FAIL) is determined, and if the memory cell MC does not conduct due to the verify voltage VLM, then write pass (PASS) is determined. As a result, the threshold voltage of the memory cell MC that has undergone the lower page write rises and undergoes transition to the intermediate threshold voltage distribution (LM).

Next, as shown in c of FIG. 3 , an upper page write (Upper Page Program) is performed that raises some of the memory cells MC in the erase state (E) to the threshold voltage distribution A and raises the memory cell MC in the intermediate voltage distribution (LM) to the threshold voltage distribution B or C. Then, similarly to in the case of the lower page write, a verify operation for verifying completion of the upper page write is performed by setting a verify voltage to, respectively, VA, VB, and VC and applying said voltage between the gate and the source of the memory cell MC. As a result, the threshold voltage of the memory cell MC that has undergone the upper page write rises and undergoes transition to any one of the threshold voltage distributions A, B, and C.

In the above data write operation, the selected word line to which one page of write-target memory cells MC are connected is provided with a write voltage VPGM (about 20 to 28 V), and another non-selected word line is provided with a write pass voltage Vpass (about 8 to 10 V). On that basis, depending on write data, the bit line electrically connected to the write-target memory cell MC is selectively provided with a ground voltage Vss (in the case of “0” write) and a power supply voltage VDD (in the case of “1” write). As a result, electrons are selectively injected into the floating gate of the memory cell MC.

In the case of “0” write that raises the threshold voltage, the ground voltage Vss provided to the bit line is transmitted to a channel of the NAND cell unit via the first select gate transistor S 1 set to a conductive state. As a result, when the write voltage VPGM is provided, a tunnel current flows between the channel and the floating gate, and electrons are injected into the floating gate.

On the other hand, in the case of “1” write that does not raise the threshold voltage (write inhibit), the bit line is provided with the power supply voltage VDD. In this state, even if the power supply voltage VDD is provided to the first select gate transistor S 1 , the channel of the NAND cell unit is charged to VDD-Vt (Vt is the threshold voltage of the first select gate transistor S 1 ) to be in a floating state. As a result, when the write voltage VPGM is provided, the cell channel is boosted by capacitive coupling, and electron injection into the floating gate does not occur.

During read of data, read voltages RA, RB, and RC which are voltages between upper limits and lower limits of each of the threshold voltage distributions E to C are applied between the gate and the source of the read-target selected memory cell MC. Moreover, a read pass voltage V READ (refer to c of FIG. 3 ) which is larger than the upper limit of the threshold voltage distribution C is applied between the gate and the source of a non-read-target non-selected memory cell MC. The read pass voltage V READ is a voltage that has a value larger than that of the upper limit of the threshold voltage distribution C and that enables the memory cell MC to be set to a conductive state irrespective of held data of the memory cell MC.

As described above, the threshold voltage distribution of the write-completed memory cell MC eventually becomes any one of E, A, B, and C (refer to c of FIG. 3 ). As previously mentioned, these threshold voltage distributions correspond to data “11 (E)”, “01 (A)”, “10 (B)”, and “00 (C)”, respectively. That is, two-bit data of one memory cell MC is configured from lower page data and upper page data, and when notated as data “*@”, “*” represents the upper page data, and “@” represents the lower page data.

FIG. 4 is a graph showing a relationship between the verify voltage VLM in the lower page write in b of FIG. 3 and a fail bit number which is the number of memory cells that have failed in write. Here, write and erase of data to the memory cell is assumed to be one cycle. FIG. 4 illustrates respective graphs for when 0 cycles have been completed (Fresh), when 1000 cycles have been completed (W/E 1 k), when 2000 cycles have been completed (W/E 2 k), and when 3000 cycles have been completed (W/E 3 k).

As shown in FIG. 4 , each of the graphs has a downwardly directed convex shape, hence an optimum verify voltage at which the fail bit number becomes a minimum can be calculated based on said graphs. For example, when 0 cycles have been completed, the optimum verify voltage is VLM=V 0 . Similarly, the optimum voltages when 1000 cycles have been completed, when 2000 cycles have been completed, and when 3000 cycles have been completed are VLM=V 1 , VLM=V 2 , and VLM=V 3 , respectively. A magnitude relationship of each of the verify voltages is V 0 <V 1 <V 2 <V 3 .

The reason that the optimum verify voltage changes as in FIG. 4 is thought to be because as the number of times of writes and erases to the memory cell increases, it becomes easier for the threshold voltage of the memory cell to lower during data hold, and it becomes easier for write fail to occur. Such a phenomenon becomes a problem particularly when forming the intermediate voltage distribution (VLM) on the way to a final voltage distribution corresponding to write data. For example, in such cases as when a power source supply to the semiconductor memory device gets interrupted during the course of data write, the need arises to maintain the intermediate voltage distribution until re-start of write. In view of the above, continuing to employ a uniform verify voltage regardless of a value of the write cycle results in the fail bit number being increased in the lower page write for forming the intermediate voltage distribution, and is undesirable.

FIG. 5 is a flowchart showing a data write method of the semiconductor memory device according to the first embodiment. First, the control circuit determines whether a cycle number corresponding to the number of times of writes and the number of times of erases is a certain number of times or more, or not (step S 10 ). Said step may be implemented by, for example, providing in the control circuit a counter that counts the above-described cycle number, and directly counting said cycle number.

If it is determined in step S 10 that the number of times of writes and the number of times of erases is a certain value or more (step S 10 =YES), then the control circuit changes the verify voltage VLM for obtaining the intermediate voltage distribution. Said step may be executed by, for example, obtaining the optimum verify voltage from the write cycle number based on a table (not illustrated) corresponding to the graph of FIG. 4 . For example, it is possible to respectively set VLM=V 1 , VLM=V 2 , and VLM=V 3 when the number of times of writes is 1000 times or more, 2000 times or more, and 3000 times or more. Then, the control circuit executes a data write operation to the memory cell using the changed verify voltage (step S 12 ).

On the other hand, if it is not determined in step S 10 that the number of times of writes is the certain value or more (step S 10 =NO), then the control circuit executes the data write operation using the verify voltage V 0 already set, without changing the verify voltage VLM (step S 12 ).

FIG. 6 is a graph showing threshold distributions of the memory cell after data write. As the verify voltage becomes larger, at V 0 , V 1 , V 2 , and V 3 , a peak of the threshold voltage distribution is also found to shift to a high voltage side. As a result, a margin for data retention expands, hence increase in the fail bit number can be suppressed.

Due to the semiconductor memory device according to the first embodiment, in the write operation for obtaining the intermediate voltage distribution in a process on the way to obtaining the final voltage distribution corresponding to write data, the verify voltage VLM is changed based on the number of times of writes and the number of times of erases. As a result, increase in the fail bit number can be suppressed and hold characteristics of data can be improved.

Note that another possible method of suppressing increase in the fail bit number is to increase a value of the write voltage applied when forming the intermediate voltage distribution LM. However, in said method, sometimes, a width of the threshold voltage distribution gets broadened (refer to FIG. 6 ), and there is an effect on the subsequent write operation. In contrast, in the case of the write method according to the first embodiment, the verify voltage, not the write voltage, is changed, hence increase in the fail bit number can be suppressed while the width of the threshold voltage distribution is kept narrow.

Second Embodiment

Next, a second embodiment will be described with reference to FIGS. 7 and 8 . A semiconductor memory device according to the second embodiment has a configuration and a data storage system that are the same as those of the first embodiment ( FIGS. 1 to 3 ), but has a write operation procedure that differs from that of the first embodiment. Specifically, the second embodiment differs in performing a pre-write and a pre-verify to the memory cell. This will be described in detail below.

FIG. 7 is a flowchart showing a data write method of the semiconductor memory device according to the second embodiment. First, the control circuit implements the pre-write on the memory cell in the erase state (E) (step S 20 ). A pre-write refers to performing a write on a “0” write-target memory cell using a write voltage which is smaller than a voltage (word line voltage VPGM and bit line voltage VSS) used during an ordinary data write. As a result, the threshold voltage of the memory cell that has undergone the pre-write rises by an amount of a voltage width which is smaller than in the ordinary data write.

Next, the control circuit implements the pre-verify operation on the memory cell that has undergone the pre-write in step S 20 (step S 21 ). A pre-verify operation refers to performing a verify using a verify voltage which is lower than the verify voltage VLM during the lower page write. By performing the pre-write and the pre-verify on the write-target memory cell as in steps S 20 to S 21 , the threshold voltage distribution of the memory cell can be caused to undergo transition from the erase state (E) to a high voltage side (LM side). This makes it possible to suppress a shift amount of the threshold voltage distribution of the “0” write-target memory cell during the lower page write. As a result, excessive write to the memory cell can be suppressed.

Next, the control circuit determines whether the number of memory cells that have passed the pre-verify in step S 21 is a certain proportion or more, or not (step S 22 ). Now, as the number of times of writes and the number of times of erases to the memory cell increases, the shift amount of the threshold voltage in one time of write increases, and the number of memory cells that pass the pre-verify increases. Accordingly, if the number of memory cells that have passed the pre-verify is a certain proportion or more (step S 22 =YES), then the control circuit performs change of the verify voltage VLM in the same way as in the first embodiment (step S 11 of FIG. 5 ) (step S 23 ). Then, the control circuit executes the data write operation similarly to in the first embodiment (step S 24 ).

On the other hand, if the number of memory cells that have passed the pre-verify is not a certain proportion or more (step S 22 =NO), then the control circuit executes the data write operation using the verify voltage already set, without changing the verify voltage (step S 24 ).

Due to the semiconductor memory device according to the second embodiment, change of the verify voltage VLM is performed based on the proportion of memory cells that have passed the pre-verify. Therefore, change of the verify voltage can be performed substantively based on the number of times of writes and the number of times of erases, without directly counting the number of times of writes and the number of times of erases. As a result, increase in the fail bit number can be suppressed and hold characteristics of data can be improved in the same way as in the first embodiment.

Additionally due to the second embodiment, implementing the pre-write and the pre-verify makes it possible to suppress the shift amount of the threshold voltage during the lower page write. As a result, excessive write can be suppressed and yield can be improved in the process of forming the intermediate voltage distribution.

In the first through second embodiments, description proceeded taking as an example a memory cell capable of four-level storage. However, said embodiments can be similarly applied to any multi-level storage memory cell that forms an intermediate voltage distribution during data write. This will be described below.

FIG. 8 includes schematic views showing threshold voltages of a memory cell during data write of a semiconductor memory device according to another embodiment. The semiconductor memory device according to said embodiment is configured such that a threshold voltage of the memory cell MC can have eight kinds of distributions. FIG. 8 , in a to d thereof, includes views showing a relationship between change in a threshold voltage distribution of the memory cell MC and three-bit eight-level data stored in the memory cell MC during data write of the nonvolatile semiconductor memory device. The eight-level data are specified by, for example, a negative threshold voltage distribution (erase distribution) Er having a lowest level of voltage level, and threshold voltage distributions A, B, C, D, E, F, and G having higher voltage levels than that of the threshold voltage distribution Er. In the present embodiment, the threshold voltage distributions Er and A to G are assumed to correspond to data in the following way, namely Er=“111”, A=“011”, B=“101”, C=“001”, D=“110”, E=“010”, F=“100”, and G=“000” (refer to d of FIG. 8 ).

First, as shown in a of FIG. 8 , before write, the memory cells included in the write-target block (refer to BLKi of FIG. 2 ) are all set to the erase state threshold voltage distribution (Er) by data erase. This data erase is performed by, for example, applying a positive erase voltage (Vera, not illustrated in FIG. 8 ) to a well where the memory cell array 1 is formed, and setting a potential of all word lines WL of the selected block to 0 V, thereby releasing electrons from the floating gates of all memory cells.

Next, as shown in b of FIG. 8 , some of the memory cells in the erase state (Er) undergo a lower page write (Lower Page Program) that raises their threshold voltage to an intermediate voltage distribution (LM 1 ). Then, a verify operation for verifying completion of the lower page write is performed by setting a verify voltage to a voltage VLM 1 and applying said voltage between the gate and the source of the memory cell. If the memory cell conducts due to the verify voltage VLM 1 , then write fail (FAIL) is determined, and if the memory cell does not conduct due to the verify voltage VLM 1 , then write pass (PASS) is determined. As a result, the threshold voltage of the memory cell that has undergone the lower page write rises and undergoes transition to the intermediate threshold voltage distribution (LM 1 ).

Next, as shown in c of FIG. 8 , a middle page write (Middle Page Program) is performed that raises some of the memory cells in the erase state (Er) to an intermediate voltage distribution LM 2 and causes the memory cell in the threshold voltage distribution LM 1 to undergo transition to intermediate voltage distributions LM 3 or LM 4 . Then, similarly to in the case of the lower page write, a verify operation for verifying completion of the middle page write is performed by setting a verify voltage to, respectively, VLM 2 , VLM 3 , and VLM 4 and applying said voltage between the gate and the source of the memory cell. As a result, the threshold voltage of the memory cell that has undergone the middle page write rises and undergoes transition to any one of the threshold voltage distributions LM 2 , LM 3 , and LM 4 .

Next, as shown in d of FIG. 8 , an upper page write (Upper Page Program) is performed that raises some of the memory cells in the erase state (Er) to the threshold voltage distribution A and causes the memory cell in the intermediate voltage distributions LM 2 to LM 4 to undergo transition to any one of the threshold voltage distributions B to G. More specifically, the threshold voltage distributions B and C are generated from the threshold voltage distribution LM 2 , the threshold voltage distributions D and E are generated from the threshold voltage distribution LM 3 , and the threshold voltage distributions F and G are generated from the threshold voltage distribution LM 4 . Then, a verify operation for verifying completion of the upper page write is performed by setting a verify voltage to, respectively, VA to VG and applying said voltage between the gate and the source of the memory cell. As a result, the threshold voltage of the memory cell that has undergone the upper page write rises and undergoes transition to any one of the threshold voltage distributions A to G.

Similarly to the semiconductor memory devices of the first through second embodiments, the above-described kind of semiconductor memory device also has a problem with hold characteristics of data when forming, for example, the intermediate voltage distribution LM 1 in b of FIG. 8 or the intermediate voltage distributions LM 2 to LM 4 in c of FIG. 8 . Accordingly, it is preferable that in the case of one or more of the verify voltages VLM 1 , VLM 2 , VLM 3 , and VLM 4 for obtaining the intermediate voltage distributions, a value of the verify voltage is changed according to the number of times of writes and the number of times of erases on the memory cell. As a result, increase in the fail bit number can be suppressed and hold characteristics of data can be improved.

FIGS. 9A and 9B are each a cross-sectional schematic view showing a configuration of the semiconductor memory device ac cording to the first through second embodiments. In FIG. 9A , a semiconductor chip 22 is mounted on a substrate 20 , and a sealing resin 24 is formed in a region above the substrate 20 and covering the semiconductor chip 22 . In FIG. 9A , the column control circuit 2 and the row control circuit 3 which are an example of the control circuit are formed in the identical semiconductor chip 22 to the memory cell array 1 .

In FIG. 9B , semiconductor chips 22 and 23 are mounted on a substrate 20 , and a sealing resin 24 is formed in a region above the substrate 20 and covering the semiconductor chips 22 and 23 . In FIG. 9B , the memory cell array 1 is formed in the semiconductor chip 22 , and the column control circuit 2 and the row control circuit 3 which are an example of the control circuit are formed in the semiconductor chip 23 . That is, the column control circuit 2 and the row control circuit 3 which are an example of the control circuit are provided externally to the semiconductor chip 22 where the memory cell array 1 is formed. The semiconductor chips 22 and 23 are electrically connected by wiring not illustrated.

Other Embodiments

While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.