Class AB amplifiers

This is a continuation of U.S. patent application Ser. No. 13/769,700 (now U.S. Pat. No. 8,736,374), filed on Feb. 18, 2013 which is a continuation of U.S. patent application Ser. No. 13/044,183 (now U.S. Pat. No. 8,378,750), filed on Mar. 9, 2011, which claims the benefit of U.S. Provisional Application No. 61/312,167, filed on Mar. 9, 2010. The entire disclosures of the above applications are incorporated herein by reference.

The present disclosure relates to amplifiers, and more particularly to class AB amplifiers.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Class A amplifiers operate over an entire cycle of an input signal. An output signal is a scaled-up replica of the input signal. Class A amplifiers have a maximum efficiency of about 50% with inductive output coupling and about 25% with capacitive output coupling.

In Class A amplifiers, a transistor is biased such that the transistor is always conducting. The transistor is operated over a linear portion of the transistor's transfer characteristic. Because the transistor is always conducting, power is drawn from the power supply even when there is no input. If high output power is needed, power consumption (and the accompanying heat) may become significant.

Class B amplifiers amplify during half of an input cycle. As a result, Class B amplifiers tend to increase distortion but have higher efficiency than Class A amplifiers. Class B amplifiers have a maximum efficiency over 75%. Transistors are switched off half of the time and do not dissipate power at this time.

Class B amplifiers may use complementary transistor pairs (a “push-pull” transistor arrangement). Complementary devices amplify opposite halves of the input signal. Mismatch or crossover distortion may occur when re-joining the halves of the signal. One solution to the mismatch problem involves biasing the transistors to be just on, rather than completely off when not in use. This biasing approach is called Class AB operation. In other words, Class AB amplifying devices may include a class B output stage that is biased so that both transistors are conducting around a crossover point.

A class AB amplifier includes a first inductor having a first terminal in communication with a voltage source terminal. A first transistor has a drain terminal in communication with a second terminal of the first inductor. A second transistor has a source terminal in communication with a source terminal of the first transistor. A second inductor has a first terminal in communication with a drain terminal of the second transistor and a second terminal in communication with a reference potential. The drain terminals of the first transistor and the second transistor are capacitively coupled together.

In other features, a first capacitance has a first terminal in communication with the source terminals of the first transistor and the second transistor. A second terminal of the first capacitance is in communication with a voltage input to the class AB amplifier.

In other features, a first capacitance has a first terminal in communication with gate terminals of the first transistor and the second transistor. A second terminal of the first capacitance is in communication with a voltage input to the class AB amplifier.

In other features, a first variable capacitance is connected in parallel with the first inductor. A second variable capacitance is connected in parallel with the second inductor. A first capacitance has a first terminal in communication with the drain terminal of the first transistor and a second terminal in communication with the drain terminal of the second transistor.

In other features, N capacitances have first terminals in communication with the drain terminal of the first transistor. N resistances have first terminals in communication with second terminals of respective ones of the N capacitances and have second terminals in communication with the drain terminal of the second transistor, wherein N is an integer greater than zero.

In other features, a third inductor has a first terminal in communication with the voltage source terminal. A third transistor has a drain terminal in communication with a second terminal of the third inductor. A fourth transistor has a source terminal in communication with a source terminal of the third transistor. A fourth inductor has a first terminal in communication with a drain terminal of the fourth transistor and a second terminal in communication with a reference potential. The drain terminals of the third transistor and the fourth transistor are capacitively coupled.

In other features, first and second capacitances are connected in series with each other and connected in parallel to the drain terminals of the first transistor and the second transistor, respectively. Third and fourth capacitances are connected in series with each other and connected in parallel to the drain terminals of the third transistor and the fourth transistor, respectively.

In other features, a fifth capacitance has a first terminal connected between the first and second capacitances and to the source terminals of the first transistor and the second transistor. The fifth capacitance has a second terminal connected between the third and fourth capacitances and to the source terminals of the third transistor and the fourth transistor. A sixth capacitance has one end that communicates with the first terminals of the first and second capacitances. A seventh capacitance has one end that communicates with the first terminals of the third and fourth capacitances.

In other features, an input driver includes a third transistor having a gate terminal in communication with an input signal, a tank circuit in communication with a terminal of the third transistor and a matching network in communication with the terminal of the third transistor and the source terminals of the first transistor and the second transistor.

In other features, a first capacitance has a first terminal in communication with the source terminals of the first transistor and the second transistor. A second capacitance has a first terminal in communication with the source terminals of the third transistor and the fourth transistor. A fifth inductor is in communication with second terminals of the first and second capacitances.

In other features, a fifth transistor has a gate terminal in communication with a first polarity of a differential input signal and a first terminal in communication with the second terminal of the first capacitance. A sixth transistor has a gate terminal in communication with a second polarity of the differential input signal and a first terminal in communication with the second terminal of the second capacitance.

In other features, a power combiner includes fifth, sixth, seventh and eighth inductors coupled to the first, second, third and fourth inductors, respectively. An antenna is connected to the power combiner. The first, second, third and fourth transistors and the first, second, third and fourth inductors are connected in a first loop. The fifth, sixth, seventh and eighth inductors are connected in a second loop that is arranged one of inside or outside of the first loop.

In other features, a first capacitance has a first terminal in communication with the source terminals of the first transistor and the second transistor. A second capacitance has a first terminal in communication with the source terminals of the third transistor and the fourth transistor. A fifth inductor is in communication with second terminals of the first and second capacitances. The first, second, third and fourth transistors and the first, second, third and fourth inductors are connected in a first loop. The fifth, sixth, seventh and eighth inductors are connected in a second loop that is arranged one of inside or outside of the first loop. The fifth inductor has a shape of number “8”. The fifth inductor is located inside of the first loop and the second loop.

In other features, the first and second capacitances and the fifth inductor have a first impedance at a center frequency of the class AB amplifier and have second and third impedances at second and third harmonic frequencies, respectively, of the class AB amplifier. The second and third impedances are greater than the first impedance. The first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

A class AB amplifier includes a first inductor having a first terminal in communication with a voltage source terminal. A first transistor has a drain terminal in communication with a second terminal of the first inductor. A second transistor has a source terminal in communication with a source terminal of the first transistor. A second inductor has a first terminal in communication with a drain terminal of the second transistor and a second terminal in communication with a reference potential. A third inductor has a first terminal in communication with the voltage source terminal. A third transistor has a drain terminal in communication with a second terminal of the third inductor. A fourth transistor has a source terminal in communication with a source terminal of the third transistor. A fourth inductor has a first terminal in communication with a drain terminal of the fourth transistor and a second terminal in communication with a reference potential. The drain terminals of the first transistor and the third transistor are capacitively coupled. The drain terminals of the second transistor and the fourth transistor are capacitively coupled. A first polarity of a differential signal is input to gates of the first and third transistors and a second polarity of the differential signal is input to gates of the second and fourth transistors.

Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.

The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

FIG. 1 is an electrical schematic of a first push-pull class AB amplifier according to the present disclosure;

FIG. 2 is an electrical schematic of second push-pull class AB amplifier according to the present disclosure;

FIG. 3 is an electrical schematic of third push-pull class AB amplifier according to the present disclosure;

FIG. 4 is an electrical schematic of fourth push-pull class AB amplifier according to the present disclosure;

FIG. 5 is an electrical schematic of fifth push-pull class AB amplifier according to the present disclosure;

FIG. 6 is an electrical schematic of sixth push-pull class AB amplifier according to the present disclosure;

FIG. 7 is an electrical schematic of seventh push-pull class AB amplifier according to the present disclosure;

FIG. 8 is an electrical schematic of eighth push-pull class AB amplifier according to the present disclosure;

FIG. 9 is an electrical schematic of ninth push-pull class AB amplifier according to the present disclosure;

FIG. 10 is an example partial layout of a push-pull class AB amplifier with a power combiner according to the present disclosure; and

FIG. 11 is an example partial layout of another push-pull class AB amplifier with a power combiner according to the present disclosure.

The following description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure.

Referring now to FIGS. 1 and 2 , single-ended arrangements of push-pull class AB amplifiers 50 and 100 are shown. In FIG. 1 , the amplifier 50 is arranged in a common gate configuration. The amplifier 50 includes a first inductor L 1 , a first transistor T 1 , a second transistor T 2 and a second inductor L 2 , which are connected in series. The first transistor T 1 may be an NMOS transistor and the second transistor T 2 may be a PMOS transistor, although other types of transistors can be used. Inputs of the transistors T 1 and T 2 may be connected to AC ground or another bias or reference signal.

Variable capacitances C 1 and C 2 may be connected in parallel with the inductors L 1 and L 2 , respectively. The inductor L 1 may be connected to a reference potential V dd . The inductor L 2 may be connected to a ground potential V ss .

A capacitance C cm may be connected to drain terminals of the first and second transistors T 1 and T 2 . An input signal may be applied via an input capacitance C in to source terminals of the first and second transistors T 1 and T 2 . Output signals V o1 and V o2 may be taken across terminals of the capacitance C cm .

In FIG. 2 , the push-pull class AB amplifier 100 is shown. The amplifier 100 is arranged in a common source configuration. The source terminals of the transistors T 1 and T 2 may be connected to AC ground or another bias or reference signal. The amplifier 100 is similar to the amplifier 50 except that the input signal V in is applied to gates of the first and second transistors T 1 and T 2 .

In both FIGS. 1 and 2 , the capacitance C cm removes even harmonics from the output signals V o1 and V o2 due to cancelling of the opposite phase of the even harmonics. The capacitance C cm tends to help transistor mismatch and to reduce distortion. Unlike conventional power amplifiers, the amplifiers 50 and 100 can have a voltage swing that is greater than 2V dd . The source node between the transistors T 1 and T 2 is floating and a low side can go below ground. The value of the capacitance C cm may be selected to be larger than the capacitances C 1 and C 2 . The output signals V o1 and V o2 may be recombined in any suitable manner. In one example, inductive coupling via transformers may be used to recombine the output signals V o1 and V o2 , as will be described below.

Referring now to FIG. 3 , another push-pull class AB amplifier 150 is shown. The capacitance C cm is replaced by one or more series-connected capacitance and resistance pairs, which are connected in parallel across the first and second transistors T 1 and T 2 . In particular, capacitances C 31 , C 32 , . . . , and C 3N are connected in series with resistances R 11 , R 12 , . . . , and R in , respectively, where N is an integer greater than zero. In some implementations, the capacitances C 31 , C 32 , . . . , and C 3N are selected to have the same or different values. In some implementations, the resistances R 11 , R 12 , . . . , and R in are selected to have the same or different values. Using the capacitances and resistances may tend to reduce oscillation.

Referring now to FIG. 4 , another push-pull class AB amplifier 200 is shown. The amplifier 200 is a differential implementation of the amplifier 150 of FIG. 3 . The amplifier 200 further includes a third inductor L 3 , a third transistor T 3 , a fourth transistor T 4 and a fourth inductor L 4 , which are connected in series. The fourth transistor T 4 may be an NMOS transistor and the third transistor T 3 may be a PMOS transistor, although other types of transistors can be used. Inputs of the transistors T 1 and T 2 and T 3 and T 4 may be connected to AC ground or another bias or reference signal.

Variable capacitances C 3 and C 4 may be connected in parallel with the inductors L 3 and L 4 , respectively. The inductor L 4 may be connected to the reference potential V dd . The inductor L 3 may be connected to the ground potential V ss . A differential input signal may be applied via an input capacitance C in to source terminals of the third and fourth transistors T 3 and T 4 . Output signals V o3 and V o4 may be taken across terminals of the third and fourth transistors T 3 and T 4 .

Capacitances C 51 , C 52 , . . . , and C 5N are connected in series with resistances R 11 , R 12 , . . . , and R in , respectively, where N is an integer greater than zero. One or more pairs of the capacitances C 51 , C 52 , . . . and C 5N and the resistances R 11 , R 12 , . . . and R in are connected in parallel across the third and fourth transistors T 1 and T 2 . Capacitances C 61 , C 62 , . . . , and C 6N are connected in series with resistances R 21 , R 22 , . . . , and R 2N , respectively, where N is an integer greater than zero. One or more pairs of the capacitances C 61 , C 62 , . . . and C 6N and the resistances R 21 , R 22 , . . . and R 2N are connected in parallel across the third and fourth transistors T 3 and T 4 .

Referring now to FIG. 5 , another push-pull amplifier 250 is shown. Additional capacitances C 5 to C 11 may be provided. The capacitances C 5 and C 6 replace one of the common mode capacitances C cm and are connected in series with each other and in parallel across the transistors T 1 and T 2 . The capacitances C 7 and C 8 replace the other common mode capacitance C cm and are connected in series with each other and in parallel across the transistors T 3 and T 4 . One end of a capacitance C 10 is connected to first terminals of the capacitances C 5 and C 6 and to the source terminals of the transistors T 1 and T 2 . Another end of the capacitance C 10 is connected to first terminals of the capacitances C 7 and C 8 and to the source terminals of the transistors T 3 and T 4 .

One end of a variable capacitance C 11 is connected to a second terminal of the capacitance C 6 and to the drain terminal of the transistors T 2 . Another end of the variable capacitance C 11 is connected to a second terminal of the capacitance C 8 and to the drain terminal of the transistor T 3 . One end of a variable capacitance C 9 is connected to a second terminal of the capacitance C 5 and to the drain terminal of the transistors T 1 . Another end of the variable capacitance C 9 is connected to a second terminal of the capacitance C 7 and to the drain terminal of the transistor T 4 . For example, an inductive coupling loop may couple with the inductors L 1 , L 2 , L 3 and L 4 to drive an output such as an antenna.

Referring now to FIG. 6 , another push-pull class AB amplifier 270 is shown and includes a power combiner 280 . The amplifier 270 includes a first inductor L 1 , a first transistor T 1 , a second transistor T 2 and a second inductor L 2 , which are connected in series.

The amplifier 270 further includes a third inductor L 3 , a third transistor T 3 , a fourth transistor T 4 and a fourth inductor L 4 , which are connected in series. Capacitances C 1 , C 2 , C 3 and C 4 may be variable capacitances that are arranged in parallel with the inductors L 1 , L 2 , L 3 and L 4 . Common mode capacitances C 5 and C 6 are arranged in parallel with transistors T 1 and T 2 and T 3 and T 4 , respectively.

The power combiner 280 includes first, second, third and fourth inductors S 1 , S 2 , S 3 and S 4 , respectively, which are coupled to the first, second, third and fourth inductors L 1 , L 2 , L 3 and L 4 , respectively, to create first, second, third and fourth transformers. In some examples, the output may be coupled to an antenna (not shown) or another load.

Referring now to FIG. 7 , an example of an input driver 300 for the single ended amplifier 50 is shown. A matching network 304 includes the capacitance C in and an inductor L 3 . A tank circuit 306 includes an inductor L 4 and a capacitance C 3 . An input signal V in is input to a gate of a transistor T 3 . The tank circuit 306 and the matching network 304 couple the input signal to the sources of the transistors T 1 and T 2 .

Referring now to FIG. 8 , an example of an input driver 340 for a differential amplifier 350 is shown. The amplifier 350 includes the components of the amplifier 50 . The amplifier 350 further includes a third inductor L 3 , a third transistor T 3 , a fourth transistor T 4 and a fourth inductor L 4 , which are connected in series. Inputs of the transistors T 1 , T 2 , T 3 , and T 4 may be connected to AC ground or another bias or reference signal. Variable capacitances C 3 and C 4 may be connected in parallel with the inductors L 3 and L 4 , respectively. The inductor L 4 may be connected to the reference potential V dd . The inductor L 3 may be connected to the ground potential V ss .

Capacitance C 5 , inductor L in and capacitance C 6 are connected in series between the sources of the transistors T 1 and T 2 and the sources of transistors T 3 and T 4 . Drains (or sources) of the transistors T 5 and T 6 are connected between the inductor L in and the capacitances C 5 and C 6 , respectively. Sources (or drains) of the transistors T 5 and T 6 are connected to V ss . One polarity of the differential input signal V in+ is coupled to a gate of the transistor T 5 and the other polarity of the differential input signal V in− is coupled to a gate of the transistor T 6 . The inductor L in may have a center tap that may be connected to a bias signal, a reference potential or a ground potential.

The connection provided by the capacitances C 5 and C 6 and the inductor L in provides source degeneration. The connection provides a low impedance connection such as a short circuit at a center frequency and a higher impedance connection at other frequencies. For example, the connection has high impedance at second and third harmonic frequencies.

Referring now to FIG. 9 , another push-pull class AB amplifier 600 is shown and includes a power combiner 630 . The amplifier 600 includes a first inductor L 1 , a first transistor T 1 , a second transistor T 2 and a second inductor L 2 , which are connected in series. The amplifier 600 further includes a third inductor L 3 , a third transistor T 3 , a fourth transistor T 4 and a fourth inductor L 4 , which are connected in series. A first capacitance C 1 , an inductor L in and a second capacitance C 2 are connected in series. The first capacitance C 1 is also connected to source terminals of the first and second transistors T 1 and T 2 . The second capacitance C 2 is also connected to source terminals of the third and fourth transistor T 3 and T 4 . Capacitance C 3 is connected to drains of the transistors T 1 and T 3 . Capacitance C 4 is connected to drains of the transistors T 2 and T 4 . A first polarity of the differential signal V in+ is input to gates of transistors T 1 and T 3 . A second polarity of the differential signal V in− is input to gates of transistors T 2 and T 4 .

The power combiner 630 includes first, second, third and fourth inductors S 1 , S 2 , S 3 and S 4 , respectively, which are coupled to the first, second, third and fourth inductors L 1 , L 2 , L 3 and L 4 , respectively, to create first, second, third and fourth transformers. In some examples, the output may be coupled to an antenna (not shown) or another load.

Referring now to FIG. 10 , an example layout of the amplifier 600 and the power combiner 630 is shown. A first loop 704 includes the first, second, third and fourth inductors S 1 , S 2 , S 3 and S 4 , respectively. A second loop 708 provides connections to the transistor pairs, V dd and V ss . The first and second loops 704 and 708 may have a circular, elliptical, rectangular, square or other generally closed shape. The inductor L in may be arranged inside or outside of the first and second loops 704 and 708 . The inductor L in may have a shape of number “8”. The first loop 704 may be arranged inside or outside of the second loop 708 in a plan view. The current in the first loop 704 may flow through the inductors S 1 , S 2 , S 3 and S 4 in the same direction.

While two legs are shown for example in FIGS. 5 and 6 , additional legs with additional transistor pairs can be used. Referring now to FIG. 11 , an example layout of an amplifier 730 and a power combiner 740 for four pairs of transistors is shown. A first loop 744 includes inductors that couple with inductors in a second loop 748 . For example only, the first and second loops 744 and 748 may have a circular, elliptical, rectangular, square or other generally-closed shape. The inductor L in may be arranged inside or outside of the first and second loops 744 and 748 . The first loop 744 may be arranged inside or outside of the second loop 748 in a plan view.

The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims.