Simplified and effective offset calibration circuit for RxLOS in serdes

This application claims priority under 35 U.S.C. §119(e) to provisional patent application U.S. Ser. No. 61/985,206 filed on Apr. 28, 2014. Said application is hereby incorporated by reference herein in its entirety.

The invention generally relates to the field of high speed serial communications, and particularly to offset calibration for a receiver loss of signal (RxLOS) in a serializer/deserializer (SerDes) receiver device.

The Receiver Loss of Signal (RxLOS) signal is an output of the analog signal detection circuit in a typical serializer/deserializer (SerDes) device core that indicates loss of signal at the SerDes receiver. The RxLOS signal may either switch between logic-one and logic-zero for a short period or remain at either value for an extended period. Active glitches may lead to indicating an erroneous loss of signal condition or erroneous recovery of a lost signal. Input signals affected by inter-symbol interference or channel noise may complicate returning an accurate loss of signal. Correction or calibration of offset error in the RxLOS signal is therefore common.

Offset calibration is generally performed in the peak detector (PKDET) cell of the RxLOS circuit. When the RxLOS circuit is in operating mode, the PKDET cell provides input to a comparator. The PKDET cell compares the received peak voltage with a known reference voltage (ex.—threshold voltage) and the comparator makes a decision (logic-zero or logic-one) with respect to the calibrated signal. The offset of the PKDET cell will affect the decision made by the comparator. It may therefore be desirable to provide improved signal offset calibration while conserving space by utilizing a more compact and cost-efficient circuit.

Accordingly, an embodiment of the disclosure is directed to a method for cancelling offset in a receiver loss of signal (RxLOS) circuit for a serializer/deserializer (SerDes) receiver device. In embodiments, the method comprises: switching the receiver loss of signal circuit from an operating mode to an offset calibration mode; receiving a differential input signal through a first stage; shorting the first differential output signal of the first stage to generate a second differential output signal and a common mode voltage; and switching the receiver loss of signal circuit from a calibration mode to an operating mode.

A further embodiment of the disclosure is directed to a peak detector cell including: a first stage including circuitry configured to receive at least one first differential input signal and to generate at least one first differential output signal, a second stage including at least one control switch configured to short the at least one first differential output signal and to generate at least one of a second differential output signal and a common mode voltage; and a third stage including circuitry configured to receive the at least one second differential output signal and to generate at least one third differential output signal.

A still further embodiment of the disclosure is directed to a serializer-deserializer (SerDes) receiver device including receiver loss of signal (RxLOS) circuitry, the circuitry including: a first stage including circuitry configured to receive at least one first differential input signal and generate at least one first differential output signal, a second stage including at least one control switch configured to short the at least one first differential output signal and generate at least one of a second differential output signal and a common mode voltage; and a third stage including circuitry configured to receive the at least one second differential output signal and generate at least one third differential output signal.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the general description, serve to explain the principles of the invention.

The invention may be better understood by those skilled in the art by reference to the accompanying figures in which:

FIG. 1 is a schematic diagram of a RxLOS circuit;

FIG. 2 is a schematic diagram of a PKDET cell in a RxLOS circuit;

FIG. 3 is a schematic diagram of a source follower of a PKDET cell;

FIG. 4 is a schematic diagram of a reconfigured PKDET cell in a RxLOS circuit according to an embodiment of the invention;

FIG. 5 is a table showing simulation results of various RxLOS offset calibration methods; and

FIG. 6 is a process flow diagram illustrating a method according to an embodiment of the invention.

Features of the invention in its various embodiments are exemplified by the following descriptions with reference to the accompanying drawings, which describe the invention with further detail. These drawings depict only selected embodiments of the invention, and should not be considered to limit its scope in any way.

FIG. 1 illustrates a receiver loss of signal (RxLOS) circuit 100 of a serializer/deserializer (SerDes) receiver device. The RxLOS circuit 100 may be set either to normal operating mode or to offset calibration mode. When the RxLOS circuit 100 is in normal operating mode, peak detector (PKDET) cell 110 can receive a differential input signal RXP/RXN representing the RxLOS signal. The precise signal pattern may vary depending on the specified application and protocol (e.g., SATA, SAS, FC, Ethernet). The PKDET cell 110 can then compare received peak voltage with a known reference voltage and provide preliminary output VPK, VREF to the comparator cell 120 . The comparator 120 can then make a decision (logic one or logic zero) with respect to the RxLOS signal. While the PKDET cell 110 is the first stage of the RxLOS circuit 100 , mismatched components of the PKDET cell 110 can lead to signal offset which must be calibrated (ex.—cancelled out) for an optimal RxLOS signal. Therefore the RxLOS circuit 100 can generally be switched to an offset calibration mode during the power-up phase of the receiver device.

FIG. 2 illustrates a PKDET cell 110 of an RxLOS circuit 100 incorporating conventional offset calibration and the three main stages 130 , 140 , 150 of the PKDET cell 110 . When the RxLOS circuit 100 is set to offset calibration mode, conventional offset calibration is generally performed only at the third stage 150 of the PKDET cell 110 . First stage 130 includes a differential amplifier 132 with RXP/RXN as input and differential output DATP and DATN. By shorting input signal RXP/RXN (i.e., setting RXP=RXN and input voltage to 0V), offset voltage V OS1 can be generated such that

DATP = DATN + V os ⁢ ⁢ 1 DATP = V cm + V os ⁢ ⁢ 1 2 DATN = V cm - V os ⁢ ⁢ 1 2

where V cm is the output common mode voltage of the first stage 130 . When the RxLOS circuit 100 is set to normal operating mode, control switch TGN shorts VR/VP, the differential input to the third stage 150 , to VREFI/VPKI (the output of the second stage 140 ). When the RxLOS circuit 100 is set to offset calibration mode, control switch TG shorts VR/VP to VCMTRIM, where VCMTRIM is the output of source follower (ex.—metal oxide semiconductor field effect transistor, MOSFET) 142 in second stage 140 . Source follower 142 a has an input CM, or the output common mode voltage of first stage 130 . Therefore, conventional offset calibration mode calibrates the offset of the third stage 150 only; the offset of first stage 130 and second stage 140 are irrelevant.

This conventional technique for RxLOS offset calibration can be improved upon by calibrating signal offset at all three stages of the PKDET cell no, but there are at least two problems associated with this approach. First, referring to FIG. 2 , the second stage 140 of the PKDET cell no includes three source followers 142 a , 142 b , 142 c . The inputs to source followers 142 b and 142 c (apart from bias current IBIASP and BIASN) respectively include DATP and DATN, where DATP/DATN represents the differential output of the first stage 130 . If the threshold voltage of each source follower is V th , and the square law model for a MOSFET in saturation mode provides that drain current I DS is equal to

I DS = μ ⁢ ⁢ C ox ⁢ W 2 ⁢ L ⁢ ( V gs - V th ) 2

it can therefore be deduced that

V REFI = V cm - V th - 2 ⁢ ⁢ L ⁢ ⁢ I DS μ ⁢ ⁢ C ox ⁢ W V PKI = DATP - V th - 2 ⁢ ⁢ L ⁢ ⁢ I DS p μ ⁢ ⁢ C ox ⁢ W = DATN - V th - 2 ⁢ ⁢ L ⁢ ⁢ I DS n μ ⁢ ⁢ C ox ⁢ W = V cm - V th - 2 ⁢ ⁢ L ⁢ ⁢ I DS μ ⁢ ⁢ C ox ⁢ W

and that, by comparing the above equations for V REFI and V PKI , the offset of first stage 130 (DATP/DATN) has no effect on second stage 140 (e.g., the value of V PKI depends on V cm regardless of whether DATP/DATN is offset).

If the receiver device is in a power-up stage the RxLOS circuit 100 may be switched to offset calibration mode via CMOS switches, either automatically or manually. Then, if CMOS switches are used to switch the RxLOS circuit 100 to offset calibration mode and thereby short the input RXP/RXN of first stage 130 and calibrate the offset of all three stages 130 , 140 , 150 of the PKDET cell no, when the RxLOS circuit 100 is switched back to normal operating mode the amplitude of differential input RXP/RXN may be large (e.g., 1600 mVppd) due to the specifications of various applications. The input common mode voltage of input signal RXP/RXN, for example, may be set by the receiver device. A sufficiently large input amplitude (e.g., 1600 mVppd) may induce a very high source voltage (e.g., above 1.2 V) of the 1V PMOS core device of the CMOS switches, while the gate of the PMOS device may be connected to a VDDA supply or regulator output (0.9 V). Therefore, the PMOS device may be in a weak inversion mode where the 0.9 V gate voltage is less than the 1.2 V source voltage, and the resulting leakage current will be too large. Reliability issues with the PMOS core device may also result. This problem can be easily solved by using 1.8 V devices as CMOS switches to short the input RXP/RXN of first stage 130 in offset calibration mode, and connecting the gate of the CMOS switches to a VDDH-level higher supply domain (e.g., 1.8 V). However, this solution also requires the use of level shifters (e.g., from an 0.9 V to a 1.8 V power supply domain) and 1.8 V I/O devices in the PKDET cell 110 , which would increase both area and cost.

FIG. 3 depicts the internal circuitry of source followers 142 a , 142 b , 142 c in second stage 140 . Input voltage VIN may consist of a different input for each source follower (common mode voltage CM for source follower 142 a , first stage differential output DATN/DATN for source followers 142 b and 142 c ), as will source follower outputs consisting of a peak voltage VPEAK and a reference voltage VREF.

FIG. 4 illustrates an embodiment of a reconfigured PKDET cell 210 of the RxLOS circuit 100 incorporating simplified offset calibration circuitry according to the invention. In embodiments, the PKDET cell 210 may incorporate a single offset calibration control switch TG in its second stage 240 . In embodiments, control switch TG may include a CMOS switch. In embodiments, control switch TG may transition the RxLOS circuit 100 between normal operating mode (ex.—switch in OFF mode with respect to offset calibration) and offset calibration mode (ex.—switch in ON mode), and short the differential output DATP/DATN of first stage 130 . In embodiments, shorting the output DATP/DATN of the first stage 130 may achieve offset calibration superior to a conventional approach which calibrates only the offset of the third stage 250 , and comparable to short-input offset calibration which calibrates the offset of all three stages, while utilizing a smaller and more cost-effective calibration circuit. In embodiments, offset calibration may take place automatically when RxLOS circuit 100 is switched to offset calibration mode. In some embodiments, control switch TG may automatically switch the RxLOS circuit 100 to offset calibration mode and perform offset calibration during the receiver power-up phase.

FIG. 5 illustrates simulation results for offset calibration in embodiments of RxLOS circuit 100 using a PMC Monte Carlo analysis of 200 runs. The leftmost column A shows results for the conventional third-stage offset calibration depicted in FIG. 2 , while the center column B shows results for short-input offset calibration. The rightmost column C shows results for an embodiments of a RxLOS circuit incorporating simplified offset calibration according to the invention, indicating performance comparable to short-input offset calibration at reduced area and cost.

FIG. 6 illustrates a process flow diagram of a method 300 for cancelling offset in a differential signal via a RxLOS circuit 100 . It is noted herein that the method 300 may be carried out utilizing any of the embodiments described previously. It is further noted, however, that method 300 is not limited to the components or configurations described previously as multiple components and/or configurations may be suitable for executing method 300 .

At step 310 , the method 300 switches the receiver loss of signal circuit from an operating mode to an offset calibration mode. In some embodiments, receiving a differential input signal may include receiving a differential input signal through a differential amplifier. At step 320 , the method 300 receives a differential input signal. At step 330 , the method 300 generates a first differential output signal. At step 340 , the method 300 shorts the first differential output signal to generate at least a second differential output signal and a common mode voltage. At step 350 , the method 300 switches the RxLOS circuit from the offset calibration mode to the operating mode. In some embodiments, the method 300 may be embodied in an RxLOS circuit of a SerDes receiver device.

Those having skill in the art will appreciate that there are various vehicles by which processes and/or systems and/or other technologies described herein can be effected (e.g., hardware, software, and/or firmware), and that the preferred vehicle will vary with the context in which the processes and/or systems and/or other technologies are deployed. For example, if an implementer determines that speed and accuracy are paramount, the implementer may opt for a mainly hardware and/or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a mainly software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware. Hence, there are several possible vehicles by which the processes and/or devices and/or other technologies described herein may be effected, none of which is inherently superior to the other in that any vehicle to be utilized is a choice dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, any of which may vary. Those skilled in the art will recognize that optical aspects of implementations will typically employ optically-oriented hardware, software, and or firmware.

The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “connected”, or “coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “couplable”, to each other to achieve the desired functionality. Specific examples of couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

While particular aspects of the subject matter described herein have been shown and described, it will be apparent to those skilled in the art that, based upon the teachings herein, changes and modifications may be made without departing from the subject matter described herein and its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of the subject matter described herein.