Constant on time controller

This application claims priority to Chinese Application Serial Number 201410043588.9, filed Jan. 30, 2014, which is herein incorporated by reference.

(1) Field of the Invention

The present invention relates to a constant on time controller, and more particularly relates to a constant on time controller for deciding a constant on-time period according to a bootstrap voltage.

(2) Description of the Prior Art

FIG. 1 is a schematic diagram of a conventional buck converting circuit and a constant on time controller. The buck converting circuit comprises a high-side transistor M 1 , a low-side transistor M 2 , an inductance L and a capacitance C. The high-side transistor M 1 is coupled between an input voltage Vin and a switching node, and the low-side transistor M 2 is coupled between the switching node and a ground potential. The inductance L and the capacitance C are connected in series between the switching node and the ground potential for filtering a voltage of the switching node into an output voltage Vout. The constant on time controller controls the switchings of the high-side transistor M 1 and the low-side transistor M 2 of the buck converting circuit, and a duty cycle of the high-side transistor M 1 decides a ratio of the output voltage Vout to the input voltage Vin.

The constant on time controller comprises comparators 8 and 10 , a SR flip-flop 9 , a capacitance 11 , a transistor 12 , a resistance 13 and a driving circuit 19 . One terminal of the resistance 13 is connected to the input voltage Vin, and another terminal thereof is connected to the capacitance 11 . A non-inverting terminal of the comparator 8 and an inverting terminal of the comparator 10 receive a reference voltage Vref. An inverting terminal of the comparator 8 receives the output voltage Vout, and triggers a set terminal S of the SR flip-flop 9 when the output voltage Vout is lower than the reference voltage Vref for enabling the SR flip-flop 9 to generate a high level signal at an output terminal Q. At this moment, the driving circuit 19 turns on the high-side transistor M 1 and cuts off the low-side transistor M 2 . At the same time, the SR flip-flop 9 generates a low level signal at an inverting output terminal Q to cut off the transistor 12 . The capacitance 11 starts to be charged at this time. When a voltage of the capacitance 11 is raised to the reference voltage Vref, the comparator 10 outputs the high level signal to a reset terminal R of the SR flip-flop 9 for enabling the SR flip-flop 9 to output a low level signal at the output terminal Q and a high level signal at the inverting output terminal V. At this moment, the driving circuit 19 cuts off the high-side transistor M 1 and turns on the low-side transistor M 2 . Besides, the transistor 12 is simultaneously turned on to discharge the capacitance 11 to zero through the transistor 12 , so as to be ready for the output voltage Vout to be lower than the reference voltage Vref again. Thus, when the buck converting circuit is in a stable state, the output voltage Vout is substantially equal to the reference voltage Vref.

The aforementioned circuit uses the resistance 13 to generate a current proportional to the input voltage Vin for charging, the capacitance 11 to reach the output voltage Vout. Therefore, in each cycle, the charging time period of the capacitance 11 is proportional to the ratio of the output voltage Vout to the input voltage Vin, i.e., the constant on time period is proportional to the ratio of the output voltage Vout to the input voltage Vin.

However, the constant on time controller has to additionally add a pin connected to the input voltage Vin for obtaining the information of the input voltage Vin, thus increasing the packaging cost of the constant on time controller.

In view of the conventional constant on time controller in which a pin has to be additionally added for obtaining the information of the input voltage, the constant on time controller of the present invention detects a bootstrap voltage or a high-side control signal for obtaining the information of the input voltage to save the package pin and the packaging cost.

To accomplish the aforementioned and other objects, the present invention provides a constant on time controller packaged in one single package for controlling a buck converting circuit to convert an input voltage into an output voltage. The constant on time controller comprises an input voltage detecting circuit, an on-time determining circuit and a driving, circuit. The input voltage detecting circuit receives a bootstrap voltage for generating an input voltage detecting signal indicative of the input voltage. The on-time determining circuit receives the input voltage detecting signal and generates an on-time signal according to the output voltage and the input voltage detecting a signal. The driving circuit controls the buck converting circuit according to the on-time signal.

The present invention also provides a constant on time controller packaged in one single package for controlling a buck converting circuit to convert an input voltage into an output voltage. The constant on time controller comprises an input voltage detecting circuit, an on-time determining circuit and a driving circuit. The input voltage detecting circuit receives a high-side control signal for generating an input voltage detecting signal indicative of the input voltage. The on-time determining circuit receives the input voltage detecting signal and generates an on-time signal according to the output voltage and the input voltage detecting signal. The driving circuit generates the high-side control signal according to the on-time signal and a bootstrap voltage for controlling the buck converting circuit.

It is to be understood that both the foregoing general description and the following, detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. In order to make the features and the advantages of the invention comprehensible, exemplary embodiments accompanied with figures are described in detail below.

The present invention will now be specified with reference to its preferred embodiment illustrated in the drawings, in which:

FIG. 1 is a schematic diagram of a conventional buck converting circuit and a constant on time controller;

FIG. 2A is a schematic diagram of a buck converting circuit and a constant on time controller according to a first preferred embodiment of the present invention;

FIG. 2B is a schematic diagram of a buck converting circuit and a constant on time controller according to a second preferred embodiment of the present invention;

FIG. 3 is a schematic diagram of a constant on time circuit according to the first preferred embodiment of the present invention; and

FIG. 4 is a schematic diagram of a constant on time circuit according to the second preferred embodiment of the present invention.

In the following, detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawings.

FIG. 2A is a schematic diagram of a buck converting circuit and a constant on time controller according to a first preferred embodiment of the present invention. The buck converting circuit comprises a high-side transistor M 1 , a low-side transistor M 2 , an inductance L and a capacitance C. The high-side transistor M 1 is coupled between an input voltage Vin and a switching node, and the low-side transistor M 2 is coupled between the switching node and a ground potential. The inductance L and the capacitance C are connected in series between the switching node and the ground potential, for filtering a voltage of the switching node into an output voltage Vout. The constant on time controller controls the switchings of the high-side transistor M 1 and the low-side transistor M 2 of the buck converting circuit, and the duty cycle of the high-side transistor M 1 decides the proportion of the output voltage Vout to the input voltage Vin.

The constant on time controller is packaged in one single package for controlling a buck converting circuit to convert an input voltage into an output voltage. The constant on time controller comprises a constant on time circuit 100 , a comparator 108 , a SR flip-flop 109 and a driving circuit 119 . A non-inverting terminal of the comparator 108 receives a reference voltage Vr, and an inverting terminal thereof receives the output voltage Vout or an output voltage detecting signal indicative of the output voltage Vout. For example, a voltage divider is connected to the output voltage Vout to generate the output voltage detecting signal. An output terminal of the comparator 108 is coupled to a set terminal S of the SR flip-flop 109 . The comparator 108 outputs a high level signal when the output voltage Vout is lower than a preset output voltage value thereby enabling the SR flip-flop 109 to generate a high level signal at an output terminal Q and generate an inverted signal Sq′ with a low level at an inverting output terminal Q′. At this moment, the driving circuit 119 outputs a high-side control signal Sug with a high level to turn on the high-side transistor M 1 , and outputs as low-side control signal Slg with a low level to cut off the low-side transistor M 2 . In actual applications, the SR flip-flop 109 may be integrated into the driving circuit 119 , or may be omitted according to the modification of the driving circuit 119 .

In the present invention, the high-side transistor M 1 and the low-side transistor M 2 are N-type MOSFETs. Hence, for ensuring the high-side transistor M 1 to be turned on the high level of the high-side control signal Sug has to be more than a threshold voltage higher than the input voltage Vin. The present invention uses a bootstrap circuit BS, coupled to the switching node of a buck converting circuit (i.e., the connected node between the high-side transistor M 1 and the low-side transistor M 2 ) and a driving voltage VDD, for providing a bootstrap voltage Vbs which is higher than the input voltage Vin. In which, the driving voltage VDD connected to the constant on time controller is generated by a driving voltage source, so as to provided required operating power to the constant on time controller. In actual application, the driving voltage VDD may be the input voltage Vin, or another voltage source. In one embodiment, the bootstrap circuit BS comprises a diode and a bootstrap capacitance connected in series. A positive terminal of the diode is connected to the driving voltage VDD, and a negative terminal thereof is connected to one terminal of the bootstrap capacitance. Another terminal of the bootstrap capacitance is connected to the switching node. When the low-side transistor M 2 is turned on, the driving voltage VDD charges the bootstrap capacitance via the diode. When the high-side transistor M 1 is turned on, the potential of the switching node is pulled up to the input voltage Vin for enabling the bootstrap capacitance to provide a voltage equal to the sum of the input voltage Vin and the driving, voltage VDD to the driving circuit 119 of the constant on time controller. In other words, the bootstrap circuit BS periodically provides the bootstrap voltage Vbs which is higher than the input voltage Vin in response to the switchings of the high-side transistor M 1 and the low-side transistor M 2 . The bootstrap circuit BS may be completely composed of external discrete devices, or parts (such as diodes) or all of the devices are integrated in the constant on time controller.

The constant on time circuit 100 is coupled to the bootstrap circuit BS for receiving the bootstrap voltage Vbs, and obtains the information of the input voltage Vin by filtering out the driving voltage VDD. The constant on time circuit 100 simultaneously receives a signal indicative of the output voltage Vout, such as the output voltage Vout, an output voltage detection signal, or a signal filtered from the connected node of the high-side transistor M 1 and the low-side transistor M 2 , for determining a constant on time period according to the information of the input voltage Vin and the output voltage Vout. The following embodiments will be illustrated in detail to explain the operation and the principle of the constant on time circuit.

The constant on time circuit 100 is coupled to a reset terminal R of the RS flip-flop 109 , and outputs an on-time signal Son to the reset terminal R in the constant on time period after the high-side transistor M 1 is started to be turned on. At this moment, the SR flip-flop 109 outputs a low level signal at the output terminal Q, and outputs an inverted signal Sq′ with high level at the inverting output terminal Q′, for enabling the driving circuit 119 to cut oil the high-side transistor M 1 and turn on the low-side transistor M 2 .

FIG. 2B is a schematic diagram of a buck converting circuit and a constant on time controller according to a second preferred embodiment of the present invention. Compared with the embodiment shown in FIG. 2A , tire constant on time circuit 100 of the present embodiment receives the high-side control signal Sug to replace the bootstrap voltage Vbs and a signal Vph indicative of the output voltage Vout. The signal Vph is generated by a filter 102 which is coupled to the connected node of the high-side transistor M 1 and the low-side transistor M 2 . Because the high logic level of the high-side control signal Sug generated by the driving circuit 119 is the same as the bootstrap voltage Vbs, the constant on time circuit 100 of the present invention can be modified to receive the high-side control signal Sug and obtain the information of the input voltage Vin. The description of other circuits can be referred to the corresponding description in FIG. 2A .

FIG. 3 is a schematic diagram of the constant on time circuit according to the first preferred embodiment of the present invention. The constant on time circuit comprises an input voltage detecting circuit and an on-tune determining circuit. The input voltage detecting circuit comprises an adder 202 . The adder 202 generates an input voltage detecting signal Svin with the information of an input voltage Vin by subtracting the driving voltage VDD from the bootstrap voltage Vbs or the high-side control signal Sug. The on-time determining circuit comprises a voltage-to-current converter 204 , a capacitance Con and a comparing circuit 206 . The voltage-to-current converter 204 generates a charging current Ich to charge the capacitance Con according to the input voltage detecting signal Svin. The comparing circuit 206 generates an on-time signal Son according to a voltage of the capacitance Con and the output voltage Vout, for example, when the voltage of the capacitance Con rises to reach the output voltage Vout. The voltage-to-current converter 204 simultaneously receives the inverted signal Sq′ generated by the SR flip-flop 109 , and discharges the capacitance Con to zero when the inverted signal Sq′ is at the high level. When the inverted signal Sq′ is at the low level, the voltage-to-current converter 204 charges the capacitance Con. At this moment, the on-time determining circuit starts counting time until the voltage of the capacitance Con reaches the output voltage Vout, and then generates the on-time signal Son. Of course, except the inverted signal Sq′, the signal outputted by the SR flip-flop 109 at the output terminal Q, the high-side control signal Sug or the low-side control signal Slg can be used to replace the inverted signal Sq′ to control the voltage-to-current converter 204 to charge and discharge the capacitance Con.

FIG. 4 is a schematic diagram of the constant on time circuit according to the second preferred embodiment of the present invention. The constant on time circuit comprises an input voltage detecting circuit and an on-time determining circuit. The input voltage detecting circuit comprises a first resistance R 1 , a second resistance R 2 and transistors Q 1 and Q 2 . The on-time determining circuit comprises a transistor Q 3 , a current mirror circuit 308 , a capacitance Con and a comparing circuit CMP. The transistors Q 1 and Q 2 may be any transistors. For example, the transistor Q 1 is a NMOS and the transistor Q 2 is a PMOS, and both of them are airs. The present embodiment uses BJTs as an example for the below explanation.

The transistor Q 1 is a BJT having a first collector, a first base and a first emitter. The first collector and the first base are coupled to a driving voltage VDD, and the first emitter is coupled to a ground potential through a first resistance R 1 . Thus, a potential v 1 of a connected node between the first emitter of the transistor Q 1 and the first resistance R 1 is (VDD-Vbe 1 ), wherein Vbe 1 is a forward bias voltage of the transistor Q 1 . The transistor Q 2 is a BIT having a second collector, a second base and a second emitter. The second emitter is coupled to a bootstrap voltage Vbs or a high-side control signal Sug through the second resistance R 2 , and the second base is coupled to the connected node between the first emitter of the transistor Q 1 and the first resistance R 1 . Thus, a potential v 2 of to connected node between the second emitter and the second resistance R 2 is (v 1 +Vbe 2 )=(VDD−Vbe 1 +Vbe 2 ), wherein Vbe 2 is a forward bias voltage of the transistor Q 2 . When Vbe 1 =Vbe 1 , v 2 =VDD. An input voltage detecting signal Svin outputted by the second collector of the transistor Q 2 is the same as the current flowing, through the second resistance R 2 , and thus the current is (Vbs−VDD)/R 2 , representing, to voltage difference obtained by subtracting the driving voltage VDD from the bootstrap voltage Nibs or the high-side control signal Sug. When the low-side transistor M 2 is cut off and the high-side transistor M 1 is turned on, the voltage level of the bootstrap voltage Vbs or the high-side control signal Sug is Vbs=Vin+VDD. Therefore, the input voltage detecting signal Svin is (Vin+VDD−VDD)/R 2 =Vin/R 2 , i.e., Svin is proportional to the input voltage Vin.

The function of the current mirror circuit 308 is a voltage-to-current converter, mirroring the input voltage detecting signal Svin outputted by the second collector of the transistor Q 2 to generate a charging current Ich proportional to the input voltage Vin. The transistor Q 3 and the capacitance Con are connected in parallel. The transistor Q 3 is a N-type MOSFET, in which a gate electrode thereof receives the inverted signal Sq′ generated by the SR flip-flop 109 , and a drain electrode thereof is coupled to the current minor circuit 308 , and a source electrode thereof is coupled to a ground potential. When the inverted signal Sq′ is at the high level, i.e., the low-side transistor M 2 is turned on and the high-side transistor M 1 is cut off, the transistor Q 3 is turned on to enable the charging current Ich to flow into the ground, and to discharge a voltage of the capacitance Con to zero. When the inverted signal Sq′ is at the low level, i.e., the low-side transistor M 2 is cut off and the high-side transistor M 1 is turned on, the transistor Q 3 is cut off. At this moment, the charging current Ich charges the capacitance Con.

A non-inverting terminal of the comparing circuit CMP is coupled to the capacitance Con, and an inverting terminal thereof receives an output voltage Vout (or an output voltage detecting signal indicative of the output voltage, such as a signal filtered from the switching node between the high-side transistor 12 and the low-side transistor M 2 ). When the capacitance Con is charged by the charging current Ich to reach the output voltage Vout, the comparing circuit CMP outputs an on-time signal Son with the high level to enable the high-side transistor M 1 to be turned on through the driving circuit 119 . At the same time, the inverted signal Sq′ is changed to the high level to turn on the transistor Q 3 , and resets the voltage of the capacitance Con to zero for the next cycle. Therefore, the period time of charging the voltage of the capacitance Con from zero to the output voltage Vout is proportional to the output voltage Vout, and is inversely proportional to the charging current Ich, i.e., inversely proportional to the input voltage Vin.

Furthermore, in the embodiment shown in FIG. 4 , an one-shot circuit coupled can be added to an output terminal of the comparing circuit CMP to generate and provide the on-time signal Son with a specified pulse width to the SR flip-flop 109 .

While the preferred embodiments of the present invention have been set forth for the purpose of disclosure, modifications of the disclosed embodiments of the present invention as well as other embodiments thereof may occur to those skilled in the art. Accordingly, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the present invention.