Comparator

This application claims the benefit of priority to Japanese Application No. 2013-099499 filed on May 9, 2013, the entire contents of which are herein incorporated by reference.

A certain aspect of the embodiments discussed herein relates to a comparator.

Conventionally, there is a signal detection device for detecting an input signal that includes noise. This signal detection device has N comparison units for comparing respective N parallel input signals (wherein N is a natural number equal to or greater than 2) with threshold values, respectively, and a computing unit for computing the number N+ of comparison units with the respective input signals greater than the threshold values. This signal detection device further has analysis means for computing a ratio N+/N of the number N+ of comparison units with the respective input signals greater than the threshold values to the number N of elements of the comparison units, based on an output from the computing unit, and estimating waveforms of the input signals by using this ratio of N+/N and statistics of noise (see, for example, Japanese Patent Application Publication No. 2010-045622).

Because a conventional signal detection device as described above uses N comparison units for comparing input signals with N threshold values, respectively, for example, 3 comparison units are needed to compare input signals with 3 threshold values.

Thus, there is a problem of a high electric power consumption of a conventional signal detection device because N comparison units are used to compare input signals with N threshold values, respectively.

According to an aspect of the embodiments, a comparator includes a first comparison unit configured to compare an input signal with a first signal and a second comparison unit configured to compare the input signal with a second signal having a voltage value lower than a voltage value of the first signal in a case where a voltage value of the input signal is lower than the voltage value of the first signal and compare the input signal with a third signal having a voltage value higher than a voltage value of the first signal in a case where a voltage value of the input signal is higher than the voltage value of the first signal.

The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.

FIG. 1 is a diagram illustrating a circuit configuration of a comparator 100 in a first embodiment;

FIG. 2 is a timing chart illustrating an operation of the comparator 100 in the first embodiment;

FIG. 3 as a timing chart illustrating an operation of the comparator 100 in the first embodiment;

FIG. 4 is a timing chart illustrating an operation of the comparator 100 in the first embodiment;

FIG. 5 is a timing chart illustrating an operation of the comparator 100 in the first embodiment;

FIG. 6 is a diagram illustrating a configuration of a comparator circuit 1000 including the comparator 100 in the first embodiment;

FIG. 7 is a diagram illustrating output levels obtained by the comparator 100 , NAND-type latch circuits 30 and 40 , and an encoding part 50 in an embodiment;

FIG. 8 is a diagram illustrating a comparator circuit 90 for comparison;

FIG. 9 is a diagram illustrating a circuit configuration of a comparator 71 ;

FIG. 10 is a diagram illustrating the comparator 71 by symbols;

FIG. 11 is a diagram illustrating outputs of the comparator circuit 90 for comparison;

FIG. 12 is a diagram illustrating a circuit configuration of a comparator 100 A in an variation example of the first embodiment;

FIG. 13 it a diagram illustrating nonterminal node logics XD 0 , XD 1 , XD 2 , and XD 3 of the comparator 100 A in the variation example of the first embodiment;

FIG. 14 is a diagram illustrating a comparator circuit 2000 in a second embodiment;

FIG. 15 is a diagram illustrating a comparator circuit 90 A for comparison;

FIG. 16 is a diagram illustrating a comparator 300 in a third embodiment; and

FIG. 17 is a timing chart illustrating an operation of the comparator 300 in the third embodiment.

Embodiments will be described below, wherein a comparator in the present invention is applied thereto.

First Embodiment

FIG. 1 is a diagram illustrating a circuit configuration of a comparator 100 in a first embodiment.

In the following, a P-channel-type transistor is denoted by a symbol including MP and an N-channel-type transistor is denoted by a symbol including MN. Here, GND denotes ground.

The comparator 100 in the first embodiment includes an input terminal Vin, reference terminals VR 1 , VR 2 , and VR 3 , output terminals XD 0 , XD 1 , XD 2 , and XD 3 , a clock input terminal CK, and an electric power terminal AVD.

The comparator 100 further includes reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 , and a switch MN 0 .

The comparator 100 further includes a pair of inverters 11 and 12 that are connected to provide positive feedback thereto, a differential pair circuit 13 , and inverters INV 1 and INV 2 . The inverter 11 has transistors MPI 1 and MNI 1 and the inverter 12 has transistors MPI 2 and MNI 2 . Furthermore, the differential pair circuit 13 includes transistors MNC 2 and MNR 2 .

Herein, the inverters 11 and 12 , the differential pair circuit 13 , the inverters INV 1 and INV 2 , the switch MN 0 , and the reset switches MPR 1 and MPR 2 constitutes a comparator part 10 . The comparator part 10 is one example of a first comparison unit.

The comparator 100 further includes a pair of inverters 21 and 22 that are connected to provide positive feedback thereto, switches MN 01 , MN 11 , MN 03 , MN 13 , and differential pair circuits 23 and 24 .

The inverter 21 has transistors MPI 0 and MNI 0 . The inverter 22 has transistors MPI 3 and MNI 3 . The differential pair circuit 21 has transistors MNR 1 and MNC 1 . The differential pair circuit 24 has transistors MNR 3 and MNC 3 .

Herein, the inverters 21 and 22 , the switches MN 01 , MN 11 , MN 03 , and MN 13 , the differential pair circuits 23 and 24 , and the reset switches MPR 0 and MPR 3 constitute a comparator part 20 . The comparator part 20 is one example of a second comparison unit.

The input terminal Vin is connected to a gate of the transistor MNC 2 of the differential pair circuit 13 , a gate of the transistor MNC 1 of the differential pair circuit 23 , and a gate of the transistor MNC 3 of the differential pair circuit 24 . The input terminal Vin is an input terminal of the comparator 100 .

The reference terminals VR 1 , VR 2 , and VR 3 are connected to a gate of the transistor MNR 1 of the differential pair circuit 23 , a gate of the transistor MNR 2 of the differential pair circuit 13 , and a gate of the transistor VR 3 of the differential pair circuit 24 , respectively.

Reference voltages VR 1 , VR 2 , and VR 3 are inputted to the reference terminals VR 1 , VR 2 , and VR 3 , respectively. There is a relationship of VR 1 <VR 2 <VR 3 among the reference voltages VR 1 , VR 2 , and VR 3 .

The reference voltages VR 1 , VR 2 , and VR 3 are three reference voltages for the comparator 100 and voltages that are references for comparison with the input voltage Vin. The reference voltage VR 2 is one example of a first signal, the reference voltage VR 1 is one example of a second signal, and the reference voltage VR 3 is one example of a third signal.

The output terminal XD 0 is connected to an output terminal of the inverter 21 . That is, the output terminal XD 0 is connected to a drain of the transistor MPI 0 of the inverter 21 and a drain of the transistor MNI 0 thereof.

Furthermore, the output terminal XD 0 is connected to an input terminal of the inverter 22 . That is, the output terminal XD 0 is connected to a gate of the transistor MPI 3 of the inverter 22 and a gate of the transistor MNI 3 thereof.

Furthermore, the output terminal XD 0 is connected to a drain of the reset switch MPR 0 .

The output terminal XD 1 is connected to an output terminal of the inverter 11 . That is, the output terminal XD 1 is connected to a drain of the transistor MPI 1 of the inverter 11 and a drain of the transistor MNI 1 thereof.

Furthermore, the output terminal XD 1 is connected to an input terminal of the inverter 12 . That is, the output terminal XD 1 is connected to a gate of the transistor MPI 2 of the inverter 12 and a gate of the transistor MNI 2 thereof.

Furthermore, the output terminal XD 1 is connected to a drain of the reset switch MPR 1 and an input terminal of the inverter INV 2 .

The output terminal XD 0 is connected to an output terminal of the inverter 12 . That is, the output terminal XD 2 is connected to a drain of the transistor MPI 2 of the inverter 11 and a drain of the transistor MNI 2 thereof.

Furthermore, the output terminal XD 2 is connected to an input terminal of the inverter 11 . That is, the output terminal XD 2 is connected to a gate of the transistor MPI 1 of the inverter 11 and a gate of the transistor MNI 1 thereof.

Furthermore, the output terminal XD 2 is connected to a drain of the reset switch MPR 2 and an input terminal of the inverter INV 1 .

The output terminal XD 3 is connected to an output terminal of the inverter 22 . That is, the output terminal XD 3 is connected to a drain of the transistor MPI 3 of the inverter 22 and a drain of the transistor MNI 3 thereof.

Furthermore, the output terminal XD 3 is connected to an input terminal of the inverter 21 . That is, the output terminal XD 3 is connected to a gate of the transistor MPI 0 of the inverter 21 and a gate of the transistor MNI 0 thereof.

Furthermore, the output terminal XD 3 is connected to a drain of the reset switch MPR 3 .

Herein, the output terminals XD 1 and XD 2 of the comparator part 10 are one example of a pair of first terminals and the output terminals XD 0 and XD 3 of the comparator part 20 are one example of a pair of second terminals.

The clock input terminal CK is connected to a gate of each of the switch MN 0 and the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 . A reference clock for operating the comparator 100 is inputted to the clock input terminal CK.

The electric power terminal AVD is an electric power input terminal where an analog electric power is inputted from an electric power source. The electric power terminal AVD is connected to a source of each of the transistors MPI 0 , MPI 1 , MPI 2 , and MPI 3 , and the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 .

A source of each of the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 is connected to the electric power terminal AVD. A gate of each of the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 is connected to the clock input terminal CK.

A drain of the reset switch MPR 0 is connected to an output terminal of the inverter 21 , an input terminal of the inverter 22 , and the output terminal XD 0 .

A drain of the reset switch MPR 1 is connected to the output terminal XD 1 , an output terminal of the inverter 11 , an input terminal of the inverter 12 , and an input terminal of the inverter INV 2 .

A drain of the reset switch MPR 2 is connected to the output terminal XD 2 , an output terminal of the inverter 12 , an input terminal of the inverter 11 , and an input terminal of the inverter INV 1 .

A drain of the reset switch MPR 2 is connected to an output terminal of the inverter 22 , an input terminal of the inverter 21 , and the output terminal XD 3 .

The switch MN 0 is such that a gate is connected to the clock input terminal CK, a drain is connected to a common terminal (sources of the transistor MNC 2 and MNR 2 ) of the differential pair circuit 13 and a source is connected to be grounded. The switch MN 0 is one example of a third switch.

The inverters 11 and 12 are connected to provide positive feedback thereto, by connecting mutual input terminals and output terminals. The inverters 11 and 12 are one example of a pair of first inverters connected to provide positive feedback thereto.

The inverter 11 has the transistors MPI 1 and MNI 1 and the inverter 12 has the transistors MPI 2 and MNI 2 .

A source of the transistor MPI 1 of the inverter 11 is connected to the electric power terminal AVD and a source of the transistor MNI 1 is connected to a drain of the transistor MNC 2 of the differential pair circuit 13 .

A source of the transistor MPI 2 of the inverter 12 is connected to the electric power terminal AVD and a source of the transistor MNI 2 is connected to a drain of the transistor MNR 2 of the differential pair circuit 13 .

The differential pair circuit 13 includes the transistors MNC 2 and MNR 2 . A gate of the transistor MNC 2 is connected to the input terminal Vin and a source thereof is connected to a source of the transistor MNR 2 and connected to a drain of the switch MN 0 . A gate of the transistor MNR 2 is connected to the reference terminal VR 2 and a source thereof is connected to a source of the transistor MNC 2 and connected to a drain of the switch MN 0 . The differential pair circuit 13 is one example of a first differential pair circuit.

The inverter INV 1 is such that an input terminal is connected to a drain of the reset switch MPR 2 and an output terminal of the inverter 12 and an output terminal is connected to gates of the switches MN 01 and MN 11 .

The inverter INV 2 is such that an input terminal is connected to a drain of the reset switch MPR 1 and an output terminal of the inverter 11 and an output terminal is connected to gates of the switches MN 03 and MN 13 .

The inverters 21 and 22 are connected to provide positive feedback thereto, by connecting mutual input terminals and output terminals. The inverters 21 and 22 are one example of a pair of second inverters connected to provide feedback thereto.

The inverter 21 has the transistors MPI 0 and MNI 0 and the inverter 22 has the transistors MPI 3 and MNI 3 .

A source of the transistor MPI 0 of the inverter 21 is connected to the electric power terminal AVD and a source of the transistor MNI 0 is connected to drains of the switches MN 11 and MN 03 . Herein, a connection point between a source of the transistor MNI 0 and drains of the switches MN 11 and MN 03 is referred to as a node BD 0 .

A source of the transistor MPI 3 of the inverter 22 is connected to the electric power terminal AVD and a source of the transistor MN 13 is connected to drains of the switches MN 13 and MN 01 . Herein, a connection point between a source of the transistor MNI 3 and drains of the switches MN 13 and MN 01 is referred to as a node BD 3 .

The switch MN 01 is such that a drain is connected to the node BD 3 , a gate is connected to an output of the inverter INV 1 , and a source is connected to a drain of the transistor MNC 1 of the differential pair circuit 23 .

The switch MN 01 is such that a drain is connected to the node BD 3 , a gate is connected to an output of the inverter INV 1 , and a source is connected to a drain of the transistor MNC 1 of the differential pair circuit 23 . Here, a connection point between both gates of the switches MN 01 and MN 11 is referred to as a node BTD 1 . Furthermore, the switches MN 01 and MN 11 are one example of a pair of first switches.

The switch MN 03 is such that a drain is connected to the node BD 0 , a gate is connected to an output of the inverter INV 2 , and a source is connected to a drain of the transistor MNC 3 of the differential pair circuit 24 .

The switch MN 13 is such that a drain is connected to the node BD 3 , a gate is connected to an output of the inverter INV 2 , and a source is connected to a drain of the transistor MNR 3 of the differential pair circuit 23 . Here, a connection point between both gates of the switches MN 03 and MN 13 is referred to as a node BTD 2 . Furthermore, the MN 03 and MN 13 are one example of a pair of second switches.

The differential pair circuit 23 has the transistors MNR 1 and MNC 1 . The transistor MNR 1 is such that a drain is connected to a source of the switch MN 11 , a gate is connected to the reference terminal VR 1 , and a source is grounded. The differential pair circuit 23 is one example of a second differential pair circuit.

The transistor MNC 1 is such that a drain is connected to a source of the switch MN 01 , a gate is connected to the input terminal Vin, and a source is grounded.

The differential pair circuit 24 has the transistors MNR 3 and MNC 3 . The transistor MNR 3 is such that a drain is connected to a source of the switch MN 13 , a gate is connected to the reference terminal VR 3 , and a source is grounded. The differential pair circuit 24 is one example of a third differential pair circuit.

The transistor is such that a drain is connected to a source of the switch MN 03 , a gate is connected to the input terminal Vin, and a source is grounded.

Although the description is herein provided in such a manner that the inverters INV 1 and INV 2 are included in components of the comparator part 10 , the inverters INV 1 and INV 2 may not be included in the comparator part 10 .

In this case, the inverters INV 1 and INV 2 are included in components of the comparator 20 , or may not be included in components of the comparator parts 10 or 20 .

Furthermore, the differential pair circuit 23 and the switches MN 01 and MN 11 are one example of a first comparison circuit that is included in the comparator part 20 as one example of a second comparison unit. Furthermore, the differential pair circuit 24 and the switches MN 03 and MN 13 are one example of a second comparison circuit that is included in the comparator part 20 as one example of a second comparison unit.

Next, an operation of the comparator 100 in the first embodiment will be described. Herein, the reference voltage VR 2 is one example of a first voltage, the reference voltage VR 1 is one example of a second voltage, and the reference voltage VR 3 is one example of a third voltage. There is a relationship of VR 1 <VR 2 <VR 3 among the reference voltages VR 1 , VR 2 , and VR 3 .

First, the comparator 100 compares the input voltage Vin with the reference voltage VR 2 at a first step. This comparison at the first step is executed in the comparator part 10 .

Then, the comparator 100 executes comparison at a second step, depending on a result of comparison at the first step. At the second step, the comparator 100 compares the input voltage Vin with the reference voltage VR 1 lower than the reference voltage VR 2 in a case where the input voltage Vin is lower than the reference voltage VR 2 , and compares the input voltage Vin with the reference voltage VR 3 higher than the reference voltage VR 2 in a case where the input voltage Vin is higher than the reference voltage VR 2 .

That is, in a case where the input voltage Vin is lower than the reference voltage VR 2 , the comparator 100 at the second step does not compare the input voltage Vin with the reference voltage VR 3 higher than the reference voltage VR 2 but compares the input voltage Vin with the reference voltage VR 1 lower than the reference voltage VR 2 .

Furthermore, in a case where the input voltage Vin is higher than the reference voltage VR 2 , the comparator 100 at the second step does not compare the input voltage Vin with the reference voltage VR 1 lower than the reference voltage VR 2 but compares the input voltage Vin with the reference voltage VR 3 higher than the reference voltage VR 2 .

This comparison at the second step is executed in the comparator part 20 .

An operation of comparison of the comparator 100 will be described by using FIG. 2 to FIG. 5 in more detail below.

FIG. 2 to FIG. 5 are timing charts illustrating operations of the comparator 100 in the first embodiment. FIG. 2 to FIG. 5 illustrate voltage levels (H (High) or L (Low)) of the clock input terminal CK, the output terminals XD 1 and XD 2 , the nodes BTD 1 and BTD 2 , and the output terminals XD 3 and XD 0 .

Furthermore, in the following, a clock to be inputted to the clock input terminal CK is referred to as a clock CK, voltages of the output terminals XD 1 , XD 2 , XD 3 , and XD 4 , are referred to as output voltages XD 1 , XD 2 , XD 3 , and XD 4 , and a voltage to be inputted to the electric power terminal AVD is referred to as an electric power source voltage AVD.

First, an operation of the comparator 100 in a case where Vin<VR 1 <VR 2 <VR 3 is held among the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 will be described by using FIG. 1 and FIG. 2 .

First, the clock CK is at an L level, and thereby, the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned on and the switch MN 0 is turned off.

As the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned on, the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are pulled up by the electric power source voltage AVD to be at an H levels (see time t 0 in FIG. 2 ). Thereby, the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are reset and are all at H levels.

Then, as the clock CK is raised at time t 1 , the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned off and the switch MN 0 is turned on.

Thereby, through-type electric currents flow on an electric current path from the electric power terminal AVD through the inverter 11 and transistor MNC 2 to the switch MN 0 and an electric current path from the electric power terminal AVD through the inverter 12 and the transistor MNR 2 to the switch MN 0 .

Through-type electric currents flow on such two electric current paths, and thereby, the output voltages XD 1 and XD 2 are pulled down and comparison between the input voltage Vin and the reference voltage VR 2 is executed.

Because the input voltage Vin is herein lower than the reference voltage VR 2 (Vin<VR 2 ), a gate-source voltage (VGS) of the transistor MNR 2 is higher than a gate-source voltage (VGS) of the transistor MNC 2 .

For this reason, an on-resistance of the transistor MNR 2 is lower than an on-resistance of the transistor MNC 2 , and the output voltage XD 2 is lowered faster than the output voltage XD 1 .

Then, positive feedback of the inverters 11 and 12 is caused, and thereby, at time t 2 , the output voltage XD 2 is charged to be at an L level and the output voltage XD 1 is held at an H level. Here, slight lowering of the output voltage XD 1 immediately before time t 2 is an phenomenon cause by an influence of through-type electric currents flowing on both electric current paths.

Furthermore, as comparison between the input voltage Vin and the reference voltage VR 2 is ended, the transistors MNI 1 and MPI 2 are turned off, and hence, through-type electric currents do not flow.

Herein, the output voltage XD 2 is at an L level at time t 2 , and thereby, the node BTD 1 is at an H level at time t 3 so that the switches MN 01 and MN 11 are turned on. Thereby, comparison between the input voltage Vin and the reference voltage VR 1 is executed by the transistors MNC 1 and MNR 1 of the differential pair circuit 23 .

Furthermore, at this time, the output voltage XD 1 is held at an H level, and thereby the node BDT 2 is at an L level and the switches MN 03 and MN 13 are turned off, so that the differential pair circuit 24 is not operated and comparison between the input voltage Vin and the reference voltage VR 3 is not executed.

Here, a difference between times t 2 and t 3 is caused by a delay time of the inverter INV 1 .

Because the reference voltage VR 1 is herein higher than the input voltage Vin (Vin<VR 1 ), a gate-source voltage (VGS) of the transistor MNR 1 is higher than a gate-source voltage (VGS) of the transistor MNC 1 .

For this reason, an on-resistance of the transistor MNR 1 is lower than an on-resistance of the transistor MNC 1 , and the output voltage XD 0 is lowered faster than the output voltage XD 3 .

Then, positive feedback of the inverters 21 and 22 is caused, and thereby, at time t 4 , the output voltage XD 0 is changed to be at an L level and the output voltage XD 3 is held at an H level.

Here, as comparison between the input voltage Vin and the reference voltage VR 1 is ended, the transistors MNI 3 and MPI 0 are turned off, and hence, through-type electric currents do not flow.

As described above, comparison between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 is ended and levels of the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are L, H, L, and H, respectively.

Next, an operation of the comparator 100 in a case where VR 1 <Vin<VR 2 <VR 3 is held among the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 will be described by using FIG. 1 and FIG. 3 .

Because an operation from time t 0 to time t 3 is similar to a case where Vin<VR 1 <VR 2 <VR 3 is held as illustrated in FIG. 2 , a description thereof will be omitted.

Because the input voltage Vin is herein higher than the reference voltage VR 1 (VR 1 <Vin), a gate-source voltage (VGS) of the transistor MNC 1 is higher than a gate-source voltage (VGS) of the transistor MNR 1 .

For this reason, an on-resistance of the transistor MNC 1 is lower than an on-resistance of the transistor MNR 1 , and the output voltage XD 3 is lowered faster than the output voltage XD 0 .

Then, positive feedback of the inverters 21 and 22 is caused, and thereby, at time t 4 , the output voltage XD 3 is changed to be at an L level and the output voltage XD 0 is held at an H level.

Here, as comparison between the input voltage Vin and the reference voltage VR 1 is ended, the transistors MNI 0 and MPI 3 are turned off, and hence, through-type electric currents do not flow.

As described above, comparison between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 is ended, and levels of the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are H, H, L, and L, respectively.

Next, an operation of the comparator 100 in a case where VR 1 <VR 2 <Vin<VR 3 is held among the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 will be described by using FIG. 1 and FIG. 4 .

First, the clock CK is at an L level, and thereby, the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned on and the switch MN 0 is turned off.

As the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned on, the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are pulled up by the electric power source voltage AVD to be at an H levels (see time t 0 in FIG. 4 ). Thereby, the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are reset and are all at H levels.

Then, as the clock CK is raised at time t 1 , the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned off and the switch MN 0 is sunned on.

Thereby, through-type electric currents flow on an electric current path from the electric power terminal AVD through the inverter 11 and transistor MNC 2 to the switch MN 0 and an electric current path from the electric power terminal AVD through the inverter 12 and the transistor MNR 2 to the switch MN 0 .

Through-type electric currents flow on such two electric current paths, and thereby, the output voltages XD 1 and XD 2 are pulled down and comparison between the input voltage Vin and the reference voltage VR 2 is executed.

Because the input voltage Vin is herein higher than the reference voltage VR 1 (VR 2 <Vin), a gate-source voltage (VGS) of the transistor MNC 2 is higher than a gate-source voltage (VGS) of the transistor MNR 2 .

For this reason, an on-resistance of the transistor MNC 2 is lower than an on-resistance of the transistor MNR 2 , and the output voltage XD 1 is lowered faster than the output voltage XD 2 .

Then, positive feedback of the inverters 11 and 12 in caused, and thereby, at time t 2 , the output voltage XD 1 is changed to be at an L level and the output voltage XD 2 is held at an H level. Here, slight lowering of the output voltage XD 2 immediately before time t 2 is an phenomenon cause by an influence of through-type electric currents flowing on both electric current paths.

Furthermore, as comparison between the input voltage Vin and the reference voltage VR 2 is ended, the transistors MNI 2 and MPI 1 are turned off, and hence, through-type electric currents do not flow.

Herein, the output voltage XD 1 is at an L level at time t 2 , and thereby, the node BTD 2 is at an H level at time t 3 so that the switches MN 03 and MN 13 are turned on. Thereby, comparison between the input voltage Vin and the reference voltage VR 3 is executed by the transistors MNC 3 and MNR 3 of the differential pair circuit 24 .

Furthermore, at this time, the output voltage XD 2 is held at an H level, and thereby the node BDT 1 is at an L level and the switches MN 01 and MN 11 are turned off, so that the differential pair circuit 23 is not operated and comparison between the input voltage Vin and the reference voltage VR 1 is not executed.

Here, a difference between times t 1 and t 3 is caused by a delay time of the inverter INV 2 .

Because the reference voltage VR 3 is herein higher than the input voltage Vin (Vin<VR 3 ), a gate-source voltage (VGS) of the transistor MNR 3 is higher than a gate-source voltage (VGS) of the transistor MNC 3 .

For this reason, an on-resistance of the transistor MNR 3 is lower than an on-resistance of the transistor MNC 3 , and the output voltage XD 3 is lowered faster than the output voltage XD 0 .

Then, positive feedback of the inverters 21 and 22 is caused, and thereby, at time t 4 , the output voltage XD 3 is changed to be at an L level and the output voltage XD 0 is held at an H level.

Here, as comparison between the input voltage Vin and the reference voltage VR 3 is ended, the transistors MNI 0 and MPI 3 are turned off, and hence, through-type electric currents do not flow.

As described above, comparison between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 is ended and levels of the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are H, L, H, and L, respectively.

Next, an operation of the comparator 100 in a case where VR 1 <VR 2 <VR 3 <Vin is held among the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 will be described by using FIG. 1 and FIG. 5 .

Because an operation from time t 0 to time t 3 is similar to a case where VR 1 <VR 2 <Vin<VR 3 is held as illustrated in FIG. 4 , a description thereof will be omitted.

Because the input voltage Vin is herein higher than the reference voltage VR 3 (VR 3 <Vin), a gate-source voltage (VGS) of the transistor MNC 3 is higher than a gate-source voltage (VGS) of the transistor MNR 3 .

For this reason, an on-resistance of the transistor MNC 3 is lower than an on-resistance of the transistor MNR 3 , and the output voltage XD 0 is lowered faster than the output voltage XD 3 .

Then, positive feedback of the inverters 21 and 22 is caused, and thereby, at time t 4 , the output voltage XD 0 is changed to be at an L level and the output voltage XD 3 is held at an H level.

Here, as comparison between the input voltage Vin and the reference voltage VR 3 is ended, the transistors MNI 3 and MPI 0 are turned off, and hence, through-type electric currents do not flow.

As described above, comparison between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 is ended and levels of the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are L, L, H, and H respectively.

Next, a configuration for connecting a NAND-type latch circuit and an encoding part to the output terminals XD 0 , XD 1 , XD 2 , and XD 3 of the comparator 100 will be described by using FIG. 6 .

FIG. 6 is a diagram illustrating a configuration of a comparator circuit 1000 that includes the comparator 100 in the first embodiment.

The comparator circuit 1000 includes a comparator circuit part 500 and an encoding part 50 .

The comparator circuit part 500 includes the comparator 100 and NAND-type latch circuits 30 and 40 .

Because the output voltages XD 0 , XD 1 , XD 2 , and XD 3 of the comparator 100 are outputs at an H level at a time when the clock CK is at an L level, the output terminals XD 1 and XD 2 and the output terminals XD 0 and XD 3 are at states of “H” and “H”, respectively, and outputs of the latch circuits 30 and 40 hold respective previous output states. Elements of this part are referred to as a comparator part and separated from an encoding part for encoding such outputs into 2 bit digital codes.

Herein, in FIG. 6 , the comparator 100 illustrated in FIG. 1 is simplified to illustrate only the input terminal Vin, the reference terminals VR 1 , VR 2 , and VR 3 , the clock input terminal CK, and the output terminals XD 0 , XD 1 , XD 2 , and XD 3 .

In the comparator circuit part 500 , the NAND-type latch circuits 30 and 40 are connected to the output terminals XD 1 and XD 2 and the output terminals XD 0 and XD 3 of the comparator 100 , respectively, as illustrated in FIG. 6 .

Two input terminals of the NAND-type latch circuit 30 are respectively connected to the output terminals XD 1 and XD 2 of the comparator 100 . Furthermore, the NAND-type latch circuit 30 has a pair of output terminals DO 1 and DO 2 . The NAND-type latch circuit 30 is one example of a first NAND-type latch circuit.

Two input terminals of the NAND-type latch circuit 40 are respectively connected to the output terminals XD 0 and XD 3 of the comparator 100 . Furthermore, the NAND-type latch circuit 40 has a pair of output terminals DO 0 and DO 3 . The NAND-type latch circuit 40 is one example of a second NAND-type latch circuit.

During a reset term where the clock CL is at an L level, the output voltages XD 0 , XD 1 , XD 2 , and XD 3 of the comparator 100 are all reset at H levels. This is executed in each period of time of the clock CK.

The reason why the NAND-type latch circuits 30 and 40 are used at an output side of the comparator 100 is that a result of comparison at a state before being reset is held during a reset period of time.

Furthermore, the encoding part 50 includes input terminals 50 A, 50 B, 50 C, and 50 D, NAND circuits 51 , 52 , and 53 , and output terminals D 0 and D 1 .

The input terminals 50 A, 50 B, 50 C, and 50 D are connected to the output terminals DO 0 , DO 1 , DO 2 , and DO 3 , respectively.

One input terminal of the NAND circuit 51 (at an upper side in the figure) is connected to the input terminal 50 C and the other input terminal (at a lower side in the figure) is connected to the input terminal 50 D. One input terminal of the NAND circuit 52 (at an upper side in the figure) is connected to the input terminal 50 A and the other input terminal (at a lower side in the figure) is connected to the input terminal 50 B. Output terminals of the NAND circuits 51 and 52 are respectively connected to two input terminals of the NAND circuit 53 .

The output terminal D 1 it connected to the input terminal 50 B and the output terminal D 0 is connected to an output terminal of the NAND circuit 53 .

The encoding part 50 is provided to encode four outputs that are outputted from the output terminal DO 0 , DO 1 , DO 2 , and DO 3 of the NAND-type latch circuits 30 and 40 into binary ones.

Such output levels of the output terminals XD 0 , XD 1 , XD 2 , and XD 3 of the comparator 100 , the output terminals DO 1 and DO 2 of the NAND-type latch circuit 30 , a pair of the output terminals DO 0 and DO 3 of the NAND-type latch circuit 40 , and the output terminals D 0 and D 1 are provided as illustrated in FIG. 7 .

FIG. 7 is a diagram illustrating output levels obtained in the comparator 100 in the embodiment, the NAND-type latch circuits 30 and 40 , and the encoding part 50 . In FIG. 7 , ↑(H) for the clock CK indicates raising to an H level.

Herein, output levels of the output terminals XD 0 , XD 1 , XD 2 , and XD 3 , and the output terminals DO 0 , DO 1 , DO 2 , and DO 3 are indicated as nonterminal node logics. Furthermore, output levels of the output terminals D 0 and D 1 are indicated as output logics.

As illustrated in FIG. 7 , during a reset period of time where the clock CK is at an L level, output levels of the output terminals XD 0 , XD 1 , XD 2 , and XD 3 are all at H levels but output levels of the output terminals DO 0 , DO 1 , DO 2 , and DO 3 hold a result of comparison.

Furthermore, as illustrated in FIG. 7 , it is possible for output levels of the output terminals D 0 and D 1 to represent a result of comparison between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 by 2-bit digital code. Output levels of the output terminals D 0 and D 1 are obtained by binary encoding based on output levels of the output terminals DO 0 , DO 1 , DO 2 , and DO 3 .

As described above, the comparator 100 in the first embodiment compares the input voltage Vin with the reference voltage VR 2 at a first step, and in a case where the input voltage Vin is lower than the reference voltage VR 2 , compares the input voltage Vin with the reference voltage VR 1 lower than the reference voltage VR 2 at a second step. In this case, comparison between the input voltage Vin and the reference voltage VR 3 is not executed.

Furthermore, the comparator 100 in the first embodiment compares the input voltage Vin with the reference voltage VR 2 at a first step, and in a case where the input voltage Vin is higher than the reference voltage VR 2 , compares the input voltage Vin with the reference voltage VR 3 higher than the reference voltage VR 2 at a second step. In this case, comparison between the input voltage Vin and the reference voltage VR 1 is not executed.

Therefore, it is possible to reduce a through-type electric current, and thereby, it is possible to attain reduction of electric power consumption.

In other words, comparison with a median value (VR 2 ) among three reference voltages (VR 1 , VR 2 , and VR 3 ) is executed at a first step and comparison with only one of remaining two reference voltages (VR 1 and VR 3 ) is executed at a second step, depending on a result or comparison as obtained at the first step, so that the number of transistors to be driven and reduction of electric power consumption is attained.

Furthermore, in a case where three comparators are used to compare the input voltage Vin with the three reference voltages (VR 1 , VR 2 , and VR 3 ), three NAND circuits are used and it is sufficient to connect the two NAND-type latch circuits 30 and 40 to the comparator 100 in the first embodiment.

For this reason, it is possible to reduce the number of NAND-type latch circuits in the first embodiment, so that it is also possible to attain reduction of electric power consumption.

Herein, a comparator for comparison will be described by using FIG. 8 to FIG. 11 .

FIG. 8 is a diagram illustrating a compactor circuit 9 for comparison.

The comparator circuit 90 for comparison includes a comparator circuit part 70 and an encoding part 80 .

The comparator circuit part 70 includes three comparators 71 , 72 , and 73 and three NAND-type latch circuits 74 , 75 , and 76 . Furthermore, the encoding part 80 includes NAND circuits 81 , 82 , and 83 .

Reference voltages VR 1 , VR 2 , and VR 3 are inputted to the comparators 71 , 72 , and 73 , respectively, and an operation of comparison is executed by raising of a clock CK to output a differential output representing a result of comparison with an input voltage Vin. Additionally, the reference voltages VR 1 , VR 2 , and VR 3 have a relationship of VR 1 <VR 2 <VR 3 , similarly to the first embodiment.

As illustrated in FIG. 8 , pairs of output terminals of the comparators 71 , 72 , and 73 to output differential outputs are connected to the NAND-type circuits 74 , 75 , and 76 , respectively.

There is no output destination for one output terminal of the NAND-type latch circuit 74 (at an upper side of the figure) and the other output terminal (in a lower side of the figure) is connected to the other input terminal of the NAND circuit 81 of the encoding part 80 (at a lower side of the figure).

One output terminal of the NAND-type latch circuit 75 (at an upper side of the figure) is connected to one input terminal of the NAND circuit 81 of the encoding part 80 (at an upper side of the figure) and the other output terminal (at a lower side of the figure) is connected to an output terminal D 1 of the encoding part 80 and the other input terminal of the NAND circuit 82 (at a lower side of the figure).

There is no output destination for one output terminal of the NAND-type latch circuit 76 (at an upper side of the figure) and the other output terminal (at a lower side of the figure) is connected to one input terminal of the NAND circuit 82 of the encoding part 80 (at an upper side of the figure).

An output terminal of the NAND circuit 81 of the encoding part 80 and an output terminal of the NAND circuit 82 are input terminals of the NAND circuit 83 , respectively, and an output terminal of the NAND circuit 83 is connected to an output terminal D 0 of the encoding part 80 .

In the comparator circuit part 70 of such a comparator 90 for comparison, the comparators 71 , 72 , and 73 compare the input terminal Vin with the reference voltages VR 1 , VR 2 , and VR 3 , respectively. The comparators 71 , 72 , and 73 input differential outputs representing results of comparison to the NAND-type latch circuits 74 , 75 , and 76 , respectively.

Then, the encoding part 80 outputs 2-bit outputs D 0 and D 1 representing results of comparison between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 from output terminals D 0 and D 1 , respectively, based on outputs of the NAND-type latch circuits 74 , 75 , and 76 .

Herein, a circuit configuration of the comparator 71 included in the comparator circuit part 70 of the comparator circuit 90 for comparison will be described by using FIG. 9 and FIG. 10 . The comparator 71 will be described herein, because the comparators 71 , 72 , and 73 have similar configurations.

FIG. 9 is a diagram illustrating a circuit configuration of the comparator 71 . FIG. 10 is a diagram illustrating the comparator 71 by symbols.

The comparator 71 includes a switch MN 0 , inverters 71 A and 71 B, transistors QM 1 and QM 2 , reset switches QRP 0 and QRP 1 , an input terminal Vin+, a reference terminal Vin−, an electric power terminal AVD, and output terminals OP and OM.

The inverters 71 A and 71 B have transistors QPI 1 and QNI 1 and transistors QPI 2 and QNI 2 , respectively.

The inverter 71 A, the transistor QM 1 , and the switch MN 0 compose an electric current path between an electric power terminal AVD and a ground terminal GND. Furthermore, the inverter 71 B, the transistor QM 2 , and the switch MN 0 compose an electric current path between the electric power terminal AVD and the ground terminal GND.

The reset switch QRP 0 is such that a source is connected to the electric power terminal AVD, a gate is connected to a clock input terminal CK, and a drain is connected to an output terminal of the inverter 71 A, an input terminal of the inverter 71 B, and the output terminal OP.

The reset switch QRP 1 is such that a source is connected to the electric power terminal AVD, a gate is connected to the clock input terminal CK, and a drain is connected to an input terminal of the inverter 71 A, an output terminal of the inverter 71 B, and an output terminal OM.

As a clock CK is at an L level in such a comparator 71 , the reset switches QRP 0 and QRP 1 are turned on and outputs of the output terminals OP and OM are reset at H levels. As this time, the switch MN 0 is turned off.

Furthermore, the clock CK is raised, both the reset switches QRP 0 and QRP 1 are turned off, and the switch MN 0 is turned on, so that comparison between an input voltage Vin+ and a reference voltage Vin− is executed to output differential outputs representing a result of comparison from the output terminals OP and OM.

As comparison between the input voltage Vin+ and the reference voltage Vin− is executed, through-type electric currents flow on two electric current paths. Here, although the reference voltage Vin− is illustrated herein, one of VR 1 , VR 2 , and VR 3 (see FIG. 8 ) is inputted as the reference voltage.

It is possible to denote such a comparator 71 by a symbol as illustrated in FIG. 10 . The comparator 71 illustrated in FIG. 10 includes an input terminal Vin+, a reference terminal Vin−, a clock input terminal CK, and output terminals OP and OM. Such a comparator 71 illustrated in FIG. 10 is identical to symbols for representing the comparators 71 , 72 , and 73 illustrated in FIG. 8 .

The comparator 71 is a so-called NMOS (N-channel Metal Oxide Semiconductor) differential dynamic comparator. This is also similar for the comparators 72 and 73 .

Next, magnitude relationships between the input terminal Vin and the reference voltages VR 1 , VR 2 , and VR 3 and relationships of the outputs D 0 and D 1 of the encoding part 80 therewith, in the comparator circuit 90 for comparison (see FIG. 8 ) will be described by using FIG. 11 .

FIG. 11 is a diagram illustrating outputs of the comparator circuit 90 for comparison.

In a case of Vin<VR 1 <VR 2 <VR 3 , outputs D 0 and D 1 of the encoding part 80 are L and L, respectively, due to an operation of comparison executed by raising the clock CK. Furthermore, in a case of VR 1 <Vin<VR 2 <VR 3 , outputs D 0 and D 1 of the encoding part 80 are H and L, respectively, due to an operation of comparison executed by raising the clock CK.

Furthermore, in a case of VR 1 <VR 2 <Vin<VR 3 , outputs D 0 and D 1 of the encoding part 80 are L and H, respectively, due to an operation of comparison executed by raising the clock GK. Furthermore, in a case of VR 1 <VR 2 <VR 3 <Vin, outputs D 0 and D 1 of the encoding part 50 are H and H, respectively, due to an operation of comparison executed by raising the clock CK.

Thus, 2-bit outputs D 0 and D 1 of the encoding part 80 represent a relationship with magnitude relationships between the input terminal Vin and the reference voltages VR 1 , VR 2 , and VR 3 .

As described above, according to the comparator circuit 90 for comparison, it is possible to obtain 2-bit outputs representing a result of comparison between the input voltage Vin and the three reference voltages VR 1 , VR 2 , and VR 3 , similarly to the comparator circuit 1000 (see FIG. 6 ) in the first embodiment.

However, as illustrated in FIG. 8 , the comparator circuit 90 for comparison has the three comparators 71 , 72 , and 73 to compare between the input voltage Vin and the three reference voltages VR 1 , VR 2 , and VR 3 .

Because each of the three comparators 71 , 72 , and 73 has a circuit configuration illustrated in FIG. 9 , two electric current paths are used to compare between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 , respectively, so that six electric current paths are used totally.

On the other hand, in the comparator 100 in the first embodiment, at a first step, through-type electric currents flow on two electric current paths that include the inverters 11 and 12 respectively, and at a second step, through-type electric currents flow on two electric current paths that include the inverters 21 and 22 , respectively.

For this reason, according to the first embodiment, it is possible to reduce an amount of a through-electric current, and as a result, to provide the comparator 100 with a reduced electric power consumption.

Herein, if each of the comparator parts 10 and 20 included in the comparator 100 in the first embodiment is regarded as an NMOS differential dynamic comparator, it is sufficient for an electric current for an operation of a comparator in the first embodiment to be an electric current for an operation of two NMOS differential dynamic comparators.

This is achieved by composing the comparator part 20 in such a manner that comparison between the input voltage Vin and the reference voltage VR 1 or comparison between the input voltage exclusively.

The comparator part 70 for comparison executes comparison between the input voltage Vin and the reference voltage VR 3 even in a case of Vin<VR 2 as the input voltage Vin and the three reference voltages VR 1 , VR 2 , and VR 3 (VR 1 <VR 2 <VR 3 ) are compared. Furthermore, even in a case of VR 2 <Vin, comparison between the input voltage Vin and the reference voltage VR 1 is executed.

For this reason, the comparator 70 for comparison always operates the three comparators 71 , 72 , and 73 so that this leads to an increase in electric power consumption. An operation of one of the three comparators 71 , 72 , and 73 does not relate to a result of comparison, and the comparator part 70 for comparison includes a redundant element on operation.

On the other hand, because it is sufficient to operate only the two comparator parts 10 and 20 for an operation of comparison between the input voltage Vin and the three reference voltages VR 1 , VR 2 , and VR 3 in the comparator 100 in the first embodiment, it is possible to reduce electric power consumption as compared with the comparator part 70 for comparison.

Furthermore, the comparator circuit part 70 for comparison has the three NAND-type latch circuits 74 , 75 , and 76 .

On the other hand, the two NAND-type latch circuits 30 and 40 are sufficient for the comparator circuit part 500 in the first embodiment (see FIG. 6 ). This is because it is possible for the comparator 100 to execute comparison between the input voltages Vin and the three reference voltages VR 1 , VR 2 , and VR 3 at the two comparator parts 10 and 20 and output a result of comparison to the output terminals XD 0 , XD 1 , XD 2 , and XD 3 .

The output terminals XD 0 , XD 1 , XD 2 , and XD 3 output an output representing a result of comparison at a first stage (a result of comparison between Vin and VR 2 ) in a differential form at the output terminals XD 1 and XD 2 . Furthermore, an output representing a result of comparison at a second step (a result of comparison between Vin and either one of VR 1 or VR 3 ) is outputted in a differential form at the output terminals XD 0 and XD 3 .

Therefore, the comparator circuit part 500 in the first embodiment reduces the number of NAND-type latch circuits as compared with the comparator circuit part 70 for comparison, and thereby, it is possible to reduce electric power consumption.

Herein, the number of transistors included in the comparator circuit part 500 in the first embodiment and the comparator circuit part 70 for comparison are compared on a condition that eight transistors are included in each of the NAND-type latch circuits 30 , 40 , 74 , 75 , and 76 .

The number of transistors included in the comparator circuit part 500 in the first embodiment is 43. This is a number obtained on a condition that two transistors are included in each of the inverters INV 1 and INV 2 and the comparator 100 (see FIG. 1 ) includes 27 transistors.

On the other hand, the comparator circuit part 70 for comparison includes 51 transistors because each of the comparators 71 , 72 , and 73 includes 9 transistors (see FIG. 9 ).

Therefore, it is possible for the comparator circuit part 500 in the first embodiment to reduce the number of transistors by about 15%, as compared with the comparator circuit part 70 for comparison.

For this reason, it is possible for the comparator circuit part 500 in the first embodiment to provide cost reduction thereof, as compared with the comparator circuit part 70 for comparison, because it is possible to reduce electric power consumption and it is possible to reduce a surface area of an integrated circuit.

Here, an embodiment has been described above, wherein the comparator 100 in the first embodiment includes the comparator parts 10 and 20 as so-called NMOS differential dynamic comparators. However, PMOS (p-channel Metal Oxide Semiconductor) differential dynamic comparators may be used as the comparator parts 10 and 20 , as illustrated in FIG. 12 .

FIG. 12 illustrates a diagram illustrating a circuit configuration of a comparator 100 A in an variation example of the first embodiment.

The comparator 100 A includes an input terminal Vin, reference terminals VR 1 , VR 2 , and VR 3 , output terminals XD 0 , XD 1 , XD 2 , and XD 3 , a clock input terminal CK, and an electric power terminal AVD.

The comparator 100 A further includes reset switches MN 0 , MNR 1 , MNR 2 , and MNR 3 , and a switch MP 0 .

The comparator 100 A further includes a pair of inverters 11 A and 12 A connected to provide positive feedback thereto, a differential pair circuit 13 A, and inverters INV 1 and INV 2 . The inverter 11 A has transistors MPI 1 and MNI 1 and the inverter 12 A has transistors MPI 2 and MNI 2 . Furthermore, the differential pair circuit 13 A includes transistors MPC 2 and MPR 2 .

Herein, the inverters 11 A and 12 A, the differential pair circuit 13 A, the inverters INV 1 and INV 2 , the switch MP 0 , and the reset switches MNR 1 and MNR 2 compose a comparator part 10 A. The comparator part 10 A is one example of a first comparison unit.

The comparator 100 A further includes a pair of inverters 21 A and 22 A connected to provide positive feedback thereto, switches MP 01 , MP 11 , MP 03 , and MP 13 , and differential pair circuits 23 A and 24 A.

The inverter 21 A has transistors MPI 0 and MNI 0 . The inverter 22 A has transistors MPI 0 and MNI 3 . The differential pair circuit 23 A has transistors MPR 1 and MPC 1 . The differential pair circuit 24 A has transistors MPR 3 and MPC 3 .

Herein, the inverters 21 A and 22 A, the switches MP 01 , MP 11 , MP 03 , and MP 13 , the differential pair circuits 23 A and 24 , and the reset switches MNR 0 and MNR 3 compose a comparator part 20 A. The comparator part 20 A is one example of a second comparison unit.

The comparator 100 A illustrated in FIG. 12 is such that channel types of the reset switches MNR 0 , MNR 1 , MNR 2 , and MNR 3 , the switch MP 0 , the differential pair circuit 13 A, the switches MP 01 , MP 11 , MP 03 , and MP 13 , and the differential pair circuits 23 A and 24 A in the comparator 100 illustrated in FIG. 1 are changed.

That is, the reset switches MNR 0 , MNR 1 , MNR 2 , and MNR 3 are such that p-channel types thereof in the comparator 100 illustrated in FIG. 1 are changed to N-channel types.

Furthermore, the switch MP 0 , the differential pair circuit 13 A, the switches MP 01 , MP 11 , MP 03 , and MP 13 , and the differential pair circuits 23 A and 24 are such that N-channel-types thereof in the comparator 100 illustrated in FIG. 1 are changed to p-channel types.

Thus, channel types of the transistors are inverted, so that a connection relationship between respective components in the comparator 100 A illustrated in FIG. 12 in a relationship wherein a connection relationship between respective corresponding components in the comparator 100 illustrated in FIG. 1 are inverted between the electric power terminal AVD and GND.

Furthermore, channel types of the transistors are inverted, so that reset operations of the reset switches MNR 0 , MNR 1 , MNR 2 , and MNR 3 are executed when a clock CK is at an H level, and an operation of comparison is started when the clock CK falls to an L level.

Herein, details of an operation of the comparator 100 A are similar to those of an operation of the comparator 100 illustrated in FIG. 1 and hence will be omitted, but nonterminal node logics corresponding to those in FIG. 7 are illustrated in FIG. 13 .

FIG. 10 is a diagram illustrating nonterminal node logics XD 0 , XD 1 , XD 2 , and XD 3 of the comparator 100 A in the variation example of the first embodiment.

As the clock CK is at an H level as illustrated in FIG. 13 to execute a reset operation, output levels of the output terminals XD 0 , XD 1 , XD 2 , and XD 3 are all at L levels.

Furthermore, a result of execution of an operation or comparison is a result similar to that of the comparator 100 illustrated in FIG. 7 .

Therefore, it is also possible to reduce through-type electric currents in the comparator 100 A illustrated in FIG. 12 similarly to the comparator 100 illustrated in FIG. 1 , and thereby, it is possible to attain reduction of electric power consumption.

Second Embodiment

FIG. 14 is a diagram illustrating a comparator circuit 2000 in a second embodiment.

The comparator circuit 2000 in the second embodiment is such that an EOC (End of Conversion) generation part 210 is added to the comparator circuit 1000 (see FIG. 6 ) in the first embodiment. Because the other configurations are similar to those of the comparator circuit 1000 in the first embodiment, an identical reference numeral is attached to each similar component and a description thereof will be omitted.

The EOC generation part 210 generates an EOC signal indicating an end of an operation of comparison in the comparator 100 .

The EOC generation part 210 includes a NAND circuit 211 and an output terminal 212 . Two input terminals of the NAND circuit 211 are respectively connected to the output terminals XD 0 and XD 3 of the comparator 100 .

In the comparator 100 , outputs of the output terminals XD 1 and XD 2 have already been determined at a stage for determining outputs of the output terminals XD 0 and XD 3 .

This is because the output terminals XD 1 and XD 2 output a result of an operation of comparison at a first step in the comparator part 10 (an operation of comparison between an input voltage Vin and a comparison voltage VR 2 ) and the output terminals XD 0 and XD 3 output a result of an operation of comparison at a second step in the comparator part 20 (an operation of comparison between the input voltage Vin and a comparison voltage VR 1 or VR 3 ).

For this reason, it is sufficient to use only outputs of the output terminals XD 0 and XD 3 in order to generate an EOC signal indicating an end of an operation of comparison at the EOC generation cart 210 .

An EOC signal outputted from the output terminal 212 of the EOC generation part 210 is at an H level. This is because the comparator 100 is reset so that both output levels of the output terminals XD 0 and XD 3 at H level states are changed when an operation of comparison is ended, in such a manner that either one of the output levels of the output terminals XD 0 and XD 3 is at an L level (see FIG. 7 ).

Therefore, according to the second embodiment, it is possible to obtain an EOC signal by merely adding the EOC generation part 210 including one NAND circuit 211 thereto. Because the EOC generation part 210 is composed of one NAND circuit 211 , it is possible to generate an EOC signal by merely using four transistors so that it is possible to attain reduction of electric power consumption.

Herein, a comparator circuit 90 A for comparison will be described by using FIG. 15 .

FIG. 15 is a diagram illustrating the comparator circuit 90 A for comparison. The comparator circuit 90 A for comparison is such that an EOC generation part 91 is added to the comparator circuit 90 for comparison illustrated in FIG. 8 .

The EOC generation part 91 include three NAND circuits 92 , 93 , and 94 , an AND circuit 95 , and an output terminal 96 .

Two input terminals of the NAND circuit 92 are connected to the two output terminals of the comparator 71 , respectively. An output terminal of the NAND circuit 92 is connected to one of three input terminals of the AND circuit 95 .

Two input terminals of the NAND circuit 93 are connected to the two output terminals of the comparator 72 , respectively. An output terminal of the NAND circuit 93 is connected to one of three input terminals of the AND circuit 95 .

Two input terminals of the NAND circuit 94 are connected to the two output terminals of the comparator 73 , respectively. An output terminal of the NAND circuit 94 is connected to one of three input terminals of the AND circuit 95 .

Three input terminals of the AND circuit 95 are respectively connected to output terminals of the NAND circuits 92 , 93 , and 94 and an output terminal thereof is connected to the output terminal 96 .

The output terminal 96 generates an EOC signal.

Because operations of comparison in the comparators 71 , 72 , and 73 of the comparator circuit part 70 are executed in parallel in the comparator circuit 91 A for comparison, a pair of outputs of each of the comparators 71 , 72 , and 73 is not determined until operations of comparison are all determined.

For this reason, the EOC generation part 91 including the three NAND circuits 92 , 93 , and 94 and the AND circuit 95 , as illustrated in FIG. 15 , is added to the comparator circuit 90 for comparison illustrated in FIG. 8 in order to obtain an EOC signal therein.

The EOC generation part 91 includes the three NAND circuits 92 , 93 , and 94 and the three-input AND circuit 95 .

The three NAND circuits 92 , 93 , and 94 are circuits for detecting completion of operations of comparison in the comparators 71 , 72 , and 73 , respectively. Furthermore, it is not possible to know which comparator ( 71 , 72 , or 73 ) completes a conversion finally depending on an input voltage because a period of time for completion of an operation of comparison is longer when an electric potential difference of a differential pair of a dynamic comparator is smaller, and hence, the three-input AND circuit 95 detects outputs of the NAND circuits 92 , 93 and 94 being all at H levels and outputs an EOC signal at an H level.

Herein, calculation is executed in such a manner that each of the NAND circuits 211 , 92 , 93 , and 94 includes four transistors and the three-input AND circuit 95 includes six transistors.

As a result, the number of transistors in the EOC generation part 210 of the comparator circuit 2000 illustrated in FIG. 14 is fourteen less than that of the EOC generation part 91 of the comparator circuit 90 A illustrated in FIG. 15 .

Therefore, according to the second embodiment, it is possible to obtain further reduction of electric power consumption in a case where an EOC signal is generated.

Third Embodiment

A comparator 300 in a third embodiment is such that a DTCK (Delay Time Clock) terminal is added to the comparator 100 in the first embodiment (see FIG. 1 ). Because the other configurations are similar to those of the comparator 100 in the first embodiment, an identical reference numeral is attached to a similar component and a description thereof will be omitted.

FIG. 16 is a diagram illustrating the comparator 300 in the third embodiment.

The comparator 300 in the third embodiment is such that nor operation circuits NOR 1 and NOR 2 are used instead of the inverters INV 1 and INV 2 of the comparator 100 in the first embodiment (see FIG. 1 ), respectively, and a DTCK terminal is added thereto.

One input terminal of the nor operation circuit NOR 1 (at an upper side in the figure) is connected to the DTCK terminal and the other input connected to an input terminal or the inverter 11 , an output terminal of the inverter 12 , and the output terminal XD 2 . An output terminal of the nor operation circuit NOR 1 is connected to gates of the switches MN 01 and MN 11 (node BTD 1 ). The nor operation circuit NOR 1 is one example of a first NOR circuit.

One input terminal of the nor operation circuit NOR 2 (at an upper side in the figure) is connected to an output terminal of the inverter 11 , an input terminal of the inverter 12 , and the output terminal XD 1 , and the other input terminal (at a lower side in the figure) is connected to the DTCK terminal. An output terminal of the nor operation circuit NOR 2 is connected to gates of the switches MN 03 and MN 13 (node BTD 2 ). The nor operation circuit NOR 2 is one example of a second NOR circuit.

When an operation of comparison at a second step is started by the comparator part 20 after an operation of comparison at a first step is ended by the comparator part 10 , raising of a clock is inputted to the DTCK terminal.

As a result, an output of the corresponding nor operation circuit NOR 1 or NOR 2 is at an H level and the corresponding node BTD 1 or BTD 2 is at an H level, so that an operation of comparison at a second step in the comparator 20 (an operation of comparison between the input voltage Vin and the comparison voltage VR 1 or VR 3 ) is started.

That is, falling of a clock is inputted to the DTCK terminal in the third embodiment, and thereby, it is possible for the comparator part 30 to start an operation of comparison at a second step.

For example, a voltage fluctuation caused by noise may be caused (ringing may be caused) on an electric power source electric potential inputted from an electric power terminal AVD or a GND electric potential, due to a resistance component R, a capacitance component C, an inductance component L, or the like, of a wiring of a package member for mounting a comparator circuit including the comparator 300 thereon or the like. Furthermore, a kick back voltage may be caused by an operation of comparison in the comparator 100 to change the input voltage Vin.

Because it is possible to use the comparator 300 in the third embodiment for, for example, SAR (Successive AppRoximation), ADC (Analog to Digital Converter), a pipeline ADC, or a Flash-type ADC, or the like, it is possible to provide, for example, a package circuit of a comparator included in these ADCs or the like, for the aforementioned package component.

There is a possibility of causing such a voltage fluctuation in the comparator 300 in the third embodiment, and it is effective in a case where a comparatively long period of time is taken for convergence of a voltage fluctuation after an operation for comparison at a first step is ended or in a case where it is desired that a time for starting an operation at a second step be delayed.

For this reason, it is sufficient for a clock DTCK inputted to the DTCK terminal to be a clock delayed by a predetermined delay time with respect to the clock input terminal CK.

It is sufficient for this delay time to be a time for delaying falling of a clock DTCK with respect to raising of a clock CK, by a period of time necessary to converge a change in the input voltage Vin as caused by a kick back voltage involved with an operation of comparison in the comparator 100 . Here, this delay time is a time less than one cycle of a clock CK, and it is sufficient for generation of the clock DTCK to be executed by delaying the clock CK by using, for example, a digital delay line or the like.

Herein, an operation of the comparator 300 in the third embodiment will be described by using FIG. 17 . An operation illustrated in FIG. 17 is an operation corresponding to the operation of the comparator 100 in the first embodiment as illustrated in FIG. 2 (an operation in a case where Vin<VR 1 <VR 2 <VR 3 is held).

FIG. 17 is a timing chart illustrating an operation of the comparator 300 in the third embodiment. FIG. 17 illustrates voltage levels (H (High) or L (Low)) of the clock input terminal CK, the output terminal XD 1 and XD 2 , the DTCK terminal, the nodes BTD 1 and BTD 2 , the output terminal XD 3 and XD 0 .

Furthermore, in the following, a clock to be inputted to the clock input terminal CK is referred to as a clock CK, voltages of the output terminals XD 1 , XD 2 , XD 3 , and XD 4 are referred to as output voltages XD 1 , XD 2 , XD 3 , and XD 4 , and a voltage to be inputted to the electric power terminal AVD is referred to as an electric power source voltage AVD. Furthermore, a clock to be inputted to the DTCK terminal is referred to as a clock DTCK.

Here, times t 1 , t 2 , t 3 , and t 4 that will be described below are different from the times t 1 , t 2 , t 3 , and t 4 illustrated in FIG. 2 to FIG. 5 .

First, the clock CK is at an L level, so that the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned on and the switch MN 0 is turned off.

As the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are turned on, the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are pulled up by the electric power source voltage AVD to be at H levels (see time t 0 in FIG. 17 ). Thereby, the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are reset to be all at H levels.

Then, as the clock CK is raised at time t 1 , the reset switches MPR 0 , MPR 1 , MPR 2 , and MPR 3 are tuned off and the switch MN 0 is turned on.

Thereby, through-type electric currents flow on an electric current path from the electric power terminal AVD through the inverter 11 and the transistor MNC 2 to the switch MN 0 and an electric current path from the electric power terminal AVD to the transistor MNR 2 to the switch MN 0 .

Through-type electric currents flow on the two electric current paths, and thereby, the output voltages XD 1 and XD 2 are pulled down to execute comparison between the input voltage Vin and the reference voltage VR 2 .

Herein, a gate source voltage (VGS) of the transistor MNR 2 is higher than a gate-source voltage (VGS) of the transistor MNC 2 , because the input voltage Vin is lower than the reference voltage VR 2 (Vin<VR 2 ).

For this reason, an on-resistance of the transistor MNR 2 is lower than an on-resistance of the transistor MNC 2 , so that the output voltage XD 2 is lowered faster than the output voltage XD 1 .

Then, positive feedback of the inverters 11 and 12 is caused so that the output voltage XD 2 is changed to be at an L level at time t 2 and the output voltage XD 1 is held at an H level. Here, slight lowering of the output voltage XD 1 immediately before time t 2 is an phenomenon cause by an influence of through-type electric currents flowing on both electric current paths.

Furthermore, as comparison between the input voltage Vin and the reference voltage VR 2 is ended, the transistors MNI 1 and MPI 2 are turned off, and hence, through-type electric currents do not flow. Thereby, an operation of comparison at a first step is ended.

Herein, the output voltage XD 2 is at an L level at time t 2 so that a signal at an L level is inputted to the other input terminal of the nor operation circuit NOR 1 (at a lower side in the figure), but the clock DTCK is at an H level at time t 2 , and hence, an output of the nor operation circuit NOR 1 is at an L level.

Then, as the clock DTCK starts to fall at time t 3 , a level of the code BTD 1 starts to rise at time t 4 and the node BTD 1 is at an H level at time t 5 so that the switches MN 01 and MN 11 are turned on. Thereby, comparison between the input voltage Vin and the reference voltage VR 1 is executed by the transistors MNC 1 and MNR 1 of the differential pair circuit 23 .

Furthermore, at this time, the output voltage XD 1 is held at an H level so that the node BDT 2 is at an L level and the switches MN 03 and MN 13 are turned off, and hence, the differential pair circuit 24 is not operated so that comparison between the input voltage Vin and the reference voltage VR 3 is not executed.

Herein, the reference voltage VR 1 is higher than the input voltage Vin (Vin<VR 1 ), and hence, a gate-source voltage (VGS) of the transistor MNR 1 is higher than a gate-source voltage (VGS) of the transistor MNC 1 .

For this reason, an on-resistance of the transistor MNR 1 is lower than an on-resistance of the transistor MNC 1 so that the output voltage XD 0 is lowered faster than the output voltage XD 3 .

Then, positive feedback of the inverters 21 and 22 is caused so that the output voltage XD 0 is changed to be at an L level at time t 6 and the output voltage XD 3 is held at an H level.

Here, as comparison between the input voltage Vin and the reference voltage VR 1 is ended, the transistors MNI 3 and MPI 0 are turned off so that through-type electric currents do not flow.

As described above, comparison between the input voltage Vin and the reference voltages VR 1 , VR 2 , and VR 3 is ended, so that levels of the output voltages XD 0 , XD 1 , XD 2 , and XD 3 are L, H, L, and H, respectively.

Here, FIG. 17 illustrates an operation corresponding to the operation of the comparator 100 in the first embodiment as illustrated in FIG. 2 (an operation in a case where Vin<VR 1 <VR 2 <VR 3 is held) as one example.

However, an operation of comparison at a second step is also started by falling of the clock DTCK after an operation of comparison at a first step is ended, similarly for an operation in a case where VR 1 <Vin<VR 2 <VR 3 is held (see FIG. 3 ), an operation in a case where VR 1 <VR 2 <Vin<VR 3 is held (see FIG. 4 ), or an operation in a case where VR 1 <VR 2 <VR 3 <Vin is held (see FIG. 5 ).

Therefore, according to the comparator 300 in the third embodiment, it is possible to reduce through-type electric currents, and thereby, it is possible to attain reduction of electric power consumption.

There is a possibility of causing a voltage fluctuation as described above for the comparator 300 in the third embodiment, and it is effective in a case where a comparatively long period of time is taken for convergence of a voltage fluctuation after an operation of comparison at a first step is ended, or in a case where it is desired that a time for starting an operation at a second step be delayed.

Here, although the terms a comparator ( 100 , 200 ), a comparator circuit part ( 500 ), and a comparator circuit ( 1000 , 2000 ) have been used in the aforementioned embodiments 1 to 3, these terms are used for making distinction for the purpose of illustration. Therefore, it is possible to treat all of a comparator ( 100 , 300 ), a comparator circuit part ( 500 ), and a comparator circuit ( 1000 , 2000 ) as comparators.

According to an illustrative embodiment of the present invention, it is possible to provide a comparator intended to reduce electric power consumption thereof.

Although comparators in illustrative embodiments of the present invention have been described above, the present invention is not limited to specifically disclosed embodiments and it is possible to apply a variety of alterations or modifications thereto, without departing from the claims.

All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specially recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.