Semiconductor devices and semiconductor systems including the same

The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2013-0113305, filed on Sep. 24, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

1. Technical Field

Embodiments of the present disclosure generally relate to semiconductor devices and semiconductor systems including the same.

2. Related Art

Currently known semiconductor devices may execute a write operation to store data therein and, likewise, may execute a read operation to output the data stored therein. To execute the write operation or the read operation, the semiconductor devices may selectively enable a word line using a row address signal to create a row path. Alternatively, the semiconductor devices may activate a switching element, coupled between a sense amplifier and an input/output (I/O) line, using a column selection signal generated by a column address signal. Upon activation of the switching element as described, the semiconductor devices may then create a column path.

Each of the semiconductor devices may be designed to include several input/output (“I/O”) lines for outputting data. Further, the devices may also include sense amplifiers that may sense and amplify a voltage difference (ΔV) between a pair of I/O lines selected by a column address signal. The sense amplifiers may then output the data during the read operation.

During the read operation of the semiconductor device, at least one of the I/O lines may be selected by the column address signal while the remaining I/O lines may remain non-selected. In such an instance, a loading capacitance between the selected I/O line and the non-selected I/O lines adjacent thereto may degrade a function of the sense amplifier to increase a data access time of the semiconductor device.

Various embodiments are directed to semiconductor devices and semiconductor systems including the same.

According to some embodiments, a semiconductor system includes a controller and a semiconductor device. The controller is suitable for generating command signals and address signals. The semiconductor device is suitable for electrically disconnecting a first local line from a second local line in response to an input control signal. Such an electrical disconnect occurs when the input control signal is enabled in a read mode set according to a logic combination of the command signals. Further, the semiconductor device is suitable for sensing and amplifying a data on the first local line or the second local line according to the address signals to output the amplified data through an input/output line.

According to several embodiments, a semiconductor device includes a command decoder, an address decoder, an input/output controller and a data input/output unit. The command decoder is suitable for decoding command signals supplied from an external device to generate a read signal enabled in a read mode. Similarly, the address decoder is suitable for decoding the address signals supplied from the external device to generate internal address signals. The input/output controller is suitable for generating an input control signal in response to the read signal. Further, the input/output controller is suitable for generating a first column selection signal group and a second column selection signal group in response to the internal address signals. One signal of the first column selection signal group and one signal of the second column selection signal group are selectively enabled according to the internal address signals. The data input/output unit is suitable for sensing and amplifying a data loaded on a first local line to output an amplified signal of the data on the first local line through an input/output line when one signal of the first column selection signal group is enabled. Further, the data input/output unit is suitable for sensing and amplifying a data loaded on a second local line to output an amplified signal of the data on the second local line through the input/output line when one signal of the second column selection signal group is enabled.

Moreover, a method for operating a semiconductor device is provided. The method includes generating a command signal and an address signal by a controller and configuring the semiconductor device to electrically disconnect a first local line from a second local line in response to an input control signal wherein the input control signal is enabled in a read mode. A logic combination of the command signal sets the read mode and a command decoder decodes the command signal to generate a read signal.

The method decodes the address signal with an address decoder to generate an internal address signal, generates an input control signal in response to the read signal by an input/output controller and senses and amplifies a data by a data input/output unit on the first local line or the second local line according to the address signal to output the amplified data through an input/output line.

Embodiments of the present invention will become more apparent in view of the attached drawings and accompanying detailed description, in which:

FIG. 1 is a block diagram illustrating a semiconductor system according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a data I/O unit included in the semiconductor system of FIG. 1 ;

FIG. 3 is a circuit diagram illustrating an isolator included in the data I/O unit of FIG. 2 ;

FIG. 4 is a circuit diagram illustrating a first pre-charger included in the data I/O unit of FIG. 2 ; and

FIG. 5 is a circuit diagram illustrating a second pre-charger included in the data I/O unit of FIG. 2 .

Various embodiments of the present invention will be described herein with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present invention.

Referring to FIG. 1 , a semiconductor system according to the present embodiment may include a controller 10 and a semiconductor device 20 .

The controller 10 may generate command signals CMD< 1 :N> and address signals ADD< 1 :N> to apply the command signals CMD< 1 :N> and the address signals ADD< 1 :N> to the semiconductor device 20 (wherein, “N” denotes a natural number which is equal to or greater than two).

The semiconductor device 20 may include a command decoder 21 , an address decoder 22 , an input/output (I/O) controller 23 and a data I/O unit 24 . The command decoder 21 may generate a read signal RD enabled in a read mode which is set according to a logic combination of the command signals CMD< 1 :N>. The address decoder 22 may decode the address signals ADD< 1 :N> to generate internal address signals IADD< 1 :N>. The I/O controller 23 may generate an input control signal DINEN enabled when the read signal RD is inputted thereto. Further, the I/O controller 23 may generate a first column selection signal group YB 1 < 1 :N>, one signal of which is selectively enabled according to a logic combination of the internal address signals IADD< 1 :N> and may generate a second column selection signal group YB 2 < 1 N>, one signal of which is selectively enabled according to a logic combination of the internal address signals IADD< 1 :N>. The data I/O unit 24 may sense and amplify data of local lines in response to the first and second column selection signal groups YB 1 < 1 :N> and YB 2 < 1 :N> to output the amplified data. The input control signal DINEN may be disabled in a write mode.

A configuration of the data I/O unit 24 will be described more fully herein with reference to FIG. 2 .

Referring to FIG. 2 , the data I/O unit 24 may include a first switching unit 241 , a second switching unit 242 , an isolator 243 , a first I/O line driver 244 and a second I/O line driver 245 .

The first switching unit 241 may electrically connect a pair of segment lines selected from a first segment line group SIO 1 < 1 >, SIO 1 B< 1 >˜SIO 1 <N>, SIO 1 B<N> according to the enabled column selection signal of the first column selection signal group YB 1 < 1 :N> to a pair of first local lines LIO 1 and LIO 1 B. The first segment line group SIO 1 < 1 >, SIO 1 B< 1 >˜SIO 1 <N>, SIO 1 B<N> may correspond to data transmission lines that are electrically connected to memory cells of the semiconductor device 20 to input or output the data. In the first segment line group SIO 1 < 1 >, SIO 1 B< 1 >˜SIO 1 <N>, SIO 1 B<N>, complementary segment lines SIO 1 B< 1 >˜SIO 1 B<N> may be data transmission lines having complementary levels of signals transmitted through the segment lines SIO 1 < 1 >˜SIO 1 <N>, respectively.

The second switching unit 242 may electrically connect a pair of segment lines selected from a second segment line group SIO 2 < 1 >, SIO 2 B< 1 >˜SIO 2 <N>, SIO 2 B<N> according to the enabled column selection signal of the second column selection signal group YB 2 < 1 :N> to a pair of second local lines LIO 2 and LIO 2 B. The second segment line group SIO 2 < 1 >, SIO 2 B< 1 >˜SIO 2 <N>, SIO 2 B<N> may correspond to data transmission lines that are electrically connected to memory cells of the semiconductor device 20 to input or output the data. In the second segment line group SIO 2 < 1 >, SIO 2 B< 1 >˜SIO 2 <N>, SIO 2 B<N>, complementary segment lines SIO 2 B< 1 >˜SIO 2 B<N> may be data transmission lines having complementary levels of signals transmitted through the segment lines SIO 2 < 1 >˜SIO 2 <N>, respectively.

The isolator 243 may electrically disconnect the first local lines LIO 1 and LIO 1 B from the second local lines LIO 2 and LIO 2 B in response to the input control signal DINEN (e.g. DINEN is enabled when the semiconductor device 20 operates in the read mode).

The first I/O line driver 244 may include a first pre-charger 2441 and a first sense amplifier (S/A) 2442 . The first pre-charger 2441 may pre-charge the pair of first local lines LIO 1 and LIO 1 B to a level which is lower than that of a power supply voltage VDD in a pre-charge mode. The first S/A 2442 may sense and amplify a voltage difference (ΔV) between a pair of first transmission lines TL 1 and TL 1 B, which are driven to have a lower level than the pair of first local lines LIO 1 and LIO 1 B in the read mode, to drive an I/O line GIO. The power supply voltage VDD may be generated in the semiconductor device 20 or may be supplied from an external device.

The second I/O line driver 245 may include a second pre-charger 2451 and a second sense amplifier (S/A) 2452 . The second pre-charger 2451 may pre-charge the pair of second local lines LIO 2 and LIO 2 B to a level which is lower than that of the power supply voltage VDD in the pre-charge mode. The second S/A 2452 may sense and amplify a voltage difference (ΔV) between a pair of second transmission lines TL 2 and TL 2 B, where the second transmission lines TL 2 and TL 2 B are driven to have a lower level than the pair of second local lines LIO 2 and LIO 2 B in the read mode, and also to drive the I/O line GIO.

A configuration of the isolator 243 will be described more fully herein with reference to FIG. 3 .

Referring to FIG. 3 , the isolator 243 may include a first switching element N 21 and a second switching element N 22 . The first switching element N 21 may be turned off in response to the input control signal DINEN enabled to have a logic “low” level in the read mode to electrically disconnect the first local line LIO 1 from the second local line LIO 2 . The second switching element N 22 may be turned off in response to the input control signal DINEN disabled to have a logic “low” level in the read mode to electrically disconnect the first complementary local line LIO 1 B from the second complementary local line LIO 2 B. The first and second complementary local lines LIO 1 B and LIO 2 B may be data transmission lines having complementary levels of signals transmitted through the first and second local lines LIO 1 and LIO 2 , respectively.

A configuration of the first pre-charger 2441 will be described more fully hereinafter with reference to FIG. 4 .

Referring to FIG. 4 , the first pre-charger 2441 may include a PMOS transistor P 21 , a PMOS transistor P 22 , a PMOS transistor P 23 , an NMOS transistor N 23 and an NMOS transistor N 24 . The PMOS transistor P 21 may be coupled between the first local line LIO 1 and the first complementary local line LIO 1 B and may be turned on in response to a pre-charge signal PCGB enabled to have a logic “low” level in a pre-charge mode to electrically connect the first local line LIO 1 to the first complementary local line LIO 1 B.

The PMOS transistor P 22 may be coupled between a power supply voltage VDD terminal and a node ND 21 and may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node ND 21 electrically connected to the first transmission line TL 1 to have the power supply voltage VDD.

The PMOS transistor P 23 may be coupled between the power supply voltage VDD terminal and a node ND 22 and may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node ND 22 electrically connected to the first complementary transmission line TL 1 B to have the power supply voltage VDD.

The NMOS transistor N 23 may be coupled between the node ND 21 and the first local line LIO 1 and may be turned on in response to the power supply voltage VDD signal to electrically connect the first local line LIO 1 to the first transmission line TL 1 .

The NMOS transistor N 24 may be coupled between the node ND 22 and the first complementary local line LIO 1 B and may be turned on in response to the power supply voltage VDD signal to electrically connect the first complementary local line LIO 1 B to the first complementary transmission line TL 1 B.

Further explained, in the pre-charge mode, the first pre-charger 2441 may drive the first local line LIO 1 to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 23 and may drive the first complementary local line LIO 1 B to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 24 . Further, in the read mode, the first pre-charger 2441 may drive the first transmission line TL 1 to have a level which is lower than that of the first local line LIO 1 by a threshold voltage (Vt) of the NMOS transistor N 23 and may drive the first complementary transmission line TL 1 B to have a level which is lower than that of the first complementary local line LIO 1 B by a threshold voltage (Vt) of the NMOS transistor N 24 .

A configuration of the second pre-charger 2451 will be described more fully hereinafter with reference to FIG. 5 .

Referring to FIG. 5 , the second pre-charger 2451 may include a PMOS transistor P 24 , a PMOS transistor P 25 , a PMOS transistor P 26 , an NMOS transistor N 25 and an NMOS transistor N 26 .

The PMOS transistor P 24 may be coupled between the second local line LIO 2 and the second complementary local line LIO 2 B and may be turned on in response to the pre-charge signal PCGB enabled to have a logic “low” level in the pre-charge mode to electrically connect the second local line LIO 2 to the second complementary local line LIO 2 B.

The PMOS transistor P 25 may be coupled between the power supply voltage VDD terminal and a node ND 23 and may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node ND 23 electrically connected to the second transmission line TL 2 to have the power supply voltage VDD.

The PMOS transistor P 26 may be coupled between the power supply voltage VDD terminal and a node ND 24 and may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node ND 24 electrically connected to the second complementary transmission line TL 2 B to have the power supply voltage VDD.

The NMOS transistor N 25 may be coupled between the node ND 23 and the second local line LIO 2 and may be turned on in response to the power supply voltage VDD signal to electrically connect the second local line LIO 2 to the second transmission line TL 2 .

The NMOS transistor N 26 may be coupled between the node ND 24 and the second complementary local line LIO 2 B and may be turned on in response to the power supply voltage VDD signal to electrically connect the second complementary local line LIO 2 B to the second complementary transmission line TL 2 B. Further explained, in the pre-charge mode, the second pre-charger 2451 may drive the second local line LIO 2 to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 25 and may drive the second complementary local line LIO 2 B to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 26 . Further, in the read mode, the second pre-charger 2451 may drive the second transmission line TL 2 to have a level which is lower than that of the second local line LIO 2 by a threshold voltage (Vt) of the NMOS transistor N 25 and may drive the second complementary transmission line TL 2 B to have a level which is lower than that of the second complementary local line LIO 2 B by a threshold voltage (Vt) of the NMOS transistor N 26 .

Operations of the semiconductor system having the aforementioned configuration will be described hereinafter with reference to FIGS. 1 to 5 in relation to the pre-charge mode and the read mode. In the read mode, a data on the first local line LIO 1 will be outputted through the I/O line GIO.

First, an operation of the pre-charge mode will be described hereinafter in conjunction with an example that the pre-charge signal PCGB is enabled to have a logic “low” level.

As illustrated in FIG. 4 , the PMOS transistor P 21 of the first pre-charger 2441 may be turned on in response to the pre-charge signal PCGB having a logic “low” level to electrically connect the first local line LIO 1 to the first complementary local line LIO 1 B. The PMOS transistor P 22 may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node ND 21 to have the power supply voltage VDD. The NMOS transistor N 23 may be turned on in response to the power supply voltage VDD signal to drive the first local line LIO 1 to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) thereof. The PMOS transistor P 23 may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node nd 22 to have the power supply voltage VDD. The NMOS transistor N 24 may be turned on in response to the power supply voltage VDD signal to drive the first complementary local line LIO 1 B to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) thereof.

Further explained, in the pre-charge mode, the first pre-charger 2441 may drive the first local line LIO 1 to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 23 and may drive the first complementary local line LIO 1 B to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 24 .

As shown in FIG. 5 , the PMOS transistor P 24 of the second pre-charger 2451 may be turned on in response to the pre-charge signal PCGB having a logic “low” level to electrically connect the second local line LIO 2 to the second complementary local line LIO 2 B. The PMOS transistor P 25 may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node nd 23 to have the power supply voltage VDD. The NMOS transistor N 25 may be turned on in response to the power supply voltage VDD signal to drive the second local line LIO 2 to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) thereof. The PMOS transistor P 26 may be turned on in response to the pre-charge signal PCGB having a logic “low” level to drive the node nd 24 to have the power supply voltage VDD. The NMOS transistor N 26 may be turned on in response to the power supply voltage VDD signal to drive the second complementary local line LIO 2 B to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) thereof.

Further explained, in the pre-charge mode, the second pre-charger 2451 may drive the second local line LIO 2 to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 25 and may also drive the second complementary local line LIO 2 B to have a level which is lower than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 26 .

Returning now to FIG. 4 , and as described above, when the semiconductor system operates in the pre-charge mode, the first local line LIO 1 and the first complementary local line LIO 1 B may be driven to have a lower level than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 23 and a lower level than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 24 , respectively. Further, when the semiconductor system operates in the pre-charge mode, the second local line LIO 2 and the second complementary local line LIO 2 B may be driven to have a lower level than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 25 and a lower level than the power supply voltage VDD by a threshold voltage (Vt) of the NMOS transistor N 26 , respectively. Thus, as discussed here, power consumption of the semiconductor system may be reduced in the pre-charge mode.

Next, as shown in FIG. 1 , an operation of the read mode will be described herein with an example that a data on the first local line LIO 1 is outputted through the I/O line GIO.

The controller 10 may apply the command signals CMD< 1 :N> for putting the semiconductor device 20 in the read mode and the address signals ADD< 1 :N> for outputting the data on the first local line LIO 1 to the semiconductor device 20 .

The command decoder 21 may decode the command signals CMD< 1 :N> to generate the read signal RD.

The address decoder 22 may decode the address signals ADD< 1 :N> to generate the internal address signals IADD< 1 :N>.

The I/O controller 23 may receive the read signal RD to generate the input control signal DINEN having a logic “low” level (i.e., a low voltage level) and to generate the first column selection signal group YB 1 < 1 :N> such that any one signal of the first column selection signal group YB 1 < 1 :N> has a logic “high” level (i.e., a high voltage level) according to a logic combination of the internal address signals IADD< 1 :N>.

As illustrated in FIG. 2 , the first switching unit 241 may electrically connect the first local line LIO 1 to one line of the first segment line group SIO 1 < 1 >˜SIO 1 <N>, which is selected by the first column selection signal group YB 1 < 1 :N> including a column selection signal generated to have a logic “high” level and may electrically connect the first complementary local line LIO 1 B to one line of the first complementary segment line group SIO 1 B< 1 >˜SIO 1 B<N>, which corresponds to a complementary line of the selected first segment line.

The second switching unit 242 may electrically disconnect the second local line LIO 2 and the second complementary local line LIO 2 B from the second segment line group SIO 2 < 1 > 18 SIO 2 <N> and the second complementary segment line group SIO 2 B< 1 >˜SIO 2 B<N> because all signals of the second column selection signal group YB 2 < 1 :N> have a logic “low” level.

As shown in FIG. 3 , the first switching element N 21 of the isolator 243 may be turned off in response to the input control signal DINEN having a logic “low” level to electrically disconnect the first local line LIO 1 from the second local line LIO 2 . The second switching element N 22 may be turned off in response to the input control signal DINEN having a logic “low” level to electrically disconnect the first complementary local line LIO 1 B from the second complementary local line LIO 2 B.

As illustrated in FIGS. 2 and 4 , the NMOS transistor N 23 of the first pre-charger 2441 may be turned on in response to the power supply voltage VDD signal to drive the first transmission line TL 1 to have a level which is lower than that of the first local line LIO 1 by a threshold voltage (Vt) of the NMOS transistor N 23 . As shown in FIG. 4 , the NMOS transistor N 24 of the first pre-charger 2441 may be turned on in response to the power supply voltage VDD signal to drive the first complementary transmission line TL 1 B to have a level which is lower than that of the first complementary local line LIO 1 B by a threshold voltage (Vt) of the NMOS transistor N 24 . In such a case, the PMOS transistors P 21 , P 22 and P 23 of the first pre-charger 2441 may be turned off.

As illustrated in FIGS. 2 and 5 , the first S/A 2442 may sense and amplify a voltage difference (ΔV) between the first transmission line TL 1 and the first complementary transmission line TL 1 B to output the amplified data of the signal on the first transmission line TL 1 through the I/O line GIO.

The NMOS transistor N 25 of the second pre-charger 2451 may be turned on in response to the power supply voltage VDD signal to drive the second transmission line TL 2 to have a level which is lower than that of the second local line LIO 2 by a threshold voltage (Vt) of the NMOS transistor N 25 . The NMOS transistor N 26 of the second pre-charger 2451 may be turned on in response to the power supply voltage VDD signal to drive the second complementary transmission line TL 2 B to have a level which is lower than that of the second complementary local line LIO 2 B by a threshold voltage (Vt) of the NMOS transistor N 26 . In such a case, the PMOS transistors P 24 , P 25 and P 26 of the second pre-charger 2451 may be turned off.

The second S/A 2452 does not operate where is no voltage difference (ΔV) between the first transmission line TL 1 and the first complementary transmission line TL 1 B.

As described above, the semiconductor system having the aforementioned configuration may electrically disconnect the first local line LIO 1 from the second local line LIO 2 and may electrically disconnect the first complementary local line LIO 1 B from the second complementary local line LIO 2 B in the read mode. Thus, as shown here, a parasitic capacitance of the selected local lines may be reduced to enhance a data access time of the semiconductor system.

It is important to note that the semiconductor system described above in relation to FIGS. 1-5 is merely one example of a system having a controller and a semiconductor device composed of a command decoder, an address decoder, an input/output controller and a data input/output unit. In alternative embodiments, such as in other semiconductor systems, the selection and/or orientation of the components listed may differ from the embodiments shown in FIGS. 1-5 without departing from the original scope and spirit of the invention.