A display device includes a display area and a terminal area formed outside the display area. The display area has a plurality of scanning lines and a plurality of video signal lines that cross the scanning lines. The terminal area has a first terminal having a semiconductor chip connected thereto, a first line, a second line, and an inspection thin-film transistor. The inspection thin-film transistor has a gate electrode connected to the first line, a source electrode connected to the second line, and a drain electrode. The first terminal is connected to any of the plurality of scanning lines and the plurality of video signal lines.

Description

13 parts

›CLAIM OF PRIORITY

The present application claims priority from Japanese patent application JP2013-22122 filed on Feb. 7, 2013, the content of which is hereby incorporated by reference into this application.

›BACKGROUND

The present invention relates to a display device, for example, to a technology applicable to a lighting inspection circuit to illuminate and inspect a display panel.

In an active matrix type display device, in an area near a cross of each scanning line (hereinafter called a gate line) and each video signal line (called a source line or also a drain line, and hereinafter called a source line), a thin-film transistor (TFT) turned on by a scanning signal from the gate line and a pixel electrode supplied with a picture signal from the source line via the above thin-film transistor are formed to form a pixel. The area to form a plurality of pixels is a display area, around which a peripheral area (frame area) is present. In this peripheral area, semiconductor chips forming a scanning line driving circuit, wiring (terminal wiring) to connect the gate lines and source lines on the display area to the semiconductor chip, etc. are provided.

In recent years, with higher definition of display images to improve recognition of information, the number of pixels is increasing and the number of source lines and gate lines is increasing. With these increases, in addition to the number of inputs and outputs of a semiconductor ship device, the number of terminal lines is also increasing. Therefore, a technology to form a semiconductor chip and many terminal lines on a peripheral area having a limited size is desired.

For example, Japanese Unexamined Patent Application Publication No. 2011-164361 (Patent Document 1) discusses a way to address that request. Patent Document 1 discusses a (small line pitch) technology to make small spaces between terminal lines by bending each terminal line adjacent to a terminal (terminal contact hole) formed on each terminal line. In addition, a technology to form an inspection circuit (hereinafter called a lighting inspection circuit) that carries out a pseudo dynamic lighting inspection in that line pitch, which is a failure detection way for liquid crystal display devices (liquid crystal display panels) is also discussed. After the search of the related technologies on the basis of the result invented by the present inventors, Japanese Unexamined Patent Application Publication No. 2010-102237 and Japanese Unexamined Patent Application Publication No. 2009-237280 have been found.

›SUMMARY

In display devices mounted in personal digital assistants etc., high definition may be required in their size-limited bodies. Accordingly, the portion outside the display area (so-called a frame area), not relating to image displays, may be required to be further small. The area to form a lighting inspection circuit may be required to be further small. On the other hand, thin-film transistors are used as switching elements forming a lighting inspection circuit as discussed in Patent Document 1. To form the thin-film transistors, a predefined area may be required. The other subjects and new features will become clear from the description and accompanying drawings of this specification.

A display device of an embodiment is equipped with transistors for an inspection circuit in the area where a group of terminals connected to terminals of a semiconductor chip that drives signal lines of the display device.

According to the above embodiment, even when a line pitch between terminal lines is small, the area for the transistors for the inspection circuit can be ensured.

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a view to explain a configuration of a display device of an embodiment;

FIG. 2 shows a view to explain the overall configuration of a liquid crystal display device of Example 1;

FIG. 3 is a cross sectional view showing a connection to an IC driver of the liquid crystal display device of Example 1;

FIG. 4 is a view to explain a schematic configuration of a lighting inspection circuit in the liquid crystal display device of Example 1;

FIG. 5 shows a circuit configuration of the lighting inspection circuit in the liquid crystal display device of Example 1;

FIG. 6 is a layout pattern of the lighting inspection circuit in the liquid crystal display device of Example 1;

FIG. 7 is an exploded layout pattern of a portion (a) squared by the thick solid line in FIG. 6 ;

FIG. 8 is a sectional view taken along Line A-A in FIG. 7 ;

FIG. 9 is an exploded layout pattern of a portion (b) squared by the thick solid line in FIG. 6 ;

FIG. 10A is an exploded layout pattern of a portion (c) squared by the thick solid line in FIG. 6 ;

FIG. 10B is an exploded layout pattern of an inspection thin-film transistor portion for in FIG. 10A ;

FIG. 10C is an exploded layout pattern of a contact portion in FIG. 10A ;

FIG. 11 is a sectional view taken along Line B-B in FIG. 10A ;

FIG. 12 is an exploded layout pattern of a portion (d) squared by the thick solid line in FIG. 6 ;

FIG. 13 is an exploded layout pattern of a portion (e) squared by the thick solid line in FIG. 6 ;

FIG. 14 is an exploded layout pattern of a portion (f) squared by the thick solid line in FIG. 6 ;

FIG. 15A is a layout pattern of a lighting inspection circuit in a liquid crystal display device of Modification 1;

FIG. 15B is an exploded layout pattern of the inspection thin-film transistor portion in FIG. 15A ;

FIG. 16 is a sectional view taken along Line C-C in FIG. 15A ;

FIG. 17 is a circuit configuration of a lighting inspection circuit in a liquid crystal display device of Modification 2;

FIG. 18 is a layout pattern of the lighting inspection circuit in the liquid crystal display device of Modification 2;

FIG. 19A is an exploded layout pattern of a portion (a) squared by the thick solid line in FIG. 18 ;

FIG. 19B is an exploded layout pattern of an inspection thin-film transistor portion in FIG. 19A ;

FIG. 20 is a circuit configuration of a lighting inspection circuit in a liquid crystal display device of Example 2;

FIG. 21 is a layout pattern of the lighting inspection circuit in the liquid crystal display device of Example 2;

FIG. 22 is an exploded layout pattern of a portion E squared by the thick solid line in FIG. 21 , and

FIG. 23 is a sectional view taken along line F-F in FIG. 22 .

›DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereafter, embodiment, examples, and modifications are explained using the accompanying figures. In the following explanation, the same components are indicated by the same reference numerals, and their explanation is not repeated.

FIG. 1 explains a structure of a display device of an embodiment. A circuit configuration view of FIG. 1 also shows its layout arrangement. A plurality of inspection transistors TTr respectively having common gate electrodes are disposed on a substrate SUB. The plurality of inspection transistors TTr and lines TGW, T 1 W, T 2 W, and T 3 W are disposed inside a semiconductor chip mounting area DrAR. The lines TGW, T 1 W, T 2 W, and T 3 W are connected to inspection terminals TG, T 1 , T 2 , and T 3 and the plurality of inspection transistors TTr. The plurality of inspection transistors TTr are connected to lines L 1 , L 2 , L 3 , L 4 , L 5 , and L 6 (called lines L), respectively. The lines L extend to a display area. The plurality of inspection transistors TTr are disposed inside an area (output terminal area) OTAR to which a group of output terminals of a semiconductor chip is connected. The plurality of inspection transistors TTr may be disposed inside an area (input terminal area) ITAR to which a group of input terminals of the semiconductor chip is connected. The inspection terminals TG, T 1 , T 2 , and T 3 are disposed outside the semiconductor mounting area DrAR in FIG. 1 , but all or part thereof may be disposed inside the semiconductor mounting area DrAR.

The inspection transistors TTr are turned on and off by signals applied to the inspection terminal TG. When the inspection transistors TTr are in the on state, signals applied to the inspection terminals T 1 , T 2 , and T 3 are transmitted to the lines L. Accordingly, before the semiconductor chip is mounted, lighting inspection is achievable. When the inspection transistors TTr are in the off state, signals on the lines T 1 W, T 2 W, and T 3 W are not transmitted to the lines L.

The inspection transistors TTr are disposed in the area to be connected to the group of terminals of the semiconductor chip. Thus, even when the area of the semiconductor chip is small, the pitch between the terminals of the semiconductor chip is small, or the space between the input terminals and output terminals of the semiconductor chip is small, the inspection circuit containing the inspection transistors TTr and lines TGW, T 1 W, T 2 W, and T 3 W can be disposed inside the semiconductor chip mounting area DrAR.

›Examples8

›Example 1 · 1 of 6

Overall Configuration

Before explanation of a specific configuration (Example) of the embodiment, a configuration of a liquid crystal display device to which this example is applied is explained. In this example, the liquid crystal display device is exampled for explanation, but this example is also applicable to other types of display devices such as an organic electroluminescence display device.

FIG. 2 explains the overall configuration of a liquid crystal display device of Example 1. FIG. 2 shows a liquid crystal display device LCDM used for personal digital assistants such as cellular phones, smart phones, and tablet terminals. In FIG. 2 , a facing substrate 200 is laminated on a TFT substrate 100 in which pixel electrodes, thin-film transistors (TFT), etc. are formed in a matrix. Color filters are formed to the facing substrate 200 correspondingly to the pixel electrodes of the TFT substrate 100 to form color images. A liquid crystal layer is sandwiched between the TFT substrate 100 and facing substrate 200 . Images are formed by controlling light transmittance by use of liquid crystal molecules in each pixel. The display area is formed of the TFT substrate 100 and facing substrate 200 .

A plurality of video signal lines (source lines) extending in the longitudinal direction (direction Y) and a plurality of scanning lines (gate lines) extending in the lateral direction (direction X) are present on the TFT substrate 100 . Pixels are formed on the areas surrounded by the video signal lines and scanning lines. The pixel mainly has a pixel electrode and a thin-film transistor (TFT), which is a switching element. Thus, the display area is formed of many pixels formed in a matrix. On the display area of the TFT substrate 100 , TFTs are formed at first, an inorganic passivation film is formed on the TFTs, and pixel electrodes are formed on the film. An insulating film of, e.g., SiN is used as the inorganic passivation film. Transparent conductive films such as ITO (Indium Tin Oxide) are used as the pixel electrodes. TFT substrate 100 is one example of the substrate SUB in the embodiment. As the TFT substrate 100 , insulating substrates of silica glass, plastic (resin), etc. are used in addition to a glass substrate, for example.

An IC driver 300 to drive the video signal lines and scanning lines is disposed to the portion where the TFT substrate 100 has been exposed from the facing substrate 200 . To supply a power source, signals, etc. from the outside, a flexible wiring substrate 500 is disposed.

FIG. 3 is a sectional view showing the connection to the IC driver of the liquid crystal display device of Example 1. As shown in FIG. 3 , the IC driver 300 is connected to terminals 10 formed to the TFT substrate 100 via an anisotropic conductive film (ACF) 400 . The IC driver 300 is one example of the semiconductor chip in the embodiment. In FIG. 2 , the terminals 10 are formed on the TFT substrate 100 . Each terminal is formed of a wiring metal, a contact hole, a transparent conductive film (ITO), etc., but not shown in FIG. 2 . Bumps 310 to be connected to the terminals 10 are formed to the IC driver 300 , and connected to the terminals 10 formed to the TFT substrate 100 . The connection between the bumps 310 and terminals 10 is made via the anisotropic conductive film 400 . Thus, the direct package of the semiconductor chip to the TFT substrate using the glass substrate etc. is called a COG (Chip On Glass) package. The terminals 10 are also called COG terminals.

The anisotropic conductive film 400 is such that conductive particles 410 are distributed to a resin film. When the IC driver 300 and TFT substrate 100 are pressed to one another, the bumps 310 and terminals 10 are electrically connected to each other via the conductive particles 410 . On the other hand, since the conductive particles 410 are apart from each other in the lateral direction (direction Y) in FIG. 3 , electrical conduction is not produced.

Thus, the liquid crystal display device of this example includes the plurality of scanning lines, the plurality of video signal lines that cross the plurality of scanning lines, the display area to form plurality of pixels, and the group of terminals formed outside the display area. The group of terminals has the plurality of terminals 10 that supply signals to any of the plurality of scanning lines and plurality of video signal lines via the terminal wiring.

FIG. 4 explains a schematic configuration of a lighting inspection circuit in the liquid crystal display device of Example 1. Hereafter, based on FIG. 4 , the configuration of the lighting inspection circuit of this example is explained. However, in the following explanation, the source electrodes of inspection thin-film transistors QDTr are connected to inspection terminals TG 1 , TG 2 , R, G, and B, and the drain electrodes of the inspection thin-film transistors QDTr are connected to source lines SL.

In the liquid crystal display device of this example, a lighting inspection circuit QD is formed to the surface on the liquid crystal side of the TFT substrate 100 and outside a display area AR. The lighting inspection circuit QD of this example includes the plurality of inspection thin-film transistors QDTr respectively having common gate electrodes. The gate electrodes of the inspection thin-film transistors QDTr are connected to the inspection terminals TG 1 and TG 2 via a line TG 1 W. The drain electrodes of the inspection thin-film transistors QDTr are connected to the source lines SL, respectively. The inspection thin-film transistors QDTr are one example of the inspection transistors TTr in the embodiment. The terminals TG 1 and TG 2 are one example of the terminal TG in the embodiment. Terminals R, G, and B are one example of the terminals T 1 , T 2 , and T 3 in the embodiment. The lines TG 1 W, DRW, DGW, and DBW are one example of the lines TGW, T 1 W, T 2 W, and T 3 W in the embodiment. The source lines SL are one example of the lines L in the embodiment.

›Example 1 · 2 of 6

On the other hand, the source electrode of the inspection thin-film transistor QDTr whose drain electrode is connected to the source line SL of a thin-film transistor of a pixel of R (red) is connected to the inspection terminal R via the line DRW. The source electrode of the inspection thin-film transistor QDTr whose drain electrode is connected to the source line SL of a thin-film transistor of a pixel of G (green) is connected to the inspection terminal G via the line DGW. The source electrode of the inspection thin-film transistor QDTr whose drain electrode is connected to the source line SL of a thin-film transistor of a pixel of B (blue) is connected to the inspection terminal B via the line DBW.

As shown in FIG. 4 , in the liquid crystal display device of this example, three inspection thin-film transistors QDTr connected to the inspection terminals R, G, and B form a group QDTrG of inspection thin-film transistors, which is sequentially disposed repeatedly on the formation area for the lighting inspection circuit QD. Terminals VGL are connected to the flexible wiring substrate 500 , and supply a fixed potential to the terminals TG 1 and TG 2 after the end of lighting inspection to enable the turn-off of the inspection thin-film transistors QDTr. Only the portion where the inspection thin-film transistors QDTr are connected to the source lines SL is shown in FIG. 4 , but the similar thin-film transistors, wiring, inspection terminals, etc. are also provided for gate lines.

FIG. 5 is a circuit configuration view of the lighting inspection circuit in the liquid crystal display device of Example 1. The circuit configuration view of FIG. 5 also shows its layout arrangement. The lines TG 1 , DRW, DGW, and DBW extend in the direction X, and source lines SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , and SL 6 extend in the direction Y. Terminals SLT 1 , SLT 2 , SLT 3 , SLT 4 , SLT 5 , and SLT 6 correspond to the terminals 10 shown in FIG. 3 in four-step staggered arrangement. That is, the terminals SLT 1 , SLT 2 , SLT 3 , SLT 4 , SLT 5 , and SLT 6 are offset by every four in the direction Y. The inspection thin-film transistors QDTr are disposed below the terminals SLT 1 , SLT 2 , SLT 3 , SLT 4 , SLT 5 , and SLT 6 , respectively.

A metal layer M 1 that forms the gate electrodes of the inspection thin-film transistors QDTr are used for the lines TG 1 , DRW, DGW, and DBW that extend in the direction X. The metal layer M 1 is used also for the source lines SL 1 , SL 3 , and SL 5 . On the other hand, a metal layer M 2 that forms the source electrodes and drain electrodes of the inspection thin-film transistors QDTr is used for the lines TG 1 , DRW, DGW, and DBW that extend in the direction Y. The metal layer M 2 is used also for the source lines SL 2 , SL 4 , and SL 6 . The metal layer M 1 and metal layer M 2 , which are formed in different layers, can be disposed proximate to one another. The black dots shown in FIG. 5 show contacts to connect the metal layer M 1 and metal layer M 2 to one another, contacts to connect the metal layer M 2 and terminals 10 (terminals SLT 2 , SLT 4 , and SLT 6 ) to each other, or contacts to connect the metal layer M 1 , metal layer M 2 , and terminals 10 (terminals SLT 1 , SLT 3 , SLT 5 ) to each other. In FIG. 5 , the output terminal area OTAR to which the output terminal group of the IC driver 300 (semiconductor chip) is connected is from the left ends of the terminals SLT 1 and SLT 5 to the right end of the terminal SLT 4 . The output terminal area OTAR extends in the direction X wider than illustrated.

FIG. 6 is a layout pattern of the lighting inspection circuit in the liquid crystal display device of Example 1. FIG. 6 shows the layout pattern of the lighting inspection circuit between the portion where one end CLE of the semiconductor chip of the IC driver 300 is located and the portion where the other end CRE of the semiconductor chip is located. From the bottom of FIG. 6 , an input terminal area ITAR to which the group of input terminals of the semiconductor chip is connected, a wiring area WAR, an output terminal area (inspection transistor area) OTAR to which the group of output terminals of the semiconductor chip is connected are located in this order. In FIG. 6 , one layout pattern including twelve terminals, twelve inspection thin-film transistors and lines therewith, and contacts is repeated.

FIG. 7 shows an exploded layout pattern of a portion (a) squared by the thick solid line in FIG. 6 . The lines TGW, DRW, DGW, and DBW formed of the metal layer M 1 extend in the direction X. The lines DRW 1 , DGW 1 , DBW 1 , DRW 2 , DGW 2 , and DBW 2 formed of the metal layer M 2 extend in the direction Y. The lines DRW, DGW, and DBW formed of the metal layer M 1 are respectively connected to the lines DRW 1 , DGW 1 , DBW 1 , DRW 2 , DGW 2 , and DBW 2 formed of the metal layer M 2 at contact portions CNT. Semiconductor layers PS are disposed to the portions where the metal layer M 2 crosses over the metal layer M 1 to ease the bumps. When the semiconductor layers PS are present, the short circuit is less likely to occur than when only an insulating film GI is provided between the metal layer M 1 and metal layer M 2 .

FIG. 8 is a sectional view taken along Line A-A in FIG. 7 . The lines TGW, DRW, DGW, and DBW are formed of the metal layer M 1 on the TFT substrate 100 . The metal layer M 2 is formed on the metal layer M 1 via the insulating film GI. The line DRW formed by the metal layer M 1 is connected to the line DRW formed of the metal layer M 2 at the contact portion CNT. On the lines TGW, DBW, and DGW formed of the metal layer M 1 , the semiconductor layers PS are formed between the insulating film GI and metal layer M 2 .

FIG. 9 shows an exploded layout pattern of a portion (b) squared by the thick solid line in FIG. 6 . The line DBW 1 formed of the metal layer M 2 is connected to the line DBW 1 formed of the metal layer M 1 at the contact portion CNT. This is to pass the line DBW 1 through the narrow space between the line DGW 1 and line DRW 1 that are formed of the metal layer M 2 .

›Example 1 · 3 of 6

FIG. 10A shows an exploded layout pattern of a portion (c) squared by the thick solid line in FIG. 6 . FIG. 10B shows an exploded layout pattern of the inspection thin-film transistor portion in FIG. 10A . FIG. 10C shows an exploded layout pattern of the contact portion in FIG. 10A . Below the terminals SLT 1 and SLT 5 formed of the transparent conductive films (ITO), the inspection thin-film transistors QDTr 1 and QDTr 5 are disposed, respectively. The gate electrode of the inspection thin-film transistor QDTr 1 located b the terminal SLT 1 is formed continuously with a metal film of the same layer as a line TGW 1 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 1 is formed continuously with a metal film of the same layer as a line DRW 1 formed of the metal layer M 2 . The drain electrode of the inspection thin-film transistor QDTr 1 is formed of a metal film of the same layer as the line DRW 1 . Below the terminal SLT 1 , a line DRSL 1 that connects the drain electrode of the inspection thin-film transistor QDTr 1 and the source line SL 1 to one another is disposed. The line DRSL 1 is connected to the source line SL 1 formed of the metal layer M 1 and the terminal SLT 1 at a contact portion CNT 1 . The width (length in the direction X) of the line DRSL 1 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 1 , and narrower than that of the terminal SLT 1 .

The gate electrode of the inspection thin-film transistor QDTr 5 located below the terminal SLT 5 is formed continuously with a metal film of the same layer as the line TGW 2 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 5 is formed continuously with a metal film of the same layer as a line DGW 2 formed of the metal layer M 2 . The drain electrode of the inspection thin-film transistor QDTr 5 is formed of a metal film of the same layer as the line DGW 2 . Below the terminal SLT 5 , a line DRSL 5 that connects the drain electrode of the inspection thin-film transistor QDTr 5 and the source line SL 5 to one another is disposed. The line DRSL 5 is connected to the source line SL 5 formed of the metal layer M 1 and the terminal SLT 5 at a contact portion CNT 5 . The width (length in the direction X) of the line DRSL 5 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 5 , and narrower than the terminal SLT 5 . The width (length in the direction X) of the line DGW 2 located below the terminal SLT 5 is wider than that of the source electrode of the inspection thin-film transistor QDTr 5 , and narrower than that of the terminal SLT 5 .

FIG. 11 shows a sectional view taken along Line B-B in FIG. 10A . A gate electrode GT 1 (line TGW 1 ) of the inspection thin-film transistor QDTr 1 and the source line SL 1 are formed of the metal layer M 1 on the TFT substrate 100 . The semiconductor layer PS is formed on the gate electrode GT 1 via the insulating film GI. A source electrode ST 1 and drain electrode DT 1 are formed on the semiconductor layer PS. The source electrode ST 1 and line DRW are integrally formed of the metal layer M 2 . The drain electrode DT 1 and line DRSL 1 are integrally formed of the metal layer M 2 . The line DRSL 1 and source line SL 1 are connected to one another at the contact portion CNT 1 . The terminal SLT 1 is formed on the source electrode ST 1 , drain electrode DT 1 , and line DRSL 1 via a passivation film (insulating film) PV. The line DRSL 1 and terminal SLT 1 are connected to one another at the contact portion CNT 1 .

FIG. 12 shows an exploded layout pattern of a portion (d) squared by the thick solid line in FIG. 6 . Below the terminals SLT 2 and SLT 6 formed of the transparent conductive films (ITO), inspection thin-film transistors QDTr 2 and QDTr 6 are disposed, respectively. The gate electrode of the inspection thin-film transistor QDTr 2 located below the terminal SLT 2 is formed continuously with a metal film of the same layer as the line TGW 1 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 2 is formed continuously with a metal film of the same layer as the line DGW 1 formed of the metal layer M 2 . The drain electrode of the inspection thin-film transistor QDTr 2 is formed of a metal film of the same layer as the line DGW 1 . Below the terminal SLT 2 , a line DRSL 2 that connects the drain electrode of the inspection thin-film transistor QDTr 2 and the source line SL 2 to one another is disposed. The line DRSL 2 is connected to the terminal SLT 2 at a contact portion CNT 2 . The width (length in the direction of X) of the line DRSL 2 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 2 , and narrower than that of the terminal SLT 2 .

The gate electrode of the inspection thin-film transistor QDTr 6 located below the terminal SLT 6 is formed continuously with a metal film of the same layer as a line TGW 2 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 6 is formed continuously with a metal film of the same layer as the line DBW 2 formed of the metal layer M 2 . The drain electrode of the inspection thin-film transistor QDTr 6 is formed of a metal fim of the same layer as the line DBW 2 . Below the terminal SLT 6 , a line DRSL 6 that connects the drain electrode of the inspection thin-film transistor QDTr 6 and the source line SL 6 to one another is disposed. The line DRSL 6 is connected to the terminal SLT 6 at a contact portion CNT 6 . The width (length in the direction X) of the line DRSL 6 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 6 , and narrower than that of the terminal SLT 6 . The width (length in the direction X) of the line DBW 2 located below the terminal SLT 6 is generally the same as that of the source electrode of the inspection thin-film transistor QDTr 6 . This is to pass the line TGW 2 below the terminal SLT 6 . Accordingly, the inspection thin-film transistor QDTr 6 is disposed not near the left end of but near the center of the terminal SLT 6 . Part of the line DBW 2 and part of the source line SL 5 pass below the terminal SLT 6 . Therefore, the contact portion CNT 6 is disposed leftward from the right end of the terminal SLT 6 .

›Example 1 · 4 of 6

FIG. 13 shows an exploded layout pattern of a portion (e) squared by the thick solid line in FIG. 6 . Below the terminal SLT 3 and a terminal SLT 7 that are formed of the transparent conductive films (ITO), inspection thin-film transistors QDTr 3 and QDTr 7 are disposed, respectively. The gate electrode of the inspection thin-film transistor QDTr 3 located below the terminal SLT 3 is formed continuously with a metal film of the same layer as the line TGW 1 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 3 is formed continuously with a metal film of the same layer as the line DBW 1 formed of the metal layer M 2 . The line DBW 1 formed of the metal layer M 1 is connected to the line DBW 1 formed of the metal layer M 2 at a contact portion CNT 3 S. The drain electrode of the inspection thin-film transistor QDTr 3 is formed of a metal film of the same layer as the line DBW 1 formed of the metal layer M 2 . Below the terminal SLT 3 , a line DRSL 3 that connects the drain electrode of the inspection thin-film transistor QDTr 3 and the source line SL 3 to one another is disposed. The line DRSL 3 is connected to the source line SL 3 and terminal SLT 3 at a contact portion CNT 3 . The width (length in the direction X) of the line DRSL 3 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 3 , and narrower than that of the terminal SLT 3 .

The gate electrode of the inspection thin-film transistor QDTr 7 located below the terminal SLT 7 is formed continuously with a metal film of the same layer as the line TGW 2 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 7 is formed continuously with a metal film of the same layer as a line DRW 3 formed of the metal layer M 2 . A line DRW 3 formed of the metal layer M 1 is connected to the line DRW 3 formed of the metal layer M 2 at the contact portion CNT 3 S. The drain electrode of the inspection thin-film transistor QDTr 7 is formed of a metal film of the same layer as the line DRW 3 formed of the metal layer M 2 . Below the terminal SLT 7 , a line DRSL 7 that connects the drain electrode of the inspection thin-film transistor QDTr 7 and the source line SL 7 to one another is disposed. The line DRSL 7 is connected to the source line SL 7 and terminal SLT 7 at a contact portion CNT 7 . The width (length in the direction X) of the line DRSL 7 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 7 , and narrower than the terminal SLT 7 . The width (length in the direction X) of the line DRW 3 located below the terminal SLT 7 is wider than that of the source electrode of the inspection thin-film transistor QDTr 7 , and narrower than that of the terminal SLT 7 . Since part of the line TGW 2 and part of the source line SL 7 are disposed below the terminal SLT 7 , there is a place where the width of the line DRW 3 is narrow. The line DRW 3 formed of the metal layer M 1 is connected to the DRW 3 formed of the metal layer M 2 at a contact portion CNT 7 S. The contact portion CNT 7 S is disposed below the terminal SL 7 . Accordingly, the inspection thin-film transistor QDTr 7 is disposed not near the left end of but near the center terminal SLT 7 . The contact portion CNT 7 is disposed leftward from the right end of the terminal SLT 7 .

FIG. 14 is an exploded layout pattern of a portion (f) squared by the thick solid line in FIG. 6 . Below the terminal SLT 4 and a terminal SLT 8 that are formed of the transparent conductive films (ITO), the inspection thin-film transistor QDTr 4 and an inspection thin-film transistor QDTr 8 are disposed, respectively. The gate electrode of the inspection thin-film transistor QDTr 4 located below the terminal SLT 4 is formed continuously with a metal film of the same layer as the line TGW 1 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 4 is formed continuously with a metal film of the same layer as the line DRW 2 formed of the metal layer M 2 . The drain electrode of the inspection thin-film transistor QDTr 4 is formed of a metal film of the same layer as the line DRW 2 formed of the metal layer M 2 . Below the terminal SLT 4 , a line DRSL 4 that connects the drain electrode of the the inspection thin-film transistor QDTr 4 and the source line SL 4 to one another is disposed. The line DRSL 4 is connected to the source line SL 4 and terminal SLT 4 at a contact portion CNT 4 . The width (length in the direction X) of the line DRSL 4 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 4 , and narrower than that of the terminal SLT 4 .

The gate electrode of the inspection thin-film transistor QDTr 8 located below the terminal SLT 8 is formed continuously with a metal film of the same layer as the line TGW 2 formed of the metal layer M 1 . The source electrode of the inspection thin-film transistor QDTr 8 is formed continuously with a metal film of the same layer as the line DGW 3 formed of the metal layer M 2 . The drain electrode of the inspection thin-film transistor QDTr 8 is formed of a metal film of the same layer as the line DGW 3 formed of the metal layer M 2 . Below the terminal SLT 8 , a line DRSL 8 that connects the drain electrode of the inspection thin-film transistor QDTr 8 and a source line SL 8 to one another is disposed. The line DRSL 8 is connected to the source line SL 8 and terminal SLT 8 at a contact portion CNT 8 . The width (length in the direction X) of the line DRSL 8 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 8 , and narrower than the terminal SLT 8 . The width (length in the direction X) of the line DGW 3 located below the terminal SLT 8 is wider than that of the source electrode of the inspection thin-film transistor QDTr 8 , and narrower than that of a terminal SLT 8 . Since part of the line TGW 2 is disposed below the terminal SLT 8 , there is a place where the width of the line DGW 3 is narrow. Accordingly, the inspection thin-film transistor QDTr 8 is disposed not near the left end of but near the center terminal SLT 8 . The contact portion CNT 8 is disposed leftward from the right end of the terminal SLT 8 .

›Example 1 · 5 of 6

When the terminal pitch is about 9 micrometers, the terminal width is about 18 micrometers, and the line width is about 4 micrometers, the terminals (for example, the terminals SLT 1 , SLT 2 ) corresponding to the adjacent source lines overlap in the direction X. Therefore, the terminals are offset from one another in the direction Y. To pass the lines also between the adjacent terminals (for example, the terminals SLT 1 , SLT 5 ) in the direction X, the space by three terminals is provided therebetween. That is, the terminals are arranged in four-step staggered manner. Therefore, the width (direction Y) of the output terminal area is large, and the space (direction Y) between the input terminal area and the output terminal area is narrow. However, as in this example, by providing the transistors of the inspection circuit below the terminals, compactness is achieved even when the transistor size is unchanged in the same equivalent circuit as Patent Document 1. It becomes possible to dispose the inspection circuit toward the output terminal area from the end of the output terminal area side of the input terminal area.

To dispose the transistors, the contact areas with the terminals (ITO) are made small, and the widths of the lines connected to the drain electrodes and the widths of the adjacent lines are expanded partially so that the metal films may be disposed below the terminals (ITO). Accordingly, the impression of ACF electric conduction particles can be monitored and the management of the number of electric conduction particles is possible.

A first modification (Modification 1) of the display device of Example 1 is explained. In this modification, only the sizes of the transparent conductive films (ITO) that form the terminals are different from those of the display device of Example 1. FIG. 15A shows a layout showing the modification of the display device of Example 1. This is an exploded layout pattern of the portion (c) squared by the thick solid line in FIG. 6 of Example 1. That is, FIG. 15A corresponds to FIG. 10A of Example 1. FIG. 15B shows an exploded layout pattern of the inspection thin-film transistor portion in FIG. 15A .

Below terminals SLT 11 and SLT 51 formed of the transparent conductive films (ITO), the inspection thin-film transistors QDTr 1 and QDTr 5 are not disposed. In Example 1, the transparent conductive films that form the terminals SLT 1 and SLT 5 extend to Line D-D of FIG. 15 . On the other hand, in this modification, the transparent conductive films that form the terminals SLT 11 and SLT 51 extend only short of the inspection thin-film transistors QDTr 1 and QDTr 5 , respectively.

FIG. 16 is a sectional view taken along Line C-C in FIG. 15A . Except that the terminal SLT 11 does not extend onto the inspection thin-film transistor QDTr 1 , FIG. 16 is the same as FIG. 11 of Example 1. Since the inspection thin-film transistors are not disposed below the terminals, the short circuit of each bump potential and inspection thin-film transistor is preventable even when the ACF electric conduction particles crack the transparent conductive films (ITO) that form the terminals at the time of strong compression of the IC driver.

A second modification (Modification 2) of the display device of Example 1 is explained. This modification is different from the display device of Example 1 in arrangement of the inspection thin-film transistors QDTr. That is, in Example 1, the inspection thin-film transistors QDTr are disposed below the terminals. On the other hand, in Modification 2, the inspection thin-film transistors QDTr are shifted to the sides of the terminals. FIG. 17 shows a circuit configuration of a lighting inspection circuit in the liquid crystal display device of Modification 2. The circuit configuration of FIG. 17 also shows its layout arrangement. In comparison to FIG. 5 of Example 1, only arrangement of the inspection thin-film transistors QDTr is different. That is, the inspection thin-film transistors QDTr are shifted to the sides of the terminals (in the direction X).

FIG. 18 shows a layout pattern of the lighting inspection circuit in the liquid crystal display device of Modification 2. The input terminal area ITAR to which the group of input terminals of the semiconductor chip is connected and the wiring area WAR are the same as FIG. 6 of Example 1. The layout pattern of the output terminal area (inspection transistor area) OTAR to which the output terminal group of the semiconductor chip is connected is different from Example 1. In FIG. 18 , one layout pattern including twelve terminals, twelve inspection thin-film transistors and lines therewith, and contacts is repeated.

FIG. 19A shows an exploded layout pattern of a portion (c) squared by the thick solid line in FIG. 18 . FIG. 19B shows an exploded layout pattern of a portion of the inspection thin-film transistor in FIG. 19A . The inspection thin-film transistors QDTr 1 and QDTr 5 are disposed to the positions shifted to the sides of the terminals SLT 1 and SLT 5 (in the direction X) formed of the transparent conductive films (ITO), respectively. That is, the inspection thin-film transistor QDTr 1 is disposed between the terminal SLT 1 and terminal SLT 5 . The lines DGW 1 , DBW 1 , DRW 2 , etc. adjacent thereto are also shifted in the direction X. Therefore, part of the lines DGW 1 , DBW 1 , and DRW 2 are disposed below the terminal SLT 5 . Part of the line DRSL 1 that connects the drain electrode of the inspection thin-film transistor QDTr 1 and source line SL 1 to one another is shifted from the terminal SLT 1 in the direction X. The line DRSL 1 is connected to the source line SL 1 formed of the metal layer M 1 and the terminal SLT 1 at the contact portion CNT 1 . The width (length in the direction X) of the wiring located below the terminal SLT 1 is wider than that of the wiring located outside the terminal SLT 1 , and narrower than that of the terminal SLT 1 .

Below the terminal SLT 5 , the line DRSL 5 that connects the drain electrode of the inspection thin-film transistor QDTr 5 and the source line SL 5 to one another is disposed. The line DRSL 5 is connected to the source line SL 5 formed of the metal layer M 1 and the terminal SLT 5 at the contact portion CNT 5 . The width (length in the direction X) of the line DRSL 5 is wider than that of the drain electrode of the inspection thin-film transistor QDTr 5 , and narrower than the terminal SLT 5 . The width (length in the direction X) of the line DRW 2 located below the terminal SLT 5 is wider than that thereof located outside the terminal SLT 5 , and narrower than that of the terminal SLT 5 .

›Example 1 · 6 of 6

Since the inspection thin-film transistors are not disposed below the terminals, even when the ACF electric conduction particles crack the transparent conductive films (ITO) that form the terminals at the strong compression of the IC driver, the short circuit of each bump potential and inspection thin-film transistor is preventable.

›Example 2 · 1 of 2

FIG. 20 shows a circuit configuration of a lighting inspection circuit in a liquid crystal display device of Example 2. The circuit configuration view of FIG. 20 also shows its layout arrangement. In Example 2, unlike in Example 1, the inspection thin-film transistors QDTr are not disposed to the output terminal area OTAR, but are disposed leftward from the end of the input terminal area ITAR side of the output terminal area OTAR (negative direction in the direction Y). The line TG 1 extends in the direction X as in Example 1, but unlike Example 1, is disposed to the side of the input terminal area ITAR.

Unlike in Example 1, the lines DRW, DGW, and DBW extend by every two in the direction X. The source lines SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , and SL 6 extend in the direction Y as in Example 1. The terminals SLT 1 , SLT 2 , SLT 3 , SLT 4 , SLT 5 , and SLT 6 are in the four-step staggered arrangement as in Example 1.

The metal layer M 1 that forms the gate electrodes of the inspection thin-film transistors QDTr are used for the line TG 1 that extends in the direction X and direction Y and the lines DRW, DGW, and DBW that extend in the direction X. The metal layer M 1 is used for the source lines SL 1 , SL 3 , and SL 5 as in Example 1. On the other hand, the metal layer M 2 that forms the source electrodes and drain electrodes of the inspection thin-film transistors QDTr are used for the lines DRW, DGW, and DBW that extend in the direction X. The metal layer M 2 is used for the source lines SL 2 , SL 4 , and SL 6 as in Example 1. The metal layer M 1 and metal layer M 2 are formed in different layers respectively, and can be thus disposed proximate to each other. The black dots shown in FIG. 20 show contacts that connect the metal layer M 1 and metal layer M 2 as in FIG. 5 of Example 1. In the terminal SLT 1 , the metal layer M 2 connected to the drain electrode of the inspection thin-film transistor QDTr in the same layer and the source line SL 1 formed of the metal layer M 1 are connected to one another. In the terminals SLT 2 , SLT 4 , and SLT 6 , the lines DSL 2 , DSL 4 , and DSL 6 formed of the metal layer M 1 are connected to the source lines SL 2 , SL 4 and SL 6 formed of the metal layer M 2 , respectively. In the terminals SLT 3 and SLT 5 , the lines DSL 3 and DSL 5 formed of the metal layer M 1 are connected to the source lines SL 3 and SL 5 . In FIG. 20 , the area OTAR to which the output terminal group of the IC driver 300 (semiconductor chip) is connected is from the left ends of the terminals SLT 1 and SLT 5 to the right end of the terminal SLOT as in Example 1. The area OTAR extends in the direction X wider than illustrated.

FIG. 21 shows a layout pattern of the lighting inspection circuit in the liquid crystal display device of Example 2. FIG. 21 shows the layout pattern of the lighting inspection circuit between the portion in which one end CLE of the semiconductor chip of the IC driver 300 is located and the portion in which the other end CRE of the semiconductor chip is located. Sequentially from the left of FIG. 21 , the input terminal area ITAR to which the input terminal group of the semiconductor chip is connected, the wiring area WAR, and the output terminal area ITAR to which the output terminal group of the semiconductor chip is connected are disposed. The input terminal area ITAR and wiring area WAR overlap with one another. Part of the inspection transistors is disposed to the input terminal area ITAR. In FIG. 21 , one layout pattern including twelve terminals, twelve inspection thin-film transistors and lines therewith, and contacts is repeated.

Since the terminal pitch is narrow as in Example 1, five inspection thin-film transistors QDTr are aligned in the direction Y in Example 2. However, the inspection thin-film transistors QDTr 5 , QDTr 6 and the lines TG 1 and DBW are disposed to the input terminal area ITAR. Below the terminals (input terminals) of the input terminal area ITAR, the wiring (input wiring) to connect to the terminals connected to the flexible wiring substrate 500 is disposed. When the input terminals use the same configuration as usual, a third-layer wiring other than the metal layers M 1 and M 2 is provided as input wiring. On the other hand, the connection area (contact area) for the input wiring and the input terminals is made small (the contact area is formed near the end CLE of the semiconductor chip), the inspection thin-film transistors QDTr 5 , QDTr 6 , and the line TG 1 is able to be disposed below the input terminals.

FIG. 22 shows an exploded layout pattern of a portion E squared by the thick solid line in FIG. 21 . The line DRW formed of the metal layer M 2 extends on the semiconductor layer PS in the direction X. The line DRSL 1 formed of the metal layer M 2 and connected to the drain electrode DT 1 of the inspection thin-film transistor QDTr extends in the direction Y. The semiconductor layer PS also extends in the direction X. The inspection thin-film transistor QDTr 1 is formed of the gate electrode GT 1 connected continuously with the line TGW 1 formed of the metal layer M 1 in the same layer, the source electrode ST 1 connected continuously with the line DRW formed of the metal layer M 2 in the same layer, and the drain electrode DT 1 connected continuously with wiring DRSL 1 formed of the metal layer M 2 in the same layer. The line DSL 6 and DSL 2 formed of the metal layer M 1 extend in the direction Y in both sides of the inspection thin-film transistor QDTr 1 .

FIG. 23 shows a sectional view taken along Line F-F in FIG. 22 . The gate electrode GT 1 (line TGW 1 ) of the inspection thin-film transistor QDTr 1 is formed of the metal layer M 1 on the TFT substrate 100 . The semiconductor layer PS is formed on the gate electrode GT 1 via the insulating film GI. The source electrode ST 1 and drain electrode DT 1 are formed on the semiconductor layer PS. The drain electrode DT 1 and line DSL 1 are integrally formed of the metal layer M 2 . The passivation film (insulating film) PV is formed on the source electrode ST 1 , drain electrode DT 1 , and line DSL 1 .

›Example 2 · 2 of 2

As in this example, by providing part of the transistors of the inspection circuit below the input terminals, compactness is achievable even with the transistor having an unchanged size in the same equivalent circuit as Patent Document 1. Therefore, the inspection circuit is able to be disposed toward the input terminal area from the end of the input terminal area side of the output terminal area.

As mentioned above, although the invention made by the present inventors has been specifically explained on the basis of the examples, the present invention is not limited to the examples and it is clear that various modifications are possible.

Claims as granted

5 claims

Classifications

5 codes

IPC · International Patent Classification

Section G — Physics

G02F1/1368
G02F1/1345
G02F1/13

Section H — Electricity

H10D30/01
H10D30/67

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