Method of driving a display panel and display device performing the same

This application claims priority from and the benefit of Korean Patent Application No. 10-2013-0087807 filed on Jul. 25, 2013, which is hereby incorporated by reference for all purposes as if fully set forth herein.

The described technology generally relates to a method of driving a display panel and a display device for performing the method, and more particularly, to a method of driving a display panel capable of improving the display quality thereof.

Description of the Related Technology

Generally, liquid crystal displays (LCDs) are relatively thin, light weight and have low power consumption, and thus LCDs are used in monitors, laptop computers and cellular phones, etc. LCDs generally include an LCD panel displaying images using the light transmittance of a liquid crystal layer, a backlight assembly disposed under the LCD panel and providing light to the LCD panel and a driving circuit driving the LCD panel.

The liquid display panel can include an array substrate which has a gate line, a data line, a thin film transistor and a pixel electrode. The liquid crystal display panel can also include an opposing substrate which has a common electrode and a liquid crystal layer interposed between the array substrate and the opposing substrate. The driving circuit typically includes a gate driver which drives the gate line and a data driver which drives the data line.

One inventive aspect is a method of driving a display panel capable of substantially preventing the degradation of a transistor.

Another aspect is a display device performing the method of driving the display panel.

Another aspect is a method of driving a display panel including a plurality of pixels, each of the pixels comprising a first transistor connected to a first gate line and a pixel electrode and a second transistor connected to a second gate line and the pixel electrode. The method includes alternately providing the first gate line with a gate signal and a reverse bias signal and alternately providing the second gate line with the gate signal when the first gate line is provided with the reverse bias signal and the reverse bias signal when the first gate line is provided with the gate signal.

One of the first and second transistors may transfer a data signal to the pixel electrode in response to the gate signal, and the other of the first and second transistors may be annealed by the reverse bias signal.

The gate signal may include an ON voltage and an OFF voltage, and the reverse bias signal may be different from the OFF voltage.

The gate signal may include an ON voltage and an OFF voltage, and the reverse bias signal may be substantially equal to the OFF voltage.

Another aspect is a method of driving a display panel including a plurality of pixels, each of the pixels comprising a first transistor connected to a first gate line and a pixel electrode and a second transistor connected to a second gate line and the pixel electrode. The method includes providing the first gate line with a gate signal to transfer a data signal to the pixel electrode through the first transistor during a first predetermined period and providing the second gate line with a reverse bias signal to anneal the second transistor during the first predetermined period.

The method may further include providing the first gate line with the reverse bias signal to anneal the first transistor during a second predetermined period and providing the second gate line with the gate signal to transfer the data signal to the pixel electrode through the second transistor during the second predetermined period.

The gate signal may include an ON voltage and a first OFF voltage and the reverse bias signal has a second OFF voltage different from the first OFF voltage.

The first OFF voltage may be a maximum voltage from a range of allowable voltages capable of turning off the first and second transistors and the second OFF voltage may be a minimum voltage from the range of the allowable voltages.

The gate signal may include an ON voltage and an OFF voltage and the reverse bias signal may be substantially equal to the OFF voltage.

The first predetermined period may be about one hour.

Another aspect is a display device including a display panel which comprises a plurality of pixels, each of the pixels comprising a first transistor connected to a first gate line and a pixel electrode and a second transistor connected to a second gate line and the pixel electrode, a first gate driver which is connected to the first gate line and alternately provides the first gate line with a gate signal and a reverse bias signal and a second gate driver which is connected to the second gate line and alternately providing the second gate line with the gate signal when the first gate line is provided with the reverse bias signal and the reverse bias signal when the first gate line is provided with the gate signal.

The first gate driver may provide the first gate line with the gate signal to turn on the first transistor during a first predetermined period, and the second gate driver may provide the second gate line with the gate signal to anneal the second transistor during the first predetermined period.

The first gate driver may provide the first gate line with the reverse bias signal to anneal the first transistor during a second predetermined period and the second gate driver may provide the second gate line with the gate signal to turn on the second transistor during the second predetermined period.

The first predetermined period may be substantially equal to the second predetermined period.

Each of the first and second predetermined periods may be about one hour.

The gate signal may include an ON voltage and a first OFF voltage and the reverse bias signal may have a second OFF voltage different from the first OFF voltage.

The first OFF voltage may be a maximum voltage from a range of allowable voltages capable of turning off the first and second transistors and the second OFF voltage may be a minimum voltage from the range of the allowable voltages.

The gate signal may include an ON voltage and an OFF voltage and the reverse bias signal may be substantially equal to the OFF voltage.

The gate signal may be sequentially applied to a plurality of gate lines, and the reverse bias signal may be concurrently applied to a plurality of gate lines.

The first and second transistors may be connected to the same data line.

According to at least one embodiment, the odd-numbered gate lines alternately receive the gate signal and the reverse bias signal, and the even-numbered gate lines alternately receives the reverse bias signal and the gate signal out of phase with the odd-numbered gate lines. Therefore, the first transistor which is connected to one of the odd-numbered gate lines and the second transistor which is connected to one of the even-numbered gate lines are alternately annealed by the reverse bias signal so that the first and second transistors may be substantially prevented from being degraded when driven for extended periods. Therefore, the charging ratio of the liquid crystal capacitor may be improved so that the display quality may be improved.

The above and other features and advantages of the described technology will become more apparent by describing in detailed exemplary embodiments thereof with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating a display device according to an exemplary embodiment.

FIG. 2 is a conceptual diagram illustrating a pixel of the display device shown in FIG. 1 .

FIG. 3 is a conceptual diagram illustrating a pixel of a display device according to an exemplary embodiment.

FIG. 4 is a waveform diagram illustrating a method of driving a display device according to an exemplary embodiment.

FIG. 5 is a waveform diagram illustrating a method of driving a display according to an exemplary embodiment.

FIGS. 6A to 6D are conceptual diagrams illustrating a method of improving blackening according to an exemplary embodiment.

The thin film transistors which drive the pixel electrodes can degrade due to continuous driving over an extended period so that the threshold voltage of the thin film transistors shift in a positive direction. By shifting the threshold voltage, the turn-on current of the thin film transistors can decrease so that the charging ratio of the LCD panel can also decrease. Therefore, blackening can occur in an image displayed on a display device due to the decrease in charging ratio.

Throughout this specification and the claims that follow, when it is described that an element is “connected” to another element, the element may be “directly connected” to the other element or connected to the other element through a third element. The term “connected” as used herein respectively includes the term “electrically connected.”

Hereinafter, the described technology will be explained in detail with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating a display device according to an exemplary embodiment.

Referring to FIG. 1 , the display device may include a timing control part (or timing controller) 100 , a data driving part (or data driver) 200 , a first gate driving part (or first gate driver) 310 , a second gate driving part (or second gate driver) 320 and a display panel 400 .

The timing control part 100 generates a data control signal DCS and a gate control signal GCS using a synchronization signal SS to drive the data driving part 200 and the first and second gate driving parts 310 and 320 . The timing control part 100 corrects image data using a compensation algorithm to provide the data driving part 200 with correction data DD.

The timing control part 100 alternately drives the first and second gate driving parts 310 and 320 in a scanning mode and an annealing mode during predetermined periods. The annealing mode means a non-operating mode where one of driving transistors (TR 1 , TR 2 ) is turned off or otherwise inactive.

The data driving part 200 converts the correction data DD, which is digital data, into a data voltage using a reference gamma voltage and outputs the data voltage to the display panel 400 .

The first gate driving part 310 is alternately operated in the scanning mode which sequentially outputs a plurality of gate signals and in the annealing mode which concurrently outputs a plurality of reverse bias signals, based on the gate control signal GCS received from the timing control part 100 . The gate signal includes an ON voltage and an OFF voltage. The gate signal includes a pulse which has the ON voltage and is repeated in increments of a frame period.

According to some embodiments, the reverse bias signal is a direct current. The OFF voltage of the gate signal can be the maximum voltage of an allowable voltage range and the reverse bias signal can be the minimum voltage of the allowable voltage range. The transistor driving the pixel of the display panel turns off in the allowable voltage range and the allowable voltage range may be predetermined based on an off-leakage current and a kickback voltage of the driving transistor.

The first gate driving part 310 is electrically connected to odd-numbered gate lines in the display panel 400 and is not connected to the even-numbered gate lines. Thus, the first gate driving part 310 drives the odd-numbered gate lines.

The second gate driving part 320 is electrically connected to the even-numbered gate lines and is not connected to the odd-numbered gate lines. Thus, the second gate driving part 320 drives the even-numbered gate lines.

The second gate driving part 320 is driven in an operation mode out of phase with the operation mode of the first gate driving part 310 based on the gate control signal GCS received from the timing control part 100 . For example, when the first gate driving part 310 is operated in the scanning mode which sequentially outputs the gate signals, the second gate driving part 320 is operated in the annealing mode which concurrently outputs the reverse bias signals. Further, when the first gate driving part 310 is operated in the annealing mode, the second gate driving part 320 is operated in the scanning mode.

The display panel 400 may include a plurality of data lines DL, a plurality of gate lines GL 1 and GL 2 and a plurality of pixels P. The data lines DL extend in a first direction 1 and are arranged in a second direction D2 crossing the first direction D1. The gate lines GL 1 and GL 2 extend in the second direction D2 and are arranged in the first direction D1. The pixels P are arranged in a substantially matrix form and each of the pixels P may includes a first transistor TR 1 , a second transistor TR 2 , a liquid crystal capacitor CLC and a storage capacitor CST.

The first transistor TR 1 is connected to a data line DL, an odd-numbered gate line GL 1 and the liquid crystal capacitor CLC. The second transistor TR 2 is connected to the data line DL, an even-numbered gate line GL 2 and the liquid crystal capacitor CLC. The storage capacitor CST is connected to the liquid crystal capacitor CLC. The first gate line GL 1 is connected to the first gate driving part 310 and is not connected to the second gate driving part 320 . The second gate line GL 2 is connected to the second gate driving part 320 and is not connected to the first gate driving part 310 .

According to an embodiment, when the first transistor TR 1 receives a gate signal through the odd-numbered gate line GL 1 , the second transistor TR 2 receives the reverse bias signal through the even-numbered gate line GL 2 . Additionally, when the first transistor TR 1 receives the reverse bias signal through the odd-numbered gate line GL 1 , the second transistor TR 2 receives a gate signal through the even-numbered gate line GL 2 .

When the first transistor TR 1 drives the liquid crystal capacitor CLC, the second transistor TR 2 is in an inactive state in which the second transistor TR 2 is annealed by the reverse bias signal. Similarly, when the second transistor TR 2 drives the liquid crystal capacitor CLC, the first transistor TR 1 is in an inactive state in which the first transistor TR 1 is annealed by the reverse bias signal.

According to the FIG. 1 embodiment, the first and second transistors TR 1 and TR 2 are alternately in the annealing mode so that the first and second transistors TR 1 and TR 2 may be substantially prevented from being degraded by being driven for an extended period of time. Thus, degradation of display quality, for example, blackening, may be substantially prevented. Blackening may occur when the charging rate of the liquid crystal capacitor CLC is reduced.

FIG. 2 is a conceptual diagram illustrating a pixel of the display device as shown in FIG. 1 .

Referring to FIG. 2 , the display panel 400 includes a pixel having a substantially rectangular shape having a longer side and a shorter side. For example, the display panel 400 includes a first pixel P 1 and a second pixel P 2 with the longer side being arranged in a longitudinal direction D1.

The first pixel P 1 includes a first transistor TR 1 , a second transistor TR 2 and a first pixel electrode PE 1 . The first transistor TR 1 is electrically connected to a data line DL, a first gate line GL 1 and the first pixel electrode PE 1 . The first gate line GL 1 is connected to the first gate driving part 310 and is not connected to the second gate driving part 320 .

The second transistor TR 2 is electrically connected to the data line DL, a second gate line GL 2 , and the first pixel electrode PE. The second gate line GL 2 is connected to the second gate driving part 320 and is not connected to the first gate driving part 310 . The second gate line GL 2 is disposed adjacent to the first gate line GL 1 .

The second pixel P 2 includes a third transistor TR 3 , a fourth transistor TR 4 and a second pixel electrode PE 2 .

The third transistor TR 3 is electrically connected to the data line DL, a third gate line GL 3 and the second pixel electrode PE 2 . The third gate line GL 3 is connected to the first gate driving part 310 and is not to the second gate driving part 320 . The third gate line GL 3 is spaced apart from the second gate line GL 2 so that the second pixel electrode PE 2 is disposed between the second and third gate lines GL 2 and GL 3 .

The fourth transistor TR 4 is electrically connected to the data line DL, a fourth gate line GL 4 and the second pixel electrode PE 2 . The fourth gate line GL 4 is connected to the second gate driving part 320 and is not connected to the first gate driving part 310 . The fourth gate line GL 4 is disposed adjacent to the third gate line GL 3 .

The first and second gate driving parts 310 and 320 are alternately operated in the scanning mode and the annealing mode so that one of two transistors in each pixel turns-on to drive the pixel electrode and the other of two transistors is annealed by the reverse bias signal.

FIG. 3 is a conceptual diagram illustrating a pixel of a display device according to another exemplary embodiment.

Referring to FIG. 3 , the display panel 400 includes a pixel having a substantially rectangular shape having a longer side and a shorter side. For example, the display panel 400 includes a first pixel P 1 and a second pixel P 2 which are arranged in a direction D1.

The first pixel P 1 includes a first transistor TR 1 , a second transistor TR 2 and a first pixel electrode PE 1 . The first and second transistors TR 1 and TR 2 are disposed adjacent to the shorter sides of the first pixel P 1 .

The first transistor TR 1 is electrically connected to a data line DL, a first gate line GL 1 and the first pixel electrode PE 1 . The first gate line GL 1 is connected to the first gate driving part 310 and is not connected to the second gate driving part 320 .

The second transistor TR 2 is electrically connected to the data line DL, a second gate line GL 2 and the first pixel electrode PE 1 . The second gate line GL 2 is connected to the second gate driving part 320 and is not connected to the first gate driving part 310 .

The second gate line GL 2 is spaced apart from the first gate line GL 1 so that the first pixel electrode PE 1 is disposed between the first and second gate lines GL 1 and GL 2 . Thus, the first pixel electrode PE 1 is disposed between the first and second gate lines GL 1 and GL 2 .

The second pixel P 2 includes a third transistor TR 3 , a fourth transistor TR 4 and a second pixel electrode PE 2 . The third transistor TR 3 is electrically connected to the data line DL, a third gate line GL 3 and the second pixel electrode PE 2 .

The third gate line GL 3 is connected to the first gate driving part 310 , and is not connected to the second gate driving part 320 . The third gate line GL 3 is disposed adjacent to the second gate line GL 2 .

The fourth transistor TR 4 is electrically connected to the data line DL, a fourth gate line GL 4 and the second pixel electrode PE 2 . The fourth gate line GL 4 is connected to the second gate driving part 320 and is not connected to the first gate driving part 310 .

The fourth gate line GL 4 is spaced apart from the third gate line GL 3 so that the second pixel electrode PE 2 is disposed between the third and fourth gate lines GL 3 and GL 4 . Thus, the second pixel electrode PE 2 is disposed between the third and fourth gate lines GL 3 and GL 4 .

Although not shown in the figures, the structure of the pixels may have various different designs and is not limited to the illustrated structures.

FIG. 4 is a waveform diagram illustrating a method of driving a display device according to an exemplary embodiment.

Referring to FIGS. 1 and 4 , the timing control part 100 respectively provides the first and second gate driving parts 310 and 320 with a gate control signal GCS including a first driving control signal GC 1 and a second driving control signal GC 2 .

According to some embodiments, when the first and second driving control signals GC 1 and GC 2 have a high level, the first and second gate driving parts 310 and 320 are operated in the scanning mode. When the first and second driving control signals GC 1 and GC 2 have a low level, the first and second gate driving parts 310 and 320 are operated in the annealing mode.

Each of the first and second driving control signals GC 1 and GC 2 alternates between the high level and the low level for each predetermined period T. The first and second driving control signals GC 1 and GC 2 respectively have opposite levels to each other during each predetermined period T. The length of the predetermined period T may be predetermined according to the design requirements. The predetermined period T may be preset as an hour. For example, the predetermined period T may be about one hour.

During a first predetermined period 1T, the first gate driving part 310 is operated in the scanning mode in response to the first driving control signal GC 1 having the high level and the second gate driving part 320 is operated in the annealing mode in response to the second driving control signal GC 2 having the low level.

When in the scanning mode, the first gate driving part 310 sequentially provides odd-numbered gate lines with gate signals G 1 , G 3 , . . . , Gn−1. When in the annealing mode, the second gate driving part 320 concurrently provides even-numbered gate lines with reverse bias signals G 2 , G 4 , . . . , Gn.

As shown in FIG. 4 , each of the odd gate signals G 1 , G 3 , . . , Gn−1 has a pulse having an ON voltage Von and a first OFF voltage Voff1 which are alternately repeated for each frame period. The reverse bias signal is a direct current signal which has a second OFF voltage Voff2 less than the first OFF voltage Voff1. The first OFF voltage Voff1 is the maximum voltage of an allowable voltage range and the second OFF voltage Voff2 is the minimum voltage of the allowable voltage range. The first or second transistor turns off in the allowable voltage range and the allowable voltage range may be preset based on an off-leakage current and a kickback voltage of the driving transistors.

Therefore, during a first predetermined period 1T, the first transistor TR 1 of the pixel P receives the gate signal and turns on in response to the gate signal. Thus, the liquid crystal capacitor CLC charges to a data signal transferred through the turned-on first transistor TR 1 . In addition, the second transistor TR 2 of the pixel P receives the reverse bias signal. Thus, the second transistor TR 2 is annealed by the reverse bias signal.

Then, during a second predetermined period 2T, the first gate driving part 310 is operated in the annealing mode in response to the first driving control signal GC 1 having the low level and the second gate driving part 320 is operated in the scanning mode in response to the second driving control signal GC 2 having the high level.

When in the annealing mode, the first gate driving part 310 concurrently provides the odd-numbered gate lines with the reverse bias signals G 1 , G 3 , . . . , Gn−1 having the second OFF voltage Voff2. When in the scanning mode, the second gate driving part 320 sequentially provides the even-numbered gate lines with the gate signals G 2 , G 4 , . . . , Gn having the ON voltage Von and the first OFF voltage Voff1.

Therefore, during the second predetermined period 2T, the second transistor TR 2 of the pixel P receives the gate signal and turns on in response to the gate signal. Thus, the liquid crystal capacitor CLC charges to a data signal transferred through the turned-on second transistor TR 2 . In addition, the first transistor TR 1 of the pixel P receives the reverse bias signal. Thus, the first transistor TR 1 is annealed by the reverse bias signal.

As described above, during the first predetermined period 1T, the second transistor TR 2 electrically connected to the second gate driving part 320 is annealed by the reverse bias signal and thus, the second transistor TR 2 is in an inactive state. During the second predetermined period 2T, the first transistor TR 1 electrically connected to the first gate driving part 310 is annealed by the reverse bias signal and thus, the first transistor TR 1 is in the inactive state. Therefore, the first and second transistors TR 1 and TR 2 of the pixel P which drive the liquid crystal capacitor CLC, are alternately annealed during the predetermined periods and thus, the first and second transistors TR 1 and TR 2 may be substantially prevented from being degraded when being driven for extended periods.

FIG. 5 is a waveform diagram illustrating a method of driving a display according to an exemplary embodiment.

Referring to FIGS. 1 and 5 , the timing control part 100 respectively provides the first and second gate driving parts 310 and 320 with a first driving control signal GC 1 and a second driving control signal GC 2 that are included in a gate control signal GCS.

During a first predetermined period 1T, the first gate driving part 310 is operated in the scanning mode in response to the first driving control signal GC 1 having a high level and the second gate driving part 320 is operated in the annealing mode in response to the second driving control signal GC 2 having a low level.

When in the scanning mode, the first gate driving part 310 sequentially provides odd-numbered gate lines with gate signals G 1 , G 3 , . . . , Gn−1 having the alternately repeated ON and OFF voltages by for each frame period. When in the annealing mode, the second gate driving part 320 concurrently provides even-numbered gate lines with reverse bias signals G 2 , G 4 , . . . , Gn which have a predetermined voltage.

According to the exemplary embodiment, the reverse bias signal may have the OFF voltage Voff.

Therefore, during a first predetermined period 1T, the first transistor TR 1 of the pixel P receives the gate signal and turns on in response to the gate signal. Thus, the liquid crystal capacitor CLC charges to a data signal transferred through the turned-on first transistor TR 1 . In addition, the second transistor TR 2 of the pixel P receives the reverse bias signal. Thus, the second transistor TR 2 is annealed by the reverse bias signal.

Then, during a second predetermined period 2T, the first gate driving part 310 is operated in the annealing mode in response to the first driving control signal GC 1 having the low level and the second gate driving part 320 is operated in the scanning mode in response to the second driving control signal GC 2 having the high level.

When in the annealing mode, the first gate driving part 310 concurrently provides the odd-numbered gate lines with the reverse bias signals G 1 , G 3 , . . . , Gn−1 having the OFF voltage Voff. When in the scanning mode, the second gate driving part 320 sequentially provides the even-numbered gate lines with the gate signals G 2 , G 4 , . . . , Gn having the ON voltage Von and the OFF voltage Voff.

Therefore, during the second predetermined period 2T, the second transistor TR 2 of the pixel P receives the gate signal and turns on in response to the gate signal. Thus, the liquid crystal capacitor CLC charges to a data signal transferred through the turned-on second transistor TR 2 . In addition, the first transistor TR 1 of the pixel P receives the reverse bias signal. Thus, the first transistor TR 1 is annealed by the reverse bias signal.

Therefore, the first and second transistors TR 1 and TR 2 of the pixel P which drive the liquid crystal capacitor CLC are alternately annealed during the predetermined period, and thus, the first and second transistors TR 1 and TR 2 may be substantially prevented from being degraded by being driven for extended periods.

FIGS. 6A to 6D are conceptual diagrams illustrating a method of reducing blackening according to an exemplary embodiment.

Referring to FIG. 6A , the display panel 500 includes an area A in which blackening occurs due to driving the display panel 500 for an extended period. According to the exemplary embodiment, a reverse bias signal of about −20 V was applied to a display panel 500 for about 100 hours so that negative annealing was performed. Thereafter, the area A was observed to include blackening.

Referring to FIG. 6B , when a 255-grayscale image was displayed on the display panel 500 , the luminance of the area A before the negative annealing was about 161.5 nit and the luminance of the area A after the negative annealing was about 333.7 nit. Thus, the luminance of the area A was increased by about 172.2 nit (106.7%) so that the blackening of the area A was reduced.

Referring to FIG. 6C , when a 238-grayscale image was displayed in the display panel 500 , the luminance of the area A before the negative annealing was about 18.68 nit and the luminance of the area A after the negative annealing was about 60.7 nit. Thus, the luminance of the area A was increased by about 42 nit (225%) so that the blackening of the area A was reduced.

Referring to FIG. 6D , the gamma curve of the display panel 500 before the negative annealing was an about 3.13-gamma curve Cint. The gamma curve of the display panel 500 after the negative annealing was an about 2.47-gamma curve Canl. The gamma curve after the negative annealing is adjacent to an about 2.2-gamma curve Cref of a reference gamma curve.

As described above, the degradation of a transistor which is driven for an extended period of time may be improved through the negative annealing.

According to at least one of the disclosed embodiments, the odd-numbered gate lines alternately receive the gate signal and the reverse bias signal, and the even-numbered gate lines alternately receive the reverse bias signal and the gate signal out of phase with the odd-numbered gate lines. Therefore, the first transistor which is connected to an odd-numbered gate line and the second transistor which is connected to an even-numbered gate line are alternately annealed by the reverse bias signal so that the first and second transistors may be substantially prevented from being degraded when being driven for extended periods. Therefore, the charging ratio of the liquid crystal capacitor may be improved so that the display quality may be improved.

The foregoing is illustrative of the described technology and is not to be construed as limiting thereof. Although a few exemplary embodiments of the described technology have been described, those skilled in the art will readily appreciate that many modifications are possible to the exemplary embodiments without materially departing from the novel teachings and advantages of the described technology. Accordingly, all such modifications are intended to be included within the scope of the described technology as defined in the appended claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the described technology and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims. The described technology is defined by the following claims, with equivalents of the claims to be included therein.