Bidirectional semiconductor device for protection against electrostatic discharges

This application claims priority to French Patent Application No. 1350323, which was filed Jan. 15, 2013 and is incorporated herein by reference.

The invention relates to integrated circuits and, in particular embodiments, to bidirectional semiconductor devices for protection against electrostatic discharges (ESD). For example, the devices can be produced in a CMOS technology in a bulk silicon substrate and can be usable without a triggering circuit.

In the field of microelectronics, an electrostatic discharge can occur throughout the lifetime of an integrated circuit, and can constitute a genuine problem for the reliability of this integrated circuit, as well as a major cause of malfunction.

An electrostatic discharge is generally manifested by a current peak of varying amplitude and varying duration.

An ESD protection device should therefore remove this current peak. Furthermore, this current peak induces a thermal stress in the protection device.

One conventional ESD protection element is a triac. The production of such a protective element in a technology of the bulk-substrate type readily makes it possible to dissipate the heat generated by the ESD pulse through the contacts and the bulk substrate in which the protective element is produced.

Furthermore, ESD protection devices of the triac type are generally associated with triggering circuits, for example, MOS transistors whose gate and substrate are connected to ground (GGNMOS transistors), connected to their gate. This presence of a triggering circuit makes it possible to reduce the triggering voltage of the protection device. The triggering voltage of such a device is the voltage applied between the two terminals of the device, beyond which the device starts to conduct. However, the presence of a triggering circuit has a negative effect on the surface size of the assembly.

In particular, when the protection device is produced in a given CMOS technology on a bulk substrate, moreover, the absence of a triggering circuit leads to high triggering voltages, which may be greater than the breakdown voltage of a transistor produced in the technology and capable of being protected by this protection device.

According to one embodiment, an ESD protection device is provided. In particular, a triac produced in a given CMOS technology is usable without a triggering circuit and has a lower breakdown voltage than a conventional triac. In particular, the breakdown voltage is less than the breakdown voltage of a transistor produced in the technology and capable of being protected by this protection device.

Another parameter of an ESD protection device, in particular a triac, is its holding voltage, that is, the minimum voltage at which the device remains conductive after having been triggered.

According to another embodiment, an ESD protection device is provided. In particular a triac can be produced in a given CMOS technology, whether on a bulk substrate or on silicon-on-insulator (SOI), and be usable without a triggering circuit and have a higher holding voltage than a conventional triac.

According to one aspect, an integrated circuit produced on a bulk semiconductor substrate in a given CMOS technology comprises a protective semiconductor device intended to protect a component produced in the CMOS technology and having at least one MOS transistor against electrostatic discharges.

The protection device has a doublet of floating-gate thyristors connected in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1 and each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of the at least one transistor of the component.

The two thyristors mounted head-to-tail make it possible to have a bidirectional protection device.

Furthermore, the common gate makes it possible to have a compact device.

It is also not necessary to have an external triggering element for triggering the device. This is because simple application of a potential to the anode or cathode of a thyristor leads to a thermodynamic imbalance of the device and distribution of the potential over the entire device, which biases the junctions allowing injection of minority or majority carriers, depending on the case, which sets the bipolar transistors of the device in conduction with, when the product of the current gains of the two transistors of each thyristor is greater than 1, amplification, sustained by positive feedback, of the base currents of the transistors, until operation of these transistors in saturated mode is obtained. Effective triggering of the device is then obtained, allowing it to efficiently fulfill its ESD protection function.

Furthermore, the Inventors have observed that adjustment of this dimension, measured perpendicularly to the spacing direction of the two electrodes and which may be referred to as the electrode width, makes it possible to adjust the triggering voltage of the thyristor in question. Increasing this electrode width also leads to a decrease in the triggering voltage of the thyristor.

Generally, in view of the bidirectional nature of the device, it is preferable for each electrode region of the two thyristors to have a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the two thyristors respective intrinsic triggering voltages less than the breakdown voltage of a transistor produced in the CMOS technology.

This being the case, it is possible to adjust the triggering voltages of the two thyristors identically or differently so as to have identical or different triggering voltages depending on the sign of the ESD pulse.

More particularly, according to an embodiment making it possible to have different triggering voltages for the two thyristors, the dimension of the electrode regions of one of the thyristors is different from the dimension of the electrode regions of the other thyristor.

By way of example, when the protection device is produced in a 28 nm or 32 nm CMOS technology, and the transistor to be protected is a transistor with a thick gate oxide, typically having a thickness of more than 3 nanometers, for example 6.5 nanometers, the dimension is advantageously greater than 6 microns.

This is because the breakdown voltage of such a transistor lies between 6 and 8 V. With a dimension of 6 microns, the triggering voltage of the protection device lies between 4 and 5 V.

According to one embodiment, the dimension of the common gate region, measured parallel to the spacing direction, is greater than the minimum dimension defined by the design rules of the technology.

This is because the Inventors have furthermore observed that adjustment of this common gate region dimension, which may be referred to as the gate length, makes it possible to adjust the holding voltage of the device. Increasing this gate length also leads to an increase in the holding voltage of the device.

This being the case, this characteristic may also be considered independently of the one relating to the electrode width.

In other words, according to another aspect an integrated circuit is provided, produced in a given CMOS technology, comprising a protective semiconductor device for protection against electrostatic discharges, having a doublet of floating-gate transistors connected in parallel and head-to-tail, each thyristor having a pair of electrode regions, the product of the current gains of the two transistors of each thyristor being greater than 1, and the two thyristors respectively having two separate gates and a common semiconductor gate region having a dimension, measured parallel to the spacing direction of the electrodes of each pair, greater than the minimum dimension defined by the design rules of the technology. These design rules are generally referred to by the person skilled in the art by the acronym DRM (“Design Rules Manual”).

Increasing the electrode widths of a triac in order to reduce its bidirectional triggering voltages is valid when the triac is produced in a bulk-substrate technology or in an SOI technology. This being the case, in an SOI technology, the intrinsic triggering voltage (without a triggering circuit) of a triac is already very low. Lastly, in an SOI technology, and more particularly in an FDSOI technology, there may be up to six orders of magnitude difference between the concentration of dopants in an N+ region of a triac and that of an intrinsic P type region, which then leads to an extremely large depletion zone of the associated PN junction and therefore to almost absence of an energy step, which leads to triggering voltages that can be very low.

This is the reason why the increase of the electrode widths applies more particularly to a triac produced in a bulk-substrate technology, in which it intrinsically has a high triggering voltage.

On the other hand, increasing the gate length in order to increase the holding voltage is advantageous irrespective of the type of technology (bulk or SOI, for example).

Further to the increase of its length, the common gate region may also comprise at least one zone selected from the group formed by a zone having the same conductivity type as the common gate region but doped more heavily than the common gate region, a zone having the opposite conductivity type to the common gate region and optionally doped more heavily than the common gate region, an electrically insulating region.

This contributes to increasing the holding voltage.

More particularly, the common gate region may comprise three zones selected from the group, with two identical zones surrounding a different zone. For example, there may be a sequence of zones P+-N+-P+, or P+-insulator-P+.

Other advantages and characteristics of the invention will become apparent on studying the detailed description of entirely nonlimiting embodiments and the appended drawings, in which FIGS. 1 to 14 schematically illustrate various embodiments of a device according to the invention.

Generally, in order to protect a component against electrostatic discharges (ESD), this component is connected to the two terminals of a protection device.

This component, produced in CMOS technology, generally comprises one or more MOS transistors.

When the component is not in operation, it may be subjected to an electrostatic discharge typically manifested by a very short current pulse.

It is then expedient for this current pulse to flow through the protection device and not through the component to be protected.

The device is consequently intended to absorb this current pulse and avoid overvoltages at the terminals of the component.

Such an ESD protection device is, for example, a triac.

Although the invention applies to any type of triac structure, a first example of a structure will now be described with reference more particularly to FIGS. 1 to 7 .

More precisely, in this example, the triac TRC with a single common gate GH comprises ( FIG. 1 ) a first semiconductor section CS 1 having a first conductivity type, for example the N conductivity type, forming the common gate GH of the two thyristors of the triac. Two second semiconductor sections CS 20 and CS 21 have a second conductivity type, the opposite of the first, here the P conductivity type. These two sections CS 20 and CS 21 are arranged on either side of the first section CS 1 .

Furthermore, an N+ doped zone and a P+ doped zone, mutually in contact, both contact the section CS 20 and form the electrode A 1 of the triac TRC.

Likewise, a P+ doped zone and an N+ doped zone, mutually in contact, both contact the second section CS 21 and form the second electrode A 2 of the triac TRC.

The electrodes A 1 and A 2 of the triac then form the two terminals, between which the component to be protected will be connected.

The P+ and N+ zones are insulated from the first section CS 1 by isolation trenches TIS of the shallow trench isolation type (STI).

Likewise, isolation trenches TIS laterally insulate the zones N+ and P+ of the triac TRC externally.

Each pair of mutually opposite zones (N+, P+) separated by the section CS 1 forms, with the underlying P and N layers, a half-triac (thyristor).

Furthermore, a buried semiconductor layer CSC (N-doped and commonly referred to as a “Niso layer”) contacts the first and second sections of the triac TRC. N-doped wells PTS are arranged laterally with respect to the sections CS 20 and CS 21 and contact the buried layer CSC. This buried layer is itself arranged in a P section (not represented for the sake of simplicity).

The triac, which is a double P-N-P-N structure, therefore in this case comprises two fingers DG 1 , DG 2 respectively produced in an integrated fashion within the semiconductor sections mentioned above.

The two thyristors TH 1 and TH 2 are connected head-to-tail, have floating gates and have a common floating semiconductor CS 1 gate N region. Furthermore, the thyristor TH 1 has a floating gate P (section CS 20 ) separate from the floating gate P (section CS 21 ) of the thyristor TH 2 .

In the case in which the anode P+ of the thyristor TH 2 is set at a positive potential relative to ground, a thermodynamic imbalance is then created in the thyristor, which causes distribution of the potential over the entire thyristor, which biases the PN junctions and consequently allows injection of minority carriers (here electrons), which sets the bipolar transistors of the thyristor in conduction.

In the case in which a negative potential relative to ground is applied to the anode of the thyristor TH 2 , and consequently to the cathode of the thyristor TH 1 . There is also distribution of the potential over the entire thyristor TH 1 , which biases the junctions and allows injection of minority carriers (here holes), which sets the bipolar transistors of the thyristor THi 1 in conduction.

More precisely, in either case, in view of the structure with two looped transistors of a thyristor, the injection of carriers at the base of one of the transistors of the thyristor leads, when the product of the current gains (gains β) of the two transistors of the thyristor is greater than 1, to a sustained positive feedback loop being obtained, causing amplification of the base current injected into each of the transistors of the thyristor and leading to operation of the transistors of the thyristor in saturated mode.

W 1 a denotes the electrode width of the thyristor TH 1 (measured perpendicularly to the spacing direction DES of the electrodes) and W 1 b denotes the electrode width of the thyristor TH 2 (measured perpendicularly to the spacing direction DES of the electrodes).

In this example, W 1 a is equal to W 1 b , although these two values may be different in order to make the response of the device non-symmetrical.

The triac TRC is produced here in a 28 nm or 32 nm CMOS bulk-substrate technology, and the transistor or transistors of the component protected by this triac are MOS transistors produced in this technology and having thick gate oxides, typically larger than 3 nanometers.

In such technologies, the breakdown voltage of such a thick gate oxide transistor is of the order of 6 to 8 volts.

Furthermore, the widths W 1 a 0 and W 1 b 0 are conventionally of the order of 3 microns in such technologies, which leads to intrinsic triggering voltages (without a triggering circuit) of the order of 7 volts.

The curve CV 0 ( FIG. 2 ) is a conventional graph of positive current and voltage of a triac having a triggering voltage VDC and a holding voltage VH (the graph would be similar on the negative side).

When W 1 a 0 and W 1 b 0 are increased in order to obtain the values W 1 a and W 1 b , the triggering voltage of the triac is reduced so as to obtain a value VDC 1 lower than VDC (it is assumed here that W 1 a and W 1 b remain equal, leading to identical triggering voltages irrespective of the sign of the ESD pulse).

This makes it possible to reduce the triggering voltage by the order of 1 to a few volts.

By way of indication, in 28 nm and 32 nm CMOS technologies, the widths W 1 a and W 1 b are selected to be greater than or equal to 6 microns. With 6 microns, a decrease in the triggering voltage of the order of 2 volts is obtained, and it then lies between 4 and 5 V.

In FIG. 1 , W 2 m denotes the length of the common gate region GH measured parallel to the spacing direction between the two regions TIS, and Lgm denotes the dimension of the common gate region measured parallel to the spacing direction between the two sections CS 20 and CS 21 .

W 2 m and Lgm are the minimum dimensions dictated by the design rules (DRM) of the technology in question.

Thus, for a 28 nm CMOS technology, W 2 m is equal to 0.129 micron and Lgm is equal to 0.227 micron, and the holding voltage VH is of the order of 1.2 volts.

For a 32 nm CMOS technology, W 2 m is equal to 0.148 micron and Lgm is equal to 0.26 micron, and the holding voltage VH is of the order of 1.2 volts.

As illustrated in FIG. 2 , when W 2 and consequently Lg are increased ( FIG. 3 ), the holding voltage is increased, its value changing from VH to VH 1 .

Thus, for a 28 nm CMOS technology and with a value W 2 equal to 2 microns, a holding voltage VH 1 of the order of 1.7 volts is obtained.

Naturally, if W 1 and W 2 are increased at the same time, the two effects mentioned above are combined.

Whereas the embodiment of FIG. 3 only had a length increase of the common gate region, it is possible to insert into this common gate region at least one zone selected from the group formed by a zone having the same conductivity type as the common gate region but doped more heavily than the common gate region, a zone having the opposite conductivity type to the common gate region and optionally doped more heavily than the common gate region, an electrically insulating region.

The holding voltage of the triac can then be increased further.

Examples of such alternative embodiments are illustrated in FIGS. 4 to 7 .

Thus, in FIG. 4 , the common gate region CS 1 comprises an N+ doped zone Z 1 , that is to say of the same conductivity type as the common gate region but more heavily doped. Such a zone modifies the acceleration field of the carriers in the direction of braking and, by the increase in the concentration of dopants, the recombination of minority carriers is increased, which contributes to increasing the holding voltage.

In FIG. 5 , the common gate region CS 1 comprises a P+ doped zone Z 2 , that is to say of the opposite conductivity type to the common gate region, and here more heavily doped, although the greater nature of the doping is not essential. Such a zone increases the recombination of the minority carriers by increasing the mean free path due to the space charge zone, and therefore contributes to increasing the holding voltage.

In FIG. 6 , the common gate region CS 1 comprises an insulating zone Z 3 , for example of the shallow trench type. Such a zone increases the mean free path of topological nature of the carriers, which increases the recombination of the minority carriers and contributes to increasing the holding voltage.

It is also possible, as illustrated in FIG. 7 , for the common gate region to comprise three zones selected from the group of zones mentioned above, with two identical zones surrounding a different zone. This makes it possible to combine the effects mentioned above.

More precisely, in FIG. 7 there is a sequence of zones Z 2 -Z 3 -Z 2 .

Reference will now be made more particularly to FIG. 8 onwards in order to describe other embodiments of the protection device according to the invention.

In FIG. 8 , the reference DTHi denotes a doublet of two thyristors THi 1 and THi 2 , connected in parallel and mounted head-to-tail so as to form a triac, of which the gates of the two transistors are floating gates.

More precisely, the device comprises a common semiconductor layer SB, here having the N conductivity type. This layer is an N section implanted in a P bulk substrate.

The doublet DTHi of thyristors is formed in and above the semiconductor layer SB.

More precisely, two sections CSi having the P conductivity type are produced in the layer SB, for example by implantation.

These two sections are mutually spaced.

In contact with the two sections CSi 1 and CSi 2 , two first semiconductor zones Zi 11 and Zi 12 are respectively produced by implantation, these two first zones being N+ doped.

Furthermore, a P+ doped second semiconductor zone Zi 21 , also produced by implantation in the layer SB, surrounds the first semiconductor zone Zi 11 and is electrically insulated from this zone Zi 11 by an isolation trench TIS.

Likewise, a second semiconductor zone Zi 22 , also P+ doped, surrounds the first semiconductor zone Zi 12 and is insulated therefrom by an isolation trench TIS.

An electrical connection CNXi 1 , for example a metallization of the first metal level (metal M 1 ) of the integrated circuit, electrically connects the first semiconductor zone Zi 11 and the second semiconductor zone Zi 21 above the layer SB.

Likewise, an electrical connection CNXi 2 (also at the metal level M 1 , for example) connects the first semiconductor zone Zi 12 and the second semiconductor zone Zi 22 .

It can therefore be seen that the doublet DTHi comprises a first thyristor THi 1 of the PNPN type.

More precisely, the anode P of the thyristor THi 1 is formed by the second semiconductor zone Zi 21 and the cathode of this thyristor is formed by the first semiconductor zone Zi 12 .

The thyristor comprises a gate N and a gate P. The gate N is formed by the layer SB whereas the gate P is formed by the section CSi 2 .

The second thyristor THi 2 is also of the PNPN type. Its anode is formed by the second semiconductor zone Zi 22 , and its cathode is formed by the first semiconductor zone Zi 11 . The second thyristor also has a gate N and a gate P. The gate N of the thyristor THi 2 is also formed by the layer SB, and is therefore common with the gate N of the thyristor THi 1 .

The gate P of the thyristor THi 2 is formed by the section CSi 1 , and is separate from the gate P of the thyristor THi 1 .

The gates P of the thyristors and the common gate N are floating gates.

Owing to the electrical connections CNXi 1 and CNXi 2 , the anode of the thyristor THi 1 is electrically connected to the cathode of the thyristor THi 2 , and the anode of the thyristor THi 2 is electrically connected to the cathode of the thyristor THi 1 .

A first terminal BDi 1 of the thyristor doublet DTHi is formed by the anode of the thyristor THi 1 and the cathode of the thyristor THi 2 .

The second terminal BDi 2 of the doublet DTHi is formed by the anode of the thyristor THi 2 and the cathode of the thyristor THi 1 .

The terminals BDi 1 and BDi 2 then form the two terminals between which the component to be protected will be connected.

The operation of the device of FIG. 8 is similar to that of the device of FIG. 1 .

Thus, in the case in which the second terminal BDi 2 , and consequently the anode of the thyristor THi 2 , is set at a positive potential relative to ground, a thermodynamic imbalance is then created in the thyristor, which causes distribution of the potential over the entire thyristor, which biases the PN junctions and consequently allows injection of minority carriers (here electrons), which sets the bipolar transistors of the thyristor in conduction.

In the case in which a negative potential relative to ground is applied to the terminal BDi 2 , and consequently to the cathode of the thyristor THi 1 , there is also distribution of the potential over the entire thyristor THi 1 , which biases the junctions and allows injection of minority carriers (here holes), which sets the bipolar transistors of the thyristor THi 1 in conduction.

More precisely, in either case, in view of the structure with two looped transistors of a thyristor, the injection of carriers at the base of one of the transistors of the thyristor leads, when the product of the current gains (gains β) of the two transistors of the thyristor is greater than 1, to a sustained positive feedback loop being obtained, causing amplification of the base current injected into each of the transistors of the thyristor and leading to operation of the transistors of the thyristor in saturated mode.

The device DIS illustrated in FIG. 9 makes it possible to protect eight nodes of an integrated circuit against ESD pulses.

It is a particularly compact structure of eight doublets of thyristors DTH 1 -DTH 8 arranged in a matrix network, here having three rows and three columns of first semiconductor zones Z 1 k respectively surrounded by their second semiconductor zones Z 2 k , to which they are respectively connected electrically by metallizations.

More precisely, the central first semiconductor zone Z 10 , surrounded by the corresponding second semiconductor zone Z 20 and arranged in contact with the corresponding underlying section, are common to all the thyristors, and the central first semiconductor zone Z 10 electrically connected to the second zone Z 20 forms the first terminal of the device DIS intended to be connected to ground.

The other first semiconductor zones Z 11 -Z 18 , surrounded by their second zones Z 21 -Z 28 and located in the immediate vicinity of the common central second zone Z 20 , respectively form the eight second terminals of the device, and are respectively intended to be connected to the eight nodes to be protected. Eight components respectively connected between the eight nodes and ground can thus be protected.

The device DTHi illustrated in section in FIG. 8 is, for example, the one which in FIG. 9 comprises the zones Z 10 and Z 18 (cathodes of the two thyristors) respectively surrounded by the zones Z 20 and Z 28 (anodes of the two thyristors).

W 1 denotes the electrode width of the thyristors (measured perpendicularly to the spacing direction DES of the electrodes).

The triac TRC is in this case produced in a 28 nm or 32 nm CMOS bulk-substrate technology.

Here again, when W 1 is increased relative to a conventional value, the triggering voltage of the triac is reduced.

In a similar way as explained with reference to FIGS. 1 and 2 , in 28 nm and 32 nm CMOS technology, a value W 1 greater than or equal to 6 microns will be selected, which makes it possible to protect components incorporating thick gate oxide MOS transistors effectively without an external triggering circuit.

In a similar way as described for the structure of FIG. 1 , W 2 m in FIG. 8 denotes the length of the common gate region GH measured parallel to the spacing direction between the two electrodes Zi 21 and Zi 22 of the two thyristors, and Lgm denotes the dimension of the common gate region measured parallel to the spacing direction between the two sections CSi 1 and CSi 2 .

W 2 m and Lgm are the minimum dimensions dictated by the design rules (DRM) of the technology in question.

Thus, for a 28 nm CMOS technology, W 2 m is equal to 0.227 μm and Lgm is equal to 0.325 μm, and the holding voltage VH is of the order of 1.6 V.

For a 32 nm CMOS technology, W 2 m is equal to 0.26 μm and Lgm is equal to 0.372 μm, and the holding voltage VH is of the order of 1.5 V.

In a similar way as described above for the structure of FIG. 3 , when W 2 and consequently Lg are increased ( FIG. 10 ), the holding voltage of the triac is increased.

As in the embodiments illustrated in FIGS. 4 to 7 , it is possible to insert into this common gate region at least one zone selected from the group formed by a zone having the same conductivity type as the common gate region but doped more heavily than the common gate region, a zone having the opposite conductivity type to the common gate region and optionally doped more heavily than the common gate region, an electrically insulating region.

The holding voltage of the triac can then be increased further.

Examples of such alternative embodiments are illustrated in FIGS. 11 to 14 .

Thus, in FIG. 11 , the common gate region comprises an N+ doped zone Z 100 , that is to say of the same conductivity type as the common gate region but more heavily doped. This zone Z 100 surrounds the electrodes Zi 21 and Zi 22 Here again, such a zone Z 100 modifies the acceleration field of the carriers in the direction of braking, which increases the recombination of the minority carriers and contributes to increasing the holding voltage.

In FIG. 12 , the common gate region comprises a P+ doped zone Z 200 , that is to say of the opposite conductivity type to the common gate region, and here more heavily doped, although the greater nature of the doping is not essential. This zone Z 200 surrounds the electrodes Zi 21 and Zi 22 Here again, such a zone increases the recombination of the minority carriers and contributes to increasing the holding voltage.

In FIG. 13 , the common gate region comprises an insulating zone Z 300 , for example of the shallow trench type. This zone Z 300 surrounds the electrodes Zi 21 and Zi 22 Here again, such a zone increases the mean free path of the carriers, which increases the recombination of the minority carriers and contributes to increasing the holding voltage.

It is also possible, as illustrated in FIG. 14 , for the common gate region to comprise three zones selected from the group of zones mentioned above, with two identical zones surrounding a different zone. This makes it possible to combine the effects mentioned above.

More precisely, in FIG. 14 there is a sequence of zones Z 200 -Z 100 -Z 200 .