Clock signal generating circuit and video signal processing circuit using same

1. Technical Field

The present disclosure relates to a clock signal generating circuit and a video signal processing circuit using the clock signal generating circuit.

2. Description of Related Art

A clock signal transmits and processes data in a high speed digital signal processing circuit. When the high speed digital signal processing circuit is a video signal processing circuit for example, the video signal processing circuit modulates video signals based on the clock signal. However, if the clock signal input to the video signal processing circuit has noise, such as phase noise, a quality of the video signals output from the video signal processing circuit is affected.

Therefore, what is needed is a clock signal generating circuit and a video signal processing circuit that can overcome the described limitations.

FIG. 1 is a schematic block diagram of an embodiment of a video signal processing circuit.

FIG. 2 is a circuit diagram of a first embodiment of a clock signal generating circuit of the video signal processing circuit of FIG. 1 .

FIG. 3 is a circuit diagram of a second embodiment of a clock signal generating circuit of the video signal processing circuit of FIG. 1

The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”

Reference will now be made to the drawings to describe embodiments of the present disclosure.

FIG. 1 illustrates one embodiment of a video signal processing circuit 100 . The video signal processing circuit 100 comprises a power source 10 , a video signal modulator 20 , and a clock signal generating circuit 30 . The power source 10 is connected to the video signal modulator 20 and the clock signal generating circuit 30 . The clock signal generating circuit 30 is further connected to the video signal modulator 20 .

The power source 10 supplies voltage to the video signal modulator 20 and the clock signal generating circuit 30 . In one embodiment, the power source 10 is a boost circuit, or a buck circuit.

The clock signal generating circuit 30 comprises a crystal oscillator 31 , a bias circuit 32 , a first capacitor C 1 , a phase compensation circuit 33 , a negative resistance compensation circuit 34 , a high pass filter circuit 35 , and an amplifier 36 . The bias circuit 32 is connected to the power source 10 and the negative resistance compensation circuit 34 , and is further connected to the crystal oscillator 31 via the first capacitor C 1 . The crystal oscillator 31 is further connected to the phase compensation circuit 33 and the negative resistance compensation circuit 34 . The high pass filter circuit 35 is connected between the negative resistance compensation circuit 34 and the amplifier 36 . The amplifier 36 is connected to the video signal modulator 20 .

The crystal oscillator 31 generates a clock signal. The bias circuit 32 receives the voltage from the power source 10 , and outputs a bias voltage to the negative resistance compensation circuit 34 . The phase compensation circuit 33 compensates the phase of the clock signal. The negative resistance compensation circuit 34 compensates negative resistance of the clock signal, to decrease phase noises generated by parasitic components, such as parasitic capacitors and parasitic inductors. The high pass filter circuit 35 filters low frequency noises of the clock signal. The amplifier 36 amplifies the clock signal after the clock signal is compensated by the phase compensation circuit 33 and the negative resistance compensation circuit 34 , and is filtered by the high pass filter circuit 35 , and outputs the amplified clock signal to the video signal modulator 20 .

The video signal modulator 20 receives the clock signal from the clock signal generating circuit 30 , modulates video signals based on the received clock signal, and outputs the modulated video signals to a display 200 . The display 200 displays images based on the modulated video signals.

A first and second embodiments of the clock signal generating circuit 30 are described below. The clock signal generating circuit 30 of the first embodiment is labeled with 30 a , and the clock signal generating circuit 30 of the second embodiment is labeled with 30 b . Correspondingly, the bias circuit 32 of each of the clock signal generating circuits 30 a , 30 b is respectively labeled with 32 a , 32 b . The phase compensation circuit 33 of each of the clock signal generating circuits 30 a , 30 b is respectively labeled with 33 a , 33 b . The negative resistance compensation circuit 34 of each of the clock signal generating circuits 30 a , 30 b is respectively labeled with 34 a , 34 b . The high pass filter circuit 35 of each of the clock signal generating circuits 30 a , 30 b is respectively labeled with 35 a , 35 b.

FIG. 2 is a circuit diagram of a first embodiment of the clock signal generating circuit 30 a . The clock signal generating circuit 30 a further comprises a second capacitor C 2 , a third capacitor C 3 , a fourth capacitor C 4 , a fifth capacitor C 5 , and a sixth capacitor C 6 . The crystal oscillator 31 comprises a first end 331 and a second end 332 . The bias circuit 32 a comprises a first resistor R 1 and a second resistor R 2 . The first resistor R 1 and the second resistor R 2 are connected between the power source 10 and ground in series. A first node N 1 is defined between the first resistor R 1 and the second resistor R 2 . The first node N 1 is connected to the negative resistance compensation circuit 34 a and is further connected to the first end 331 of the crystal oscillator 31 via the first capacitor C 1 .

The phase compensation circuit 33 a comprises a third resistor R 3 , a first inductor L 1 , a seventh capacitor C 7 , and an eighth capacitor C 8 . The third resistor R 3 is connected between the second end 333 and ground. The first inductor L 1 and the eighth capacitor C 8 are connected between the second end 333 and ground in series. A second node N 2 is defined between the first inductor L 1 and the eighth capacitor C 8 . The seventh capacitor C 7 is connected between the second node N 2 and ground. The phase compensation circuit 33 a compensates the phase of the clock signal. The clock signal output by the crystal oscillator 31 reaches a predetermined frequency, such as 27 MHz, even as the clock signal is affected by noises when the crystal oscillator 31 generates the clock signal.

The negative resistance compensation circuit 34 a comprises a first transistor Q 1 and a second transistor Q 2 . In the embodiment, the first and second transistors Q 1 , Q 2 are NPN bipolar transistors. A base of the first transistor Q 1 is connected to the first node N 1 , and is further connected to ground via the second, third, and fourth capacitors C 2 , C 3 , C 4 in sequence. A third node N 3 is defined between the second capacitor C 2 and the third capacitor C 3 . A fourth node N 4 is defined between the third capacitor C 3 and the fourth capacitor C 4 . A collector of the first transistor Q 1 is connected to the power source 10 . An emitter of the first transistor Q 1 is connected to the third node N 3 . A base of the second transistor Q 2 is connected to the third node N 3 . A collector of the second transistor Q 2 is connected to the collector of the first transistor Q 1 . An emitter of the second transistor Q 2 is connected to the base of the first transistor Q 1 . The clock signal generating circuit 30 a further comprises a fourth resistor R 4 . The fourth resistor R 4 is connected to the third capacitor C 3 in parallel. The first transistor Q 1 filters the phase noises. The second transistor Q 2 compensates the clock signal after the clock signal is filter by the first transistor Q 1 .

The high pass filter circuit 35 a is a Π type LC high pass filter. The high pass filter circuit 35 a comprises a second inductor L 2 , a third inductor L 3 , and a ninth capacitor C 9 . The second inductor L 2 is connected between the fourth node N 4 and ground. The ninth capacitor C 9 comprises a first end E 1 and a second end E 2 . The first end E 1 of the ninth capacitor C 9 is connected to the fourth node N 4 , and the second end E 2 of the ninth capacitor C 9 is connected to ground via the third inductor L 3 . The second end E 2 of the ninth capacitor C 9 is further connected to the amplifier 36 via the fifth capacitor C 5 , and is further connected to the power source 10 via the sixth capacitor C 6 .

FIG. 3 is a circuit diagram of a second embodiment of the clock signal generating circuit 30 b . The second embodiment of the clock signal generating circuit 30 b is similar to the first embodiment of the clock signal generating circuit 30 a except that the circuits of a bias circuit 32 b , a phase compensation circuit 33 b , a negative resistance compensation circuit 34 b , and a high pass filter circuit 35 b differs from circuits of the bias circuit 32 a , the phase compensation circuit 33 a , the negative resistance compensation circuit 34 a , and the high pass filter circuit 35 a.

In the embodiment, the bias circuit 32 b is current mirror bias circuit. The bias circuit 32 b comprises a first transistor M 1 , a second transistor M 2 , a first resistor R 11 , and a second resistor R 12 . In the embodiment, the first and second transistors M 1 , M 2 are n-channel transistors. A source electrode of the first transistor M 1 is connected to the power source 10 via the first resistor R 11 . A gate electrode of the first transistor M 1 is connected to the source electrode of the first transistor M 1 and a gate electrode of the second transistor M 2 . Drain electrodes of the first and second transistor M 2 , M 2 are connected to a first node N 1 defined between a first capacitor C 1 and the negative resistance compensation circuit 34 b via the second resistor R 22 . A source electrode of the second transistor M 2 is connected between a first capacitor C 1 and the negative resistance compensation circuit 34 b . The source electrode of the second transistor M 2 outputs a bias voltage to the negative resistance compensation circuit 34 b.

The phase compensation circuit 33 b comprises a third resistor R 33 , a first inductor L 11 , a variable capacitance diode D 1 , a seventh capacitor C 77 , an eighth capacitor C 88 , and a variable voltage source VSS. The third resistor R 33 is connected between a second end 333 of a crystal oscillator 31 and ground. The first inductor L 11 and the seventh capacitor C 77 are connected between the second end 333 of the crystal oscillator 31 and ground in series. A node N 2 is defined between the first inductor L 11 and the seventh capacitor C 77 . An anode of the variable capacitance diode D 1 is connected to the second node N 2 . A cathode of the variable capacitance diode D 1 is connected to ground via the eighth capacitor C 88 , and is further connected to the variable voltage source VSS. A capacitance of the variable capacitance diode D 1 is adjustable via adjusting output voltage of the variable voltage source VSS. Accordingly, a frequency and a phase of the clock signal generated by the crystal oscillator 31 are conveniently adjusted.

The negative resistance compensation circuit 34 b comprises a third transistor M 3 and a fourth transistor M 4 . In the embodiment, the third and fourth transistors M 3 , M 4 are n-channel transistors. A gate electrode of the third transistor M 3 is connected to the first node N 1 . A source electrode of the third transistor M 3 is connected to a third node N 3 . A drain electrode of the third transistor M 3 is connected to the power source 10 . A gate of the fourth transistor M 4 is connected to the third node N 3 . A source electrode of the fourth transistor M 4 is connected to the first node N 1 . A drain electrode of the fourth transistor M 4 is connected to the power source 10 . Operation of the negative resistance compensation circuit 34 b is similar to the operation of the negative resistance compensation circuit 34 a . Accordingly, the operation of the negative resistance compensation circuit 34 b is not repeated here.

The high pass filter circuit 35 b is a T type LC high pass filter. The high pass filter circuit 35 b comprises a second inductor L 22 , a ninth capacitor 99 , and a tenth capacitor C 10 . The ninth capacitor C 99 comprises a first end E 11 and a second end E 22 . The first end E 11 of the ninth capacitor C 99 is connected to a fourth node N 4 defined between a third capacitor C 3 and a fourth capacitor C 4 via the tenth capacitor C 10 . The first end E 11 of the ninth capacitor C 99 is further connected to ground via the second inductor L 22 . The second end E 12 of the ninth capacitor C 99 is connected to the power source 10 via a sixth capacitor C 6 , and is further connected to the amplifier 36 via a fifth capacitor C 5 .

The clock signal generating circuit 30 filters phase noises, low frequency noises, and other noises, and thus outputs the clock signal with little or no noise. Accordingly, a quality of the video signals output from the video signal processing circuit based on the clock signal is improved.

It is believed that the present embodiments and their advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the present disclosure or sacrificing all of its material advantages.