Discharge circuit for power supply unit

Relevant subject matter is disclosed in one co-pending U.S. patent application Ser. No. 14/141,401 having the same titles, which are assigned to the same assignees as this patent application.

1. Technical Field

The present disclosure relates to a discharge circuit.

2. Description of Related Art

During a power-on operation of a computer, a voltage creep may be generated when a system voltage is output later than a stand-by voltage. A resistor may be used to discharge the voltage creep. However, the resistor is still working when the computer is powered on, which wastes energy.

Therefore, there is room for improvement in the art.

Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views.

The FIGURE is a circuit diagram of an embodiment of a discharge circuit.

The disclosure is illustrated by way of example and not by way of limitation in the FIGURE of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”

The FIGURE illustrates an embodiment of a discharge circuit. The discharge circuit comprises a pulse width modulator (PWM) chip U 1 , four capacitors C 1 -C 4 , six resistors R 1 -R 6 , an inductance L 1 , and four transistors Q 1 -Q 4 .

A phase output pin Phase of the PWM chip U 1 is coupled to a first terminal of the inductance L 1 . A gate G of the transistor Q 3 is coupled to a second terminal of the inductance L 1 through the resistor R 3 . A source S of the transistor Q 3 is connected to ground. A drain D of the transistor Q 3 is coupled to a stand-by power terminal 5 VSB through the resistor R 4 , and is also coupled to a gate G of the transistor Q 4 . A source S of the transistor Q 4 is connected to ground. A drain D of the transistor Q 4 is coupled to a first terminal of an inductance L 1 through the resistors R 5 and R 6 connected in parallel.

A voltage pin Vc of the PWM chip U 1 is coupled to the system power terminal Vcc. The enable pin En is used to receive an enable signal Enable. A ground pin GND of the PWM chip U 1 is connected to ground. A high gate output pin Hgate of the PWM chip U 1 is coupled to a gate G of the transistor Q 1 . A drain D of the transistor Q 1 is coupled to a system power terminal VIN. The power system terminal VIN is connected to ground parallel through capacitors C 1 and C 2 . A source S of the transistor Q 1 is coupled to the phase output pin Phase. A low gate output pin Lgate is coupled to a gate G of a transistor Q 2 . A drain D of transistor Q 2 is coupled to the phase output pin Phase. A source S of the transistor Q 2 is connected to ground. A voltage output pin FB of the PWM chip U 1 is connected to ground through a resistor R 2 , and is coupled to the second terminal of the inductance L 1 . The second terminal of the inductance L 1 is further connected to ground through capacitors C 3 and C 4 connected in parallel.

In the embodiment, during a power-on operation, if the system power terminal VCC is not output a system voltage, while the stand-by power terminal 5 VSB outputs a stand-by voltage, the PWM chip U 1 outputs a voltage creep through the phase output pin Phase. When the voltage creep is less than a voltage that makes the transistor Q 3 turn on, the gate G of the transistor Q 4 is coupled to the stand-by power terminal 5 VSB, and the gate G of the transistor Q 3 receives the low-voltage level control signal, and the transistor Q 3 is turned off, and the gate G of the transistor Q 4 is at high-voltage level. Accordingly, the transistor Q 4 is turned on, and the voltage creep is discharged through the resistors R 6 , R 7 and the transistor Q 4 .

When the voltage creep is equal to or greater than the voltage that makes the transistor Q 3 turn on, the transistor Q 3 is turned on. Accordingly, the gate G of the transistor Q 3 is at high-voltage level, and the transistor Q 3 is turned on, and the gate G of the transistor Q 3 is at low-voltage level, such as logic 0 , the transistor Q 4 is turned off. According, the resistors R 6 and R 7 are no longer consume power.

In the embodiment, the transistors Q 1 -Q 4 are n-channel metal oxide field effective transistors (NMOSFET).

While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.