Sensorless current sensing methods for power electronic converters

Example embodiments are related to power conversion circuits and methods for estimating a current flowing through power electronic converters and/or switches used therein.

Conventional low cost current sensing methods deploy open loop current sensors in high power inverter and converter applications. An open loop current sensor is an integrated potted plastic-case assembly of Hall element, silicon-iron magnetic core, electronic circuit and connectors. Such open loop current sensors encounter significant temperature rise due to iron losses in their magnetic core. Therefore, open loop sensors pose constraints in handling the current flowing through the power electronics switches being monitored and/or sensed by them.

In addition, there is a direct proportionality between cost and level of performance of such current sensors. Moreover, assembly, packaging, reliability and thermal issue are also of concern. Volumetric space occupied by current sensors render many surrounding areas, in the power electronic assembly, unusable. Such unused spaces may negatively impact power density (kW/Kg) and/or energy density (kW/liter) of power electronics assemblies with added vulnerabilities in the design such as thermal failure modes in the current sensor that are difficult to detect and remedy in a fast and timely manner.

Some embodiments are directed to methods and apparatuses for estimating a current flowing through power electronic converters and/or switches used in power conversion circuits.

In one example embodiment, an apparatus includes a power electronics switching circuit having a semiconductor switch and a device in communication with the power electronics switching circuit. The device includes a processor configured to estimate a current through the power electronics switching circuit based on a first voltage across the semiconductor switch, a control signal controlling the semiconductor switch and a first voltage-current characteristic of the semiconductor switch.

In one example embodiment, an electrical structure includes a first apparatus including a first power electronics switching circuit having a semiconductor switch and a first device, the first device including a first processor configured to estimate a first portion of a current flowing through the first power electronics switching circuit based on a first voltage across the semiconductor switch of the first power electronics switching circuit, a first control signal controlling the semiconductor switch of the power electronics switching circuit and a first voltage-current characteristic of the semiconductor switch of the power electronics switching circuit. The electrical structure further includes a second apparatus including a second power electronics switching circuit and a second device, the second device including a second processor configured to estimate a second portion of the current flowing through the second power electronics switching circuit based on a second voltage across a semiconductor switch of the second power electronics switching circuit, a second control signal controlling the semiconductor switch of the second power electronics switching circuit and a first voltage-current characteristic of the semiconductor switch of the second power electronics switching circuit. The processor further includes a third processor configured to estimate the current based on the estimated first portion of the current and the estimated second portion of the current.

In one example embodiment, a method includes measuring a first voltage across a semiconductor switch of a first power electronics switching circuit and estimating a current through the power electronics switching circuit based on the measured first voltage, a control signal controlling the semiconductor switch and a first voltage-current characteristic of the semiconductor switch.

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-5B represent non-limiting, example embodiments as described herein.

FIG. 1 depicts an apparatus including a power electronics switching circuit and a device for estimating a current flowing through the power electronics switching circuit, according to an example embodiment;

FIG. 2 illustrates a flowchart of a method of estimating the current flowing through the power electronics switching circuit shown in FIG. 1 , according to an example embodiment;

FIG. 3 depicts another apparatus including a power electronics switching circuit and a device for estimating a current flowing through the power electronics switching circuit, according to an example embodiment;

FIG. 4 illustrates a flowchart of a method of estimating the current flowing through the power electronics switching circuit shown in FIG. 3 , according to an example embodiment;

FIG. 5 depicts an electrical structure with a high-side apparatus and a low-side apparatus and a device in each apparatus for estimating a portion of a current flowing through a power electronics switching circuit included in each apparatus, according to an example embodiment;

FIG. 6 depicts another electrical structure with a high-side apparatus and a low-side apparatus and a device in each apparatus for estimating a portion of a current flowing through a power electronics switching circuit included in each apparatus, according to an example embodiment;

FIGS. 7A-C illustrates converter phase having a HS and LS power electronics switching circuit as well as directions of the phase current for the converter phase, according to an example embodiment;

FIG. 8 illustrates a dual inverter system deployable for on-board power generation and traction systems in hybrid vehicles, employing a plurality of apparatuses described with respect to FIGS. 1-2 , according to an example embodiment; and

FIG. 9 illustrates a permanent magnet generator with a three phase output and an n-phase switch reluctance machine, employing a plurality of apparatuses described with respect to FIGS. 1-2 , according to an example embodiment.

Some example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are illustrated.

Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the claims. Like numbers refer to like elements throughout the description of the figures.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Portions of example embodiments and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operation on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as the term is used here, and as it is used generally, is conceived to be a self-consistent sequence of steps leading to a result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

In the following description, illustrative embodiments will be described with reference to acts and symbolic representations of operations (e.g., in the form of flowcharts) that may be implemented as program modules or functional processes including routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and may be implemented using existing hardware. Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific-integrated-circuits, field programmable gate arrays (FPGAs) computers or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or as is apparent from the discussion, terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Note also that the software implemented aspects of example embodiments are typically encoded on some form of tangible (or recording) storage medium or implemented over some type of transmission medium. The tangible storage medium may be magnetic (e.g., a floppy disk or a hard drive) or optical (e.g., a compact disk read only memory, or “CD ROM”), and may be read only or random access. Similarly, the transmission medium may be twisted wire pairs, coaxial cable, optical fiber, or some other suitable transmission medium known to the art. Example embodiments are not limited by these aspects of any given implementation.

FIG. 1 depicts an apparatus including a power electronics switching circuit and a device for estimating a current flowing through the power electronics switching circuit, according to an example embodiment. The apparatus 100 may include a power electronics switching circuit 102 and a current sensing device 104 (hereinafter referred to as the device 104 ).

The power electronics switching circuit 102 may include a semiconductor switch 106 and a diode 108 . A current I IGBT (or alternatively, I MOSFET ) may be flowing through the power electronics switching circuit 102 , as shown in FIG. 1 , an estimate of which may be determined, as will be explained below. The semiconductor switch 106 may be an Insulated Gate Bi-polar Transistor (IGBT) having a gate 110 , a collector 112 and an emitter 114 . The semiconductor switch 106 may also be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (e.g., nMOS, pMOS, etc.), wherein elements 110 , 112 and 114 may be a gate, a drain and a source, respectively. It will be appreciated that the semiconductor switch 106 is not limited to the above IGBT and FET type transistors but may include any other known or to be developed semiconductor based transistors.

The device 104 may include a first circuit 116 , a digital device 118 , a processor 120 and a memory 122 . The first circuit 116 may include a DC voltage source 116 - 1 , a first resistance element 116 - 2 , a second resistance element 116 - 3 , a diode 116 - 4 and a capacitance element 116 - 5 connected between the first resistance element 116 - 2 and a ground. The digital device 118 may have a built-in analog to digital converter (ADC), which may be a high-speed converter (e.g., conversion time is 100 s of nano-seconds) with a high accuracy (e.g. error less than 0.5%). The digital device 118 may also have input/output ports for receiving signals and/or outputting signals, as will be described below. The memory 122 may be any type of storage device, as described above. The memory 122 may be accessible by the processor 120 . In one example embodiment, the memory 122 may be a separate unit in communication with the device 104 . In one example embodiment, a field programmable gate array (FPGA) may be used instead of the memory 122 . In one example embodiment, the FPGA may be used together with a microprocessor to form a complete system on chip. Accordingly, instead of the processor 120 and the memory 122 , the complete system on chip may be used.

As will be explained in further detail below with reference to FIG. 2 , the first circuit 116 may measure a collector-emitter voltage (V ce ) of the IGBT transistor 106 (or alternatively, a drain-source voltage (V DS ) of the MOSFET transistor). The digital device 118 may digitize the V ce (V DS ), via the built-in ADC. Furthermore, the digital device 118 may be able to read the state (ON or OFF) of gate-emitter voltage (V ge ) of the IGBT transistor (or, alternatively a gate-source voltage (V GS ) of the MOSFET transistor). V ge (or, alternatively V gs ) may be digitized signals read by the digital device 118 directly from a control signal 128 . In one example embodiment, a voltage at the gate of the semiconductor switch 106 may be determined based on the control signal 128 . The control signal 128 may determine the ON/OFF states of the semiconductor switch 106 . For example, when the control signal 128 is high (H), the semiconductor switch 106 is ON and when the control signal 128 is low (L), the semiconductor switch 106 is OFF. H or L may also be represented as ‘1’ or ‘0’, respectively.

In one example embodiment, if the V ge (or, alternatively V gs ) is an analog signal, the digital device 118 may digitize such analog signals via the built-in ADC.

In one example embodiment, the digitized V ge (or, alternatively V gs ) may be known by the inverter and control system 124 , described below). Accordingly, the inverter and control system 124 may communicate the information regarding V ge (or, alternatively V gs ) to the digital device 118 or in the alternative communicate V ge (or, alternatively V gs ) directly to the processor 120 to be used, as will be described below.

In one example embodiment, reading of the V ge (or, alternatively V gs ) by the digital device 118 as opposed to receiving such information from the inverter and control system 124 , may result in synchronizing V ge (or, alternatively V gs ) with the measured value of the voltage drop across the semiconductor switch 106 (e.g., V ce ) and thus avoid any delay due to additional connectors/cables used in transmitting the information from the inverter and control system 124 to the processor 120 .

The processor 120 , as will be described below with respect to FIG. 2 , may estimate the current through the power electronics switching circuit 102 based on the digitized voltages and a current-voltage characteristics of at least the semiconductor switch 104 .

The current estimated by the processor 120 may then be used by an inverter and/or a control system 124 to control desired parameters (e.g., speed, torque, etc.) of the machine 126 . The machine 126 may be any one of, but not limited to, a hybrid machine, a heavy equipment machine, etc. In one example embodiment, a certain torque and a certain speed may be desired for operating the machine 126 . In order to provide the certain torque/speed, the inverter and control systems 124 supplies controlled currents at the regulated magnitude and frequency to electric motors in the machine 126 , where the controlled currents may be determined based on the current estimated by the processor 120 of the device 104 . The regulated magnitude and frequency may be supplied to electric motors in the machine 126 by turning ON or OFF the power electronics switching circuit (e.g., power electronics switching circuit 102 ).

FIG. 2 illustrates a flowchart of a method of estimating the current flowing through the power electronics switching circuit shown in FIG. 1 , according to an example embodiment. At S 200 , the first circuit 116 of the device 104 measures a first voltage (e.g., V ce or alternatively, V DS ), when the semiconductor switch 106 (IGBT transistor 106 or alternatively, the MOSFET transistor 106 ) is in the operating state (e.g., the semiconductor switch 106 is ON)). For example, when the semiconductor switch 106 is ON, the capacitor 116 - 5 (C 1 ) may discharge to a level that is higher than a voltage across the semiconductor switch 106 by the amount of voltage drop across the diode 116 - 4 (D 3 ). The voltage cross the diode 116 - 4 may remain constant and negligibly small over temperature fluctuations because at voltage balance condition stated above (e.g., capacitor 116 - 5 (C 1 ) discharging by the amount that is higher than voltage across the semiconductor switch 106 by the amount of voltage drop across the diode 116 - 4 (D 3 )), no current flows from the capacitor 116 - 5 to the semiconductor switch 106 via the resistor 116 - 3 (R 3 ) and the diode 116 - 4 . Therefore, the voltage drop across the capacitor 116 - 5 may be the same as the voltage across the semiconductor switch 106 and thus its value may be measured so as to measure the voltage across the semiconductor switch 106 (e.g., V ce in IGBT or, alternatively V DS in FET).

At S 210 , the digital device 118 of the device 104 may digitize the first voltage. The digital device 118 may further, as described above, read V ge or V GS of the semiconductor switch 106 , depending on the type of the semiconductor switch 106 .

At S 215 , the processor 120 of the device 104 may receive an estimate of the temperature of the power electronics switching circuit. Such estimated temperature may be provided from the inverter/control system 124 . The semiconductor switch 106 may exhibit different voltage-current (may also be referred to as voltage-ampere) characteristics at different temperatures. Similarly, the diode 108 may exhibit different voltage-current (may also be referred to as voltage-ampere) characteristics at different temperatures. The different voltage-ampere characteristics of the semiconductor switch 106 and/or different voltage-ampere characteristics of the diode 108 , over a range of temperatures, may be programmed/stored in the memory 122 .

In one example embodiment, the memory 122 may have been programmed or may have stored thereon different voltage current characteristic data of not only the semiconductor switch 106 /diode 108 but also that of any additional semiconductor switches/diode and/or other electronic circuit elements that may be used in one or more power electronics switching circuits.

The voltage-current characteristic data of the semiconductor switch 106 and/or the diode 108 may be initially provided by the manufacturer/supplier of the semiconductor switch 106 and/or diode 108 . Furthermore, the voltage-current characteristics of the semiconductor switch 106 and/or the diode 108 may be adjustable by a user. For example, adjusting of such voltage-current characteristics may be due to field tests, empirical data, motor load/generator load/electrical machine load characteristics and or based on voltage-current characteristics of semiconductor switches/diodes that may be used as replacements for the semiconductor switch 106 and the diode 108 , where the replacements may have been manufactured/provided by a different manufacturer/supplier.

Accordingly, at S 220 and upon receiving the estimated temperature, the processor 120 may access the memory 122 and determine a corresponding one of the voltage-current characteristics data from among data stored on the memory 122 , which corresponds to the semiconductor switch 106 and/or diode 108 .

At S 225 , the device 104 , via the processor 120 , may estimate a first current flowing through the semiconductor switch 106 . The processor 120 may estimate the first current using three inputs. The three inputs may be the digitized first voltage across the collector-emitter or drain-source of the semiconductor switch 106 , V ge or V GS of the semiconductor switch 106 (e.g., indicating whether the semiconductor switch 106 is ON or OFF), and a voltage-current characteristic of the semiconductor switch 106 corresponding to the received temperature.

In one example embodiment, the processor 120 may estimate the first current by executing a program, where the program implements a polynomial-based current estimation algorithm, a degree/order and form of which may be a matter of design choice and/or determined empirically. For example, during an initial configuration of the algorithm, tests may be performed during which polynomials of various forms and degrees/orders may be implemented and the results (e.g., estimated currents) may be compared to currents measured by, for example, high-fidelity, high accuracy and high-precision current probes, so as to determine the appropriate form and degree/order of such polynomial. Similar techniques may be applied to determine other appropriate polynomials, which will be described below for determining other values (currents, voltages, etc.).

The processor 120 may estimate the current flowing through the power electronics switching circuit 102 at every specific time interval, where the number of time intervals may be regulated by a clock rate of a clock (not shown) of the processor 120 (e.g., the clock rate may be in the nano-seconds range). In one example embodiment, the processor 120 may estimate the current flowing through the power electronics switching circuit 102 whenever power electronics switching circuit 102 changes its status from ON to OFF and OFF to ON. Furthermore, the processor 120 's clock may be synchronized with switching frequency of the control signal 128 . Since Inverter control system is communicating with the processor 120 and the digital device 118 , therefore clock can be synchronized with switching frequency of power electronics switching circuit 102 .

To estimate the current, the processor 120 may input the three received inputs into the program according to the following:

i IGBT _ estimated (n) =ƒ( v ce _ digitized (n) ,v ge _ state (n) ,T J _ sw _ estimated )  (1)

where, n corresponds to the n th sampling interval, i IGBT _ estimated is the n th sampling interval estimated current flowing through the semiconductor switch 106 , ƒ is a function that implements the polynomial, v ce _ digitized (n) is the digitized first voltage (e.g., V ce or alternatively, V DS ) at the n th sampling interval, v ge _ state (n) is the digitized V ge or the V GS of the semiconductor switch 106 at the n th sampling interval and T J _ sw _ estimated is the estimated temperature of the power electronics switching circuit 106 . It will be appreciated that i IGBT _ estimated (n) may be replaced by i MOSFET _ estimated (n) if the semiconductor switch 106 is a MOSFET transistor.

Once the processor 120 estimates the first current at S 225 , the processor 120 estimates a second current, for the (n+1) th sampling interval flowing through the diode 108 at S 230 . In one example embodiment, the processor 120 may estimate the second current as follows.

In order to estimate the current flowing through the power electronics switching circuit 102 , the processor 120 may first determine a voltage drop across the diode 108 for the n th sampling interval, based on the estimated first current flowing through the semiconductor switch 106 determined at S 225 . The processor 120 may determine the n th sampling interval voltage drop across the diode 108 using the polynomial with appropriate form and degree/order. The processor may determine the voltage drop across the diode 108 , as follows:

v d(n) =ƒ( i IGBT _ estimated (n) ,v ge _ states (n) ,(volt-ampere) diode ,T J _ sw _ estimated)   (2)

wherein v d(n) is the voltage drop for the n th sampling interval, to be determined, across the diode 108 , ƒ is a function that implements the appropriate polynomial, i IGBT _ estimated (n) (or, alternatively, i MOSFET _ estimated(n) ) is the n th sampling interval current flowing through the semiconductor switch 106 , estimated at S 225 , (volt-ampere) diode is the voltage-ampere characteristic of the diode 108 at T J _ sw _ estimated , which is the estimated temperature of the power electronics switching circuit.

Once the voltage drop across the diode is determined, the processor 120 may estimate the second current flowing through the diode 108 for the (n+1) th sampling interval. The processor 120 may estimate the current flowing through the diode 108 using the polynomial with appropriate form and degree/order. The processor may estimate the current flowing through the diode 108 , as follows:

i diode _ estimated(n+1) =ƒ{v d(n) ,(volt-ampere) diode ,T J _ sw _ estimated}   (3)

wherein i diode _ estimated(n+1) is the (n+1) th sampling interval current, to be estimated, flowing through the diode 108 . v d(n) is the n th sampling interval voltage drop across the diode 108 , ƒ is a function that implements the appropriate polynomial, (volt-ampere) diode is the voltage-ampere characteristic of the diode 108 and T J _ sw _ estimated is the estimated temperature of the power electronics switching circuit.

At S 235 , the processor 120 may estimate the current flowing through the power electronics switching circuit, i sw _ estimated , based on the first current estimated at S 225 and the second current estimated at S 230 . In one example embodiment, the processor 120 may estimate the current flowing through the power electronics switch as the sum of the first and second currents estimated at S 225 and S 230 , respectively.

In one example embodiment, estimating the current flowing through the power electronics switching circuit 102 as described with respect to FIGS. 1-2 and through the use of a polynomial-based current estimation algorithm, eliminates the need for using external current sensors, which have the disadvantages, described above.

FIG. 3 depicts another apparatus including a power electronics switching circuit and a device for estimating a current flowing through the power electronics switching circuit, according to an example embodiment. The apparatus 300 is similar to the apparatus 100 , except as described below. Elements designated by reference numerals 300 , 302 , 304 , 306 , 308 , 310 , 312 , 314 , 316 - 1 to 316 - 5 , 318 , 320 , 322 , 324 , 326 and 328 in FIG. 3 , are the same as elements designated by reference numerals 100 , 102 , 104 , 106 , 108 , 110 , 112 , 114 , 116 - 1 to 116 - 5 , 118 , 120 , 122 , 124 , 126 and 128 in FIG. 1 . Therefore, a description of elements of apparatus 300 corresponding to the described elements of apparatus 100 is omitted.

As can be seen from FIG. 3 , the device 302 , compared to its counterpart 102 , includes an additional second circuit 330 , which as will be described below, may be utilized to measure a voltage across the diode 308 . Similar to the first circuit 316 , the second circuit also includes a voltage source 330 - 1 , a first resistance element 330 - 2 , a second resistance element 330 - 3 , a diode 330 - 4 and a capacitance element 330 - 5 .

FIG. 4 illustrates a flowchart of a method of estimating the current flowing through the power electronics switching circuit shown in FIG. 3 , according to an example embodiment. At S 400 , the device 304 , via the first circuit 316 measure a first voltage across the collector-emitter/drain-source of the semiconductor switch 306 (V ge or V DS , depending on the type of the semiconductor switch 306 . The manner in which the first circuit 316 measures the first voltage across the collector emitter/drain-source of the semiconductor switch 306 , is the same as that described at S 200 , in FIG. 2 .

At S 405 , the device 304 , via the second circuit 330 , measures a second voltage across the diode 308 . For example, when the diode 308 is conducting (e.g., when the semiconductor device 306 is OFF), the capacitor 330 - 5 (C 2 ) may discharge to a level that is higher than a voltage across the diode 308 by the amount of voltage drop across the diode 330 - 4 (D 4 ). The voltage cross the diode 330 - 4 may remain constant and negligibly small over temperature fluctuations because at voltage balance condition stated above (e.g., capacitor 330 - 5 (C 2 ) discharging by the amount of voltage drop across the diode 330 - 4 plus voltage across the diode 308 ), no current flows from the capacitor 330 - 5 to the diode 308 via the resistor 330 - 3 (R 4 ) and the diode 330 - 4 . Therefore, the voltage drop across the capacitor 330 - 5 may be the same as the voltage across the diode 308 and thus its value may be measured so as to measure the voltage across the diode 308 .

At S 410 , the device 304 , via the digital device 318 digitizes the first and second voltages measured at S 400 and S 405 , respectively. The digital device 318 may further digitize V ge or V GS of the semiconductor switch 306 , depending on the type of the semiconductor switch 306 . The digital device 318 is the same as the digital device 118 described with reference to FIG. 1 .

At S 415 the processor 320 may receive an estimate of the temperature of the power electronics switching circuit 302 . The processor 320 , similar to processor 120 , may receive the temperature estimate from the inverter/control system 324 .

At S 420 , similar to the process described with respect to S 220 , the processor 320 may determine the appropriate voltage-current characteristics of the semiconductor switch 306 /diode 308 , based on the estimated temperature of the power electronics switching circuit received at S 415 .

At S 425 , the device 304 , via the processor 320 , may estimate the current i sw _ estimated flowing through the power electronics switching circuit 302 . The device 304 may synchronize the digitized first and second voltages with the digitized V ge or V GS of the semiconductor switch 306 , determined at S 410 . The device 304 may then feed synchronized voltages into the processor 320 . The processor 320 may implement a polynomial based current estimation algorithm, which may take the digitized first and second voltages, the digitized V ge or V GS of the semiconductor switch 306 as well as the estimate temperature of the power electronics switching circuit 302 . The output of the implemented polynomial based algorithm may be the estimated current flowing through the power electronics switching circuit 302 . As discussed above, the form and degree/order of the underlying polynomial may be based on empirical studies and/or may be a matter of design choice.

In one example embodiment, estimating the current flowing through the power electronics switching circuit 302 as described with respect to FIGS. 3-4 and through the use of a polynomial-based current estimation algorithm, eliminates the need for using external current sensors, which have the disadvantages, described above.

In one example embodiment, an inverter such as the inverter 124 of FIG. 1 and/or the inverter 324 of FIG. 3 may be a dual system inverter used for on-board power generation and traction systems in machines (e.g., hybrid machines). Accordingly different power electronics switching systems may be associated with a high-side (HS) and a low-side (LS) of the dual system inverter. In order to estimate a current for each phase of the inverter (e.g., inverter 124 / 324 ), a first portion of the current flowing through the HS power electronics switching circuit and a second portion of the current flowing through the LS power electronics switching circuit need to be estimated.

FIG. 5 depicts an electrical structure with a high-side apparatus and a low-side apparatus and a device in each apparatus for estimating a portion of a current flowing through a power electronics switching circuit included in each apparatus, according to an example embodiment. As shown in FIG. 5 , the electrical structure 550 includes a pair of a HS apparatus 500 -HS, a LS apparatus 500 -LS and a processor 555 . The HS side apparatus 500 -HS includes a HS power electronics switching circuit 502 -HS and a HS device 504 -HS. The LS side apparatus 500 -LS includes a LS power electronics switching circuit 502 -LS and a LS device 504 -LS. The HS apparatus 500 -HS is the same as the apparatus 100 shown in FIG. 1 . The LS apparatus 500 -LS is the same as the apparatus 100 shown in FIG. 1 . Accordingly, for a given sampling interval, the processor of the HS device 504 -HS estimates a first portion of the current, i phase _ estimated _ HS , flowing through the HS power electronics switching circuit 502 -HS, in the same manner as that described above with reference to FIG. 2 . Similarly, for the given sampling interval, the processor of the LS device 504 -LS estimates a second portion of the current, i phase _ estimated _ LS , flowing through the LS power electronics switching circuit 502 -LS, in the same manner as that described above with reference to FIG. 2 .

Thereafter, the processor 555 may estimate the current i phase _ estimated by, for example, adding the i phase _ estimated _ HS and i phase _ estimated _ LS estimated by processors of the 504 -HS and 504 -LS, respectively. Thereafter, the i phase _ estimated may be used by the inverter 524 to control the machine 526 .

FIG. 6 depicts another electrical structure with a high-side apparatus and a low-side apparatus and a device in each apparatus for estimating a portion of a current flowing through a power electronics switching circuit included in each apparatus, according to an example embodiment. As shown in FIG. 6 , the electrical structure 650 includes a pair of a HS apparatus 600 -HS, a LS apparatus 600 -LS and a processor 655 . The HS side apparatus 500 -HS includes a HS power electronics switching circuit 602 -HS and a HS device 604 -HS. The LS side apparatus 600 -LS includes a LS power electronics switching circuit 602 -LS and a LS device 604 -LS. The HS apparatus 600 -HS is the same as the apparatus 300 shown in FIG. 3 . The LS apparatus 600 -LS is the same as the apparatus 300 shown in FIG. 3 . The processor of the HS device 604 -HS estimates a first portion of the current i phase _ estimated _ HS , flowing through the HS power electronics switching circuit 602 -HS, in the same manner as that described above with reference to FIG. 4 . The processor of the LS device 604 -LS estimates a second portion of the current, i phase _ estimated _ LS , flowing through the LS power electronics switching circuit 602 -LS, in the same manner as that described above with reference to FIG. 4 .

Thereafter, the processor 655 may estimate the current i phase _ estimated by, for example, adding the i phase _ estimated _ HS and i phase _ estimated _ LS estimated by processors of the 604 -HS and 604 -LS, respectively. Thereafter, the i phase _ estimated may be used by the inverter 624 to control the machine 626 .

FIGS. 7A-C illustrates converter phase having a HS and LS power electronics switching circuit as well as directions of the phase current for the converter phase, according to an example embodiment. As shown in FIG. 7A , i phase is a resultant of two currents, i phase-HS and i phase-LS from the HS power electronics switching circuit 702 -HS and the LS power electronics switching circuit 702 -LS, respectively. As shown in FIG. 7B , when the semiconductor switch 706 -HS is ON, i phase-HS flows through the semiconductor switch 706 -HS while no current flows through the diode 708 -HS. Also, when the semiconductor switch 706 -HS is ON, semiconductor switch 706 -LS is OFF and i phase-LS flows through the diode 708 -LS. Therefore, i phase is the sum of the current flowing through the semiconductor switch 706 -HS and the current flowing through diode 708 -LS. Similarly, as shown in FIG. 7C , when the semiconductor switch 706 -HS is OFF, semiconductor switch 706 -LS is ON and thus i phase may be a sum of the current flowing through the diode 708 -HS and the current flowing through the semiconductor switch 706 -LS.

Based on the method described with reference to FIG. 2 , the determination of the currents and voltages, described with respect to FIGS. 7A-C , may be based on the following. i IGBT _ estimated(n) _ HS of the semiconductor switch 706 -HS, for the n th sampling interval, may first be determined according to equation (4) below:

i IGBT _ estimated(n) _ HS =ƒ( v ce _ digitized(n) _ HS ,v ge _ state(n) ,T J _ sw _ estimated _ HS )  (4)

Using the estimated IGBT current for the HS, a voltage drop across the LS diode 708 -LS may be determined according to equation (5) below:

v d(n−1) _ LS =ƒ( i IGBT _ estimated(n−1) _ HS ,v ge _ state(n−1) _ HS ,v ge _ state(n−1) _ LS ,(volt- ampere) diode _ LS ,T J _ sw _ estimated _ LS )  (5)

Using the estimated voltage drop across the diode 708 -LS, the current flowing through the LS diode 708 -LS may be determined according to equations (6) below:

i diode _ estimated(n) _ LS =ƒ{v d(n−1) _ LS ,(volt-ampere) diode _ LS ,T J _ sw _ estimated _ LS }  (6)

Accordingly, i phase may be given by:

i sw _ estimated(n) =i IGBT _ estimated(n) _ HS +i diode _ estimated(n) _ LS   (7)

In one example embodiment, applying the method described with respect to FIG. 4 (e.g., measuring the voltage drops across the semiconductor switches 706 -HS/ 706 -LS and diodes 708 -HS/ 708 -LS) to FIG. 7 , the i phase may be determined as follows:

i phase _ estimated(n) _ HS =i IGBT _ estimated(n) _ HS +i diode _ estimated(n) _ HS   (8)

i phase _ estimated(n) _ LS =i IGBT _ estimated(n) _ LS +i diode _ estimated(n) _ LS   (9)

Where i IGBT _ estimated(n) _ HS , i IGBT _ estimated(n) _ LS , i diode _ estimated(n) _ HS and i diode _ estimated(n) _ HS in (8) and (9) may be determined based on voltage drops measured across the HS/LS semiconductor switches and diodes, given by:

v sw _ digitized(n) _ HS =v ce _ digitized(n) _ HS +v d _ digitized(n) _ HS   (10)

v sw _ digitized(n) _ LS =v ce _ digitized(n) _ LS +v d _ digitized(n) _ LS   (11)

i phase _ estimated(n) _ HS =ƒ{v sw _ digitized(n) _ HS ,v ge _ state(n) _ HS ,v ge _ state(n) _ LS }  (12)

i phase _ estimated(n) _ LS =ƒ{v sw _ digitized(n) _ LS ,v ge _ state(n) _ HS ,v ge _ state(n) _ LS }  (13)

Then,

i phase _ estimated(n) =i phase _ estimated(n) _ HS +i phase _ estimated(n) _ HS   (14)

FIG. 8 illustrates a dual inverter system deployable for on-board power generation and traction systems in hybrid vehicles, employing a plurality of apparatuses described with respect to FIGS. 1-2 , according to an example embodiment. FIG. 8 illustrates a circuit configuration 800 -A for on-board power generation where a plurality of apparatuses such as those described with respect to FIG. 1 and FIG. 3 are utilized in the dual inverter system (e.g., 800 HS/LS numbered and shown as an example of the plurality of apparatuses). Each apparatus comprises a power electronics switching circuit (e.g., 802 -HS or 802 -LS) and a device (e.g., 804 -HS or 804 -LS) for estimating a current flowing through the corresponding one of the power electronics switches 802 -HS/ 802 -LS. The estimated currents (e.g., output i sw-sg1 of the device 804 -HS or output i sw-sg4 of the device 804 -LS, for example) may then be used to control each phase of the three-phase current, generated by the electric generator 850 , associated one pair of HS/LS power electronics switching circuit (e.g., 802 -HS and 802 -LS), as shown in FIG. 8 .

Furthermore, FIG. 8 illustrates a circuit configuration 800 -B for on-board traction system where a plurality of apparatuses such as those described with respect to FIG. 1 and FIG. 3 are utilized in a similar manner as that described with respect to the circuit configuration 800 -A.

While FIG. 8 illustrates a dual inverter system deployable for on-board power generation and traction systems in hybrid vehicles, employing a plurality of apparatuses described with respect to FIGS. 1-2 , the plurality of apparatuses described with respect to FIG. 3-4 may also be used (either concurrently with or in place of that described with respect to FIG. 1-2 ).

FIG. 9 illustrates a permanent magnet generator with a three phase output and an n-phase switch reluctance machine, employing a plurality of apparatuses described with respect to FIGS. 1-2 , according to an example embodiment.

FIG. 9 illustrates a circuit configuration 900 -A, which may be a permanent magnet (PM) generator with a three-phase output, where a plurality of apparatuses such as those described with respect to FIG. 1 and FIG. 3 are utilized (e.g., 900 HS/LS numbered and shown as an example of the plurality of apparatuses). Each apparatus comprises a power electronics switching circuit (e.g., 902 -HS or 902 -LS) and a device (e.g., 904 -HS or 904 -LS) for estimating a current flowing through the corresponding one of the power electronics switches 902 -HS/ 902 -LS. The estimated currents (e.g., output i sw-sg1 of the device 904 -HS or output i sw-sg4 of the device 904 -LS, for example) may then be used to control each phase of the three-phase output of the permanent magnet generator 900 -A, generated by the electric generator 950 , associated with one pair of HS/LS power electronics switching circuit (e.g., 902 -HS and 902 -LS), as shown in FIG. 9 .

Furthermore, FIG. 9 illustrates a circuit configuration 900 -B, which may be an n-phase switch reluctance machine, where a plurality of apparatuses such as those described with respect to FIG. 1 and FIG. 3 are utilized in a similar manner as that described with respect to the circuit configuration 900 -A.

There are four operating modes associated with the each phase of the n-phase switch reluctance machine 900 -B. Accordingly, a description of phase 1 of the switch reluctance (SR) machine 900 -B will be given as an example of the n-phase switch reluctance machine 900 -B.

In Mode 1, the power electronics switching circuit 970 (ST 11 ) and the power electronics switching circuit 972 (ST 12 ), shown in FIG. 9 , are ON. Therefore, a current (i phase _ 1 ) through SR traction machine winding 974 will be established. As the machine winding 974 is connected across inverter's DC bus and DC bus forward (+V dc ), connected to the switching power electronics switching circuit 970 and 974 (shown in FIG. 3 but not in FIG. 9 ), application of inverter DC bus voltage across the machine winding 974 will cause the current (i phase _ 1 ) through the machine winding 974 to rise. Then SR machine phase current is expressed as below;

i phase _ 1 =i st11 =i st12   (15)

In Mode 2, the power electronics switching circuit 970 (ST 11 ) is ON and the power electronics switching circuit (ST 12 ) is OFF. Therefore, current flowing through the SR machine will free-wheel and no voltage will be applied across the SR machine winding 974 . Accordingly, the amount of current through the SR machine may decline at a rate governed by machine time constant

( τ = L SR R SR ) .

Accordingly,

i phase _ 1 =i st11 =i dt11   (16)

In Mode 3, the power electronics switching circuit 970 (ST 11 ) is OFF and the power electronics switching circuit (ST 12 ) is ON. Therefore, current through SR machine will free-wheel and no voltage will be applied across the SR machine winding 974 . Accordingly, the amount of current through the SR machine may decline at a rate governed by machine time constant (τ). Accordingly,

i phase _ 1 =i st12 =i dt12   (17)

In Mode 4, the power electronics switching circuit 970 (ST 11 ) and the power electronics switching circuit (ST 12 ) are OFF. Therefore, current flowing through SR machine will free-wheel through diode 976 (DT 12 ) and the diode 978 (DT 12 ) and back to inverter DC causing regenerative braking. Therefore, reverse voltage (−V dc ) will be applied across the SR machine winding 974 . Due to application of reverse voltage (−V dc ) current through SR machine winding 974 will decline at a faster rate than the free-wheel current condition stated above. Accordingly,

i phase _ 1 =i dt12 =i dt11   (18)

From equations (15) to (18), it will be appreciated that if the currents through the power electronics switches 970 and 972 (ST 11 and ST 12 ) and the diodes 976 and 978 (DT 11 and DT 12 ) are estimated using methods described with respect to FIGS. 1-2 , the phase current of SR machine 900 -B may be estimated accurately without using any external current sensors, which provides the advantages described below.

While FIG. 9 illustrates a permanent magnet generator with a three phase output and an n-phase switch reluctance machine, employing a plurality of apparatuses described with respect to FIGS. 1-2 , the plurality of apparatuses described with respect to FIG. 3-4 may also be used (either concurrently with or in place of that described with respect to FIG. 1-2 ).

In yet another example embodiment, the apparatuses described with respect to FIG. 1 and FIG. 3 may be utilized in current sensing for inverter needed for brushless DC motor having trapezoidal back electro-motive force (emf) and rectangular wave shaped current.

As described above, the example current sensing apparatuses and the corresponding polynomial based estimation methods, described above with reference to FIGS. 1-4 , eliminate the need for external current sensors conventionally used to sense current of power electronics switching circuits.

Some of the advantages of utilizing the current sensing apparatuses and associated methods, described above include, first, significant cost reduction may be achieved as current sensors and the associated assembly is eliminated. Second, errors caused by current sensors will be eliminated, therefore, electric drive control systems will offer improved and precise performance due to elimination of variations caused by current sensors and current sensor processing circuit. Third, the electric drive will be able to respond much faster to abnormal conditions in the electric drive such as over current conditions and inverter output shorted to vehicle chassis. This may be due to the current estimation scheme implemented within a fast digital processor (e.g., processor 120 of FIG. 1 ), where the associated clock time may be in nano-seconds as opposed to sensor response of conventional current sensors which is in micro-seconds. Fourth, the current sensing apparatuses described above, will result in elimination or reduction in the number of current sensors in electric-drive, therefore resulting in simpler overall inverter systems having smaller footprints, lower cost associated therewith, and an increased reliability due to elimination of breakdown(s) caused by sensor failure(s) as may be the case with conventional current sensors that fail due to vibration and over temperature caused by, for example, self-heating in such sensors.

Example embodiments being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of example embodiments, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the claims.