Solar photovoltaic power conversion system and method of operating the same

1. Technical Field

The present disclosure relates generally to a solar photovoltaic power conversion system and a method of operating the same, and more particularly to a solar photovoltaic power conversion system and a method of operating the same which are provided to reduce leakage current of a DC input voltage caused by parasitic capacitance voltage.

2. Description of Related Art

Reference is made to FIG. 1 which is a block diagram of a related art dual-buck inverter. The dual-buck inverter receives a DC input voltage Vdc, and converts the DC input voltage Vdc into an AC output voltage Vac. The dual-buck inverter includes two buck circuits, namely, a first buck circuit BC 1 and a second buck circuit BC 2 . The first buck circuit BC 1 mainly has a first bridge arm Lg 1 a and a second bridge arm Lg 2 a . The first bridge arm Lg 1 a has a first switch S 1 a and a first diode D 1 a connected in series to the first switch S 1 a . The second bridge arm Lg 2 a has a second switch S 2 a and a second diode D 2 a connected in series to the second switch S 2 a . The second buck circuit BC 2 mainly has a third bridge arm Lg 3 a and a fourth bridge arm Lg 4 a . The third bridge arm Lg 3 a has a third switch S 3 a and a third diode D 3 a connected in series to the third switch S 3 a . The fourth bridge arm Lg 4 a has a fourth switch S 4 a and a fourth diode D 4 a connected in series to the fourth switch S 4 a . Also, the first buck circuit BC 1 and the second buck circuit BC 2 are connected in parallel to an input capacitor C 1 a.

Reference is made to FIG. 2 which is a schematic waveform graph of driving signals for controlling the related art dual-buck inverter. A driving signal generating circuit (not shown) is provided to produce a plurality of control signals, namely a first control signal Sca 1 , a second control signal Sca 2 , a third control signal Sca 3 , and a fourth control signal Sca 4 to correspondingly control the first switch S 1 a , the second switch S 2 a , the third switch S 3 a , and the fourth switch S 4 a.

The first control signal Sca 1 and the second control signal Sca 2 are a complementary low-frequency signal pair. When the AC output voltage Vac is under a positive half-cycle operation (during a time interval between time t0 and time t1), the first control signal Sca 1 turns on the first switch S 1 a and the second control signal Sca 2 turns off the second switch S 2 a , and the third control signal Sca 3 turns off the third switch S 3 a and the fourth control signal Sca 4 controls the fourth switch S 4 a in the high-frequency switching manner. When the AC output voltage Vac is under a negative half-cycle operation (during a time interval between time t1 and time t2), the first control signal Sca 1 turns off the first switch S 1 a and the second control signal Sca 2 turns on the second switch S 2 a , and the third control signal Sca 3 controls the third switch S 3 a in the high-frequency switching manner and the fourth control signal Sca 4 turns off the fourth switch S 4 a.

However, the leakage current Icp 1 , Icp 2 would be rapidly changed once the parasitic capacitance voltage of the parasitic capacitances Cp 1 , Cp 2 significantly change because of the large variation of the AC output voltage Vac of the dual-buck inverter. That is, the leakage current gets larger as the variation of the parasitic capacitance voltage gets larger.

Accordingly, it is desirable to provide a solar photovoltaic power conversion system and a method of operating the same to control a dual-buck inverter having two switching circuits and two filtering circuits so as to provide energy-storing and energy-releasing loops of output inductors and connect the filtering circuits to a neutral point at a DC input side, thus significantly reducing leakage current of a DC input voltage caused by parasitic capacitance voltage.

An object of the present disclosure is to provide a solar photovoltaic power conversion system to solve the above-mentioned problems. Accordingly, the solar photovoltaic power conversion system is provided to convert a DC input voltage into an AC output voltage. The solar photovoltaic power conversion system includes an input capacitor bank, a first switching circuit, a second switching circuit, a first filtering circuit, a second filtering circuit, and a control circuit.

The input capacitor bank has a first capacitor and a second capacitor, and the first capacitor and the second capacitor are connected to a neutral point and configured to receive the DC input voltage. The first switching circuit is connected in parallel to the input capacitor bank, and the first switching circuit has a first bridge arm and a second bridge arm connected in parallel to the first bridge arm. The second switching circuit is connected in parallel to the input capacitor bank, and the second switching circuit has a third bridge arm and a fourth bridge arm connected in parallel to the third bridge arm. The first filtering circuit is connected to the first switching circuit, and an output side of the first filtering circuit is connected to the neutral point. The second filtering circuit is connected to the second switching circuit, and an output side of the second filtering circuit connected to the neutral point. The control circuit is configured to produce a plurality of control signals to control the first switching circuit and the second switching circuit, respectively, to reduce leakage current of the DC input voltage caused by parasitic capacitance voltage.

Another object of the present disclosure is to provide a method of operating a solar photovoltaic power conversion system to solve the above-mentioned problems. Accordingly, the solar photovoltaic power conversion system converts a DC input voltage into an AC output voltage, and the method includes following steps: (a) providing an input capacitor bank to receive the DC input voltage; wherein the input capacitor bank has a first capacitor and a second capacitor, and the first capacitor and the second capacitor are connected to a neutral point; (b) providing a first switching circuit connected in parallel to the input capacitor bank; wherein the first switching circuit has a first bridge arm and a second bridge arm connected in parallel to the first bridge arm; (c) providing a second switching circuit connected in parallel to the input capacitor bank; wherein the second switching circuit has a third bridge arm and a fourth bridge arm connected in parallel to the third bridge arm; (d) providing a first filtering circuit; wherein the first filtering circuit is connected to the first switching circuit and an output side of the first filtering circuit is connected to the neutral point; (e) providing a second filtering circuit; wherein the second filtering circuit is connected to the second switching circuit and an output side of the second filtering circuit is connected to the neutral point; and (f) providing a control circuit to produce a plurality of control signals to control the first switching circuit and the second switching circuit, respectively, to reduce leakage current of the DC input voltage caused by parasitic capacitance voltage.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the present disclosure as claimed. Other advantages and features of the present disclosure will be apparent from the following description, drawings and claims.

The features of the present disclosure believed to be novel are set forth with particularity in the appended claims. The present disclosure itself, however, may be best understood by reference to the following detailed description of the present disclosure, which describes an exemplary embodiment of the present disclosure, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a related art dual-buck inverter;

FIG. 2 is a schematic waveform graph of driving signals for controlling the related art dual-buck inverter;

FIG. 3 is a circuit diagram of a solar photovoltaic power conversion system according to the present disclosure;

FIG. 4 is a schematic circuit diagram of a control circuit of the solar photovoltaic power conversion system according to the present disclosure;

FIG. 5 is a schematic waveform graph of control signals for controlling the solar photovoltaic power conversion system according to the present disclosure;

FIG. 6 is a circuit diagram of the solar photovoltaic power conversion system under a positive half-cycle energy-storing operation according to the present disclosure;

FIG. 7 is a circuit diagram of the solar photovoltaic power conversion system under a positive half-cycle energy-releasing operation according to the present disclosure;

FIG. 8 is a circuit diagram of the solar photovoltaic power conversion system under a negative half-cycle energy-storing operation according to the present disclosure;

FIG. 9 is a circuit diagram of the solar photovoltaic power conversion system under a negative half-cycle energy-releasing operation according to the present disclosure; and

FIG. 10 is a flowchart of a method of operating a solar photovoltaic power conversion system according to the present disclosure.

Reference will now be made to the drawing figures to describe the present invention in detail.

Reference is made to FIG. 3 which is a circuit diagram of a solar photovoltaic power conversion system according to the present disclosure. The solar photovoltaic power conversion system is provided to convert a DC input voltage Vdc into an AC output voltage Vac. The solar photovoltaic power conversion system includes an input capacitor bank 10 , a first switching circuit 11 , a second switching circuit 12 , a first filtering circuit 21 , a second filtering circuit 22 , and a control circuit 30 . The input capacitor bank 10 has a first capacitor 101 and a second capacitor 102 . The first capacitor 101 and the second capacitor 102 are connected to a neutral point Po and receive the DC input voltage Vdc. In particular, the first capacitor 101 and the second capacitor 102 are connected to the neutral point Po to maintain a voltage across the first capacitor 101 and a voltage across the second capacitor 102 are equal to a half of the DC input voltage Vdc. The first switching circuit 11 is connected in parallel to the input capacitor bank 10 . The first switching circuit 11 has a first bridge arm Lg 1 and a second bridge arm Lg 2 connected in parallel to the first bridge arm Lg 1 . The first bridge arm Lg 1 is composed of a first power switch S 1 and a first diode D 1 connected in series to the first power switch S 1 , and the second bridge arm Lg 2 is composed of a second power switch S 2 and a second diode D 2 connected in series to the second power switch S 2 . The second switching circuit 12 is connected in parallel to the input capacitor bank 10 . The second switching circuit 12 has a third bridge arm Lg 3 and a fourth bridge arm Lg 4 connected in parallel to the third bridge arm Lg 3 . The third bridge arm Lg 3 is composed of a third power switch S 3 and a third diode D 3 connected in series to the third power switch S 3 , and the fourth bridge arm Lg 4 is composed of a fourth power switch S 4 and a fourth diode D 4 connected in series to the fourth power switch S 4 .

The first filtering circuit 21 has a first output inductor L 1 , a second output inductor L 2 , and a first output capacitor C 1 . The first output inductor L 1 has a first terminal and a second terminal, the second output inductor L 2 has a first terminal and a second terminal, and the first output capacitor C 1 has a first terminal and a second terminal. The first terminal of the first output inductor L 1 is connected to the first terminal of the second output inductor L 2 and connected to the first terminal of the first output capacitor C 1 . The second terminal of the first output inductor L 1 is connected to the first power switch S 1 and the first diode D 1 , and the second terminal of the second output inductor L 2 is connected to the second power switch S 2 and the second diode D 2 . The second terminal of the first output capacitor C 1 is connected to the neutral point Po. The second filtering circuit 22 has a third output inductor L 3 , a fourth output inductor L 4 , and a second output capacitor C 2 . The third output inductor L 3 has a first terminal and a second terminal, the fourth output inductor L 4 has a first terminal and a second terminal, and the second output capacitor C 2 has a first terminal and a second terminal. The first terminal of the third output inductor L 3 is connected to the first terminal of the fourth output inductor L 4 and connected to the first terminal of the second output capacitor C 2 . The second terminal of the third output inductor L 3 is connected to the third power switch S 3 and the third diode D 3 , and the second terminal of the fourth output inductor L 4 is connected to the fourth power switch S 4 and the fourth diode D 4 . The second terminal of the second output capacitor C 2 is connected to the neutral point Po. The AC output voltage Vac is outputted between the first terminal of the first output capacitor C 1 and the first terminal of the second output capacitor C 2 . The control circuit 30 produces a first control signal Sc 1 , a second control signal Sc 2 , a third control signal Sc 3 , and a fourth control signal Sc 4 to correspondingly control the first power switch S 1 , the second power switch S 2 , the third power switch S 3 , and the fourth power switch S 4 to reduce leakage current of the DC input voltage Vdc caused by parasitic capacitance voltage. The detailed operation of the solar photovoltaic power conversion system will be described hereinafter as follows.

Reference is made to FIG. 4 which is a schematic circuit diagram of a control circuit of the solar photovoltaic power conversion system according to the present disclosure. The control circuit 30 includes a signal inverting unit 303 , a first not gate unit 311 , a second not gate unit 312 , a first comparison unit 301 , and a second comparison unit 302 . The first comparison unit 301 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The non-inverting input terminal receives an AC output voltage signal Sac provided from the AC output voltage Vac and the inverting input terminal receives a triangular carrier signal Stri. The output terminal outputs the first control signal Sc 1 , and the output terminal is connected to the first not gate unit 311 to output the second control signal Sc 2 . The triangular carrier signal Stri is a high-frequency carrier signal. The second comparison unit 302 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The non-inverting input terminal is connected to the signal inverting unit 303 and receives the AC output voltage signal Sac and the inverting input terminal receives the triangular carrier signal Stri. The output terminal outputs the third control signal Sc 3 , and the output terminal is connected to the second not gate unit 312 to output the fourth control signal Sc 4 .

Reference is made to FIG. 5 which is a schematic waveform graph of control signals for controlling the solar photovoltaic power conversion system according to the present disclosure. When the AC output voltage Vac is under a positive half-cycle operation (during a time interval between time t0 and time t1), the first control signal Sc 1 and the second control signal Sc 2 is a complementary high-frequency switching signal pair, and the third control signal Sc 3 and the fourth control signal Sc 4 is a complementary low-frequency signal pair. When the AC output voltage Vac is under a negative half-cycle operation (during a time interval between time t1 and time t2), the first control signal Sc 1 and the second control signal Sc 2 is a complementary low-frequency signal pair, and the third control signal Sc 3 and the fourth control signal Sc 4 is a complementary high-frequency switching signal pair.

More specifically, when the AC output voltage Vac is under the positive half-cycle operation, the AC output voltage signal Sac is compared with the triangular carrier signal Stri by the first comparison unit 301 to produce the first control signal Sc 1 which is a pulse width modulation (PWM) signal. In addition, the first not gate unit 311 is provided to convert the first control signal Sc 1 into the second control signal Sc 2 which is also a PWM signal. In particular, the second control signal Sc 2 and the first control signal Sc 1 are the complementary high-frequency switching signals, that is, when the first control signal Sc 1 is high-level, the second control signal Sc 2 is low-level; on the contrary, when the first control signal Sc 1 is low-level, the second control signal Sc 2 is high-level. Especially, the switching frequency of the PWM signal is equal to the frequency of the triangular carrier signal Stri. In addition, the frequency of converting the third control signal Sc 3 and the fourth control signal Sc 4 is equal to the utility frequency of the AC output voltage signal Sac.

Similarly, when the AC output voltage Vac is under the negative half-cycle operation, the AC output voltage signal Sac is converted to produce an inverting AC output voltage signal Sac- by the signal inverting unit 303 , and the inverting AC output voltage signal Sac- is compared with the triangular carrier signal Stri by the second comparison unit 302 to produce the third control signal Sc 3 which is a PWM signal. In addition, the second not gate unit 312 is provided to convert the third control signal Sc 3 into the fourth control signal Sc 4 which is also a PWM signal. In particular, the fourth control signal Sc 4 and the third control signal Sc 3 are the complementary high-frequency switching signals, that is, when the third control signal Sc 3 is high-level, the fourth control signal Sc 4 is low-level; on the contrary, when the third control signal Sc 3 is low-level, the fourth control signal Sc 4 is high-level. Especially, the switching frequency of the PWM signal is equal to the frequency of the triangular carrier signal Stri. In addition, the frequency of converting the first control signal Sc 1 and the second control signal Sc 2 is equal to the utility frequency of the AC output voltage signal Sac.

Reference is made to FIG. 6 which is a circuit diagram of the solar photovoltaic power conversion system under a positive half-cycle energy-storing operation according to the present disclosure. When the AC output voltage Vac is under the positive half-cycle operation, and the first power switch S 1 is turned on by the first control signal Sc 1 in the high-frequency switching manner and the fourth power switch S 4 is turned on by the fourth control signal Sc 4 in the low-frequency high-level manner, the first output inductor L 1 and the fourth output inductor L 4 are under the energy-storing operation through a positive half-cycle energy-storing loop Lps sequentially formed by the DC input voltage Vdc, the first power switch S 1 , the first output inductor L 1 , the AC output voltage Vac, the fourth output inductor L 4 , the fourth power switch S 4 , and the DC input voltage Vdc.

Reference is made to FIG. 7 which is a circuit diagram of the solar photovoltaic power conversion system under a positive half-cycle energy-releasing operation according to the present disclosure. When the AC output voltage Vac is under the positive half-cycle operation, and the first power switch S 1 is turned off by the first control signal Sc 1 in the high-frequency switching manner and the fourth power switch S 4 is turned on by the fourth control signal Sc 4 in the low-frequency high-level manner, the first output inductor L 1 and the fourth output inductor L 4 are under the energy-releasing operation through a positive half-cycle energy-releasing loop Lpr sequentially formed by the first output inductor L 1 , the AC output voltage Vac, the fourth output inductor L 4 , the fourth power switch S 4 , the first diode D 1 , and the first output inductor L 1 .

Reference is made to FIG. 8 which is a circuit diagram of the solar photovoltaic power conversion system under a negative half-cycle energy-storing operation according to the present disclosure. When the AC output voltage Vac is under the negative half-cycle operation, and the third power switch S 3 is turned on by the third control signal Sc 3 in the high-frequency switching manner and the second power switch S 2 is turned on by the second control signal Sc 2 in the low-frequency high-level manner, the third output inductor L 3 and the second output inductor L 2 are under the energy-storing operation through a negative half-cycle energy-storing loop Lns sequentially formed by the DC input voltage Vdc, the third power switch S 3 , the third output inductor L 3 , the AC output voltage Vac, the second output inductor L 2 , the second power switch S 2 , and the DC input voltage Vdc.

Reference is made to FIG. 9 which is a circuit diagram of the solar photovoltaic power conversion system under a negative half-cycle energy-releasing operation according to the present disclosure. When the AC output voltage Vac is under the negative half-cycle operation, and the third power switch S 3 is turned off by the third control signal Sc 3 in the high-frequency switching manner and the second power switch S 2 is turned on by the second control signal Sc 2 in the low-frequency high-level manner, the third output inductor L 3 and the second output inductor L 2 are under the energy-releasing operation through a negative half-cycle energy-releasing loop Lnr sequentially formed by the third output inductor L 3 , the AC output voltage Vac, the second output inductor L 2 , the second power switch S 2 , the third diode D 3 , and the third output inductor L 3 .

Reference is made to FIG. 10 which is a flowchart of a method of operating a solar photovoltaic power conversion system according to the present disclosure. The solar photovoltaic power conversion system is provided to convert a DC input voltage into an AC output voltage. The method includes following steps. First, an input capacitor bank is provided to receive the DC input voltage. The input capacitor bank has a first capacitor and a second capacitor, and the first capacitor and the second capacitor are connected to a neutral point (S 10 ). Afterward, a first switching circuit connected in parallel to the input capacitor bank is provided. The first switching circuit has a first bridge arm and a second bridge arm connected in parallel to the first bridge arm; the first bridge arm is composed of a first power switch and a first diode connected in series to the first power switch, and the second bridge arm is composed of a second power switch and a second diode connected in series to the second power switch (S 20 ). Afterward, a second switching circuit connected in parallel to the input capacitor bank is provided. The second switching circuit has a third bridge arm and a fourth bridge arm connected in parallel to the third bridge arm; the third bridge arm is composed of a third power switch and a third diode connected in series to the third power switch, and the fourth bridge arm is composed of a fourth power switch and a fourth diode connected in series to the fourth power switch (S 30 ).

Afterward, a first filtering circuit is provided. The first filtering circuit has a first output inductor, a second output inductor, and a first output capacitor. The first output inductor has a first terminal and a second terminal, the second output inductor has a first terminal and a second terminal, and the first output capacitor has a first terminal and a second terminal. The first terminal of the first output inductor is connected to the first terminal of the second output inductor and connected to the first terminal of the first output capacitor. The second terminal of the first output inductor is connected to the first power switch and the first diode, and the second terminal of the second output inductor is connected to the second power switch and the second diode. The second terminal of the first output capacitor is connected to the neutral point (S 40 ). Afterward, a second filtering circuit is provided. The second filtering circuit has a third output inductor, a fourth output inductor, and a second output capacitor. The third output inductor has a first terminal and a second terminal, the fourth output inductor has a first terminal and a second terminal, and the second output capacitor has a first terminal and a second terminal. The first terminal of the third output inductor is connected to the first terminal of the fourth output inductor and connected to the first terminal of the second output capacitor. The second terminal of the third output inductor is connected to the third power switch and the third diode, and the second terminal of the fourth output inductor is connected to the fourth power switch and the fourth diode. The second terminal of the second output capacitor is connected to the neutral point (S 50 ). The AC output voltage is outputted between the first terminal of the first output capacitor and the first terminal of the second output capacitor. Finally, a control circuit is provided to produce a first control signal, a second control signal, a third control signal, and a fourth control signal to correspondingly control the first power switch, the second power switch, the third power switch, and the fourth power switch to reduce leakage current of the DC input voltage caused by parasitic capacitance voltage (S 60 ).

When the AC output voltage is under the positive half-cycle operation, and the first power switch is turned on by the first control signal in the high-frequency switching manner and the fourth power switch is turned on by the fourth control signal in the low-frequency high-level manner, the first output inductor and the fourth output inductor are under the energy-storing operation through a positive half-cycle energy-storing loop sequentially formed by the DC input voltage, the first power switch, the first output inductor, the AC output voltage, the fourth output inductor, the fourth power switch, and the DC input voltage.

When the AC output voltage is under the positive half-cycle operation, and the first power switch is turned off by the first control signal in the high-frequency switching manner and the fourth power switch is turned on by the fourth control signal in the low-frequency high-level manner, the first output inductor and the fourth output inductor are under the energy-releasing operation through a positive half-cycle energy-releasing loop sequentially formed by the first output inductor, the AC output voltage, the fourth output inductor, the fourth power switch, the first diode, and the first output inductor.

When the AC output voltage is under the negative half-cycle operation, and the third power switch is turned on by the third control signal in the high-frequency switching manner and the second power switch is turned on by the second control signal in the low-frequency high-level manner, the third output inductor and the second output inductor are under the energy-storing operation through a negative half-cycle energy-storing loop sequentially formed by the DC input voltage, the third power switch, the third output inductor, the AC output voltage, the second output inductor, the second power switch, and the DC input voltage.

When the AC output voltage is under the negative half-cycle operation, and the third power switch is turned off by the third control signal in the high-frequency switching manner and the second power switch is turned on by the second control signal in the low-frequency high-level manner, the third output inductor and the second output inductor are under the energy-releasing operation through a negative half-cycle energy-releasing loop sequentially formed by the third output inductor, the AC output voltage, the second output inductor, the second power switch, the third diode, and the third output inductor.

In conclusion, the present disclosure has following advantages:

The dual-buck inverter, composed of the first switching circuit 11 , the second switching circuit 12 , the first filtering circuit 21 , and the second filtering circuit 22 , is used to provide energy-storing and energy-releasing loops of the first output inductor L 1 , the second output inductor L 2 , the third output inductor L 3 , and the fourth output inductor L 4 . In addition, the first filtering circuit 21 and the second filtering circuit 22 are connected to the neutral point Po at the DC input side, thus significantly reducing leakage current of the DC input voltage Vdc caused by parasitic capacitance voltage.

Although the present disclosure has been described with reference to the preferred embodiment thereof, it will be understood that the present disclosure is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the present disclosure as defined in the appended claims.