High-speed divide-by-1.5 circuit with 50 percent duty cycle

High-speed data transceivers commonly include frequency divider circuits that convert a higher frequency to a lower frequency, i.e., divide a higher frequency down to a lower frequency. Such frequency divider circuits are commonly known as “divide-by-X” circuits, where X is a number. Most commonly, X is an integer. However, “fractional divider” circuits, in which X is not an integer, are also known. For example, divide-by-1.5 circuits are known.

High-speed data transceivers can include several frequency divider circuits that divide by several corresponding values of X. For example, transceiver can include a divide-by-2 circuit and a divide-by-4 circuit and other such divide-by-X circuits. A multiplexer can be included that selects which of the frequency divider circuits is to be utilized in response to operating conditions.

Fractional divider circuits are commonly based upon phase-locked loop (PLL) circuitry and can be somewhat complex, especially if a 50 percent duty cycle is generated. Circuit complexity can undesirably contribute to power dissipation and consume area on an integrated circuit chip.

Embodiments of the present invention relate to a divide-by-1.5 circuit that comprises a divide-by-3 circuit and a frequency doubler circuit. The divide-by-3 circuit has an input that can be coupled to a source of an input signal, i.e., the signal to be divided in frequency. The frequency doubler circuit comprises phase-locked loop circuitry and has an input coupled to an output of the divide-by-3 circuit and an output that defines the output of the divide-by-1.5 circuit.

Other systems, methods, features, and advantages will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the specification, and be protected by the accompanying claims.

The invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention.

FIG. 1 is a block diagram of a divide-by-1.5 circuit in accordance with an exemplary embodiment of the invention.

FIG. 2 is a block diagram of the divide-by-3 circuit of FIG. 1 .

FIG. 3 is a timing diagram for the divide-by-3 circuit of FIG. 2 .

FIG. 4 is a block diagram of an exemplary frequency doubler circuit of the divide-by-1.5 circuit of FIG. 1 .

FIG. 5 is a block diagram of another exemplary frequency doubler circuit of the divide-by-1.5 circuit of FIG. 1 .

FIG. 6 is a block diagram of a yet another exemplary frequency doubler circuit of the divide-by-1.5 circuit of FIG. 1 .

FIG. 7 is a block diagram of a still another exemplary frequency doubler circuit of the divide-by-1.5 circuit of FIG. 1 .

FIG. 8 is a block diagram of a further exemplary frequency doubler circuit of the divide-by-1.5 circuit of FIG. 1 .

FIG. 9 is a block diagram of a ring VCO.

As illustrated in FIG. 1 , in an illustrative or exemplary embodiment of the invention, a divide-by-1.5 circuit 100 includes a divide-by-3 circuit 102 and a phase-locked loop (PLL)-based frequency doubler circuit 104 . The output of divide-by-3 circuit 102 is coupled to the input of PLL-based frequency doubler circuit 104 . Divide-by-1.5 circuit 100 receives an input clock signal (CLK) having a frequency f and generates an output clock signal (CLK/1.5) having a frequency f/1.5 and a 50 percent duty cycle.

As illustrated in FIG. 2 , divide-by-3 circuit 102 includes a first D flip-flop 106 , a second D flip-flop 108 , a third D flip-flop 110 , a first NOR gate 112 , and a second NOR gate 114 . The clock input of first D flip-flop 106 is coupled to a circuit node 116 defining the input of divide-by-3 circuit 102 that receives the above-described input clock signal (CLK). The clock input of second D flip-flop 108 is similarly coupled to circuit node 116 . The input (D) of second D flip-flop 108 is coupled to the output (Q) of first D flip-flop 106 . The clock input of third D flip-flop 110 is inverted but similarly coupled to circuit node 116 . The input (D) of third D flip-flop 110 is coupled to the output (Q) of second D flip-flop 108 . The first input of first NOR gate 112 is coupled to the output (Q) of first D flip-flop 106 . The second input of first NOR gate 112 is coupled to the output (Q) of second D-flip-flop 108 . The output of first NOR gate 112 is coupled to the input (D) of first D flip-flop 106 . The first input of second NOR gate 114 is coupled to the output of third D flip-flop 110 . The second input of second NOR gate 114 is coupled to the output of the second D-flip-flop 108 . The output of second NOR gate 114 defines the output of divide-by-3 circuit 102 .

As illustrated by the timing diagram of FIG. 3 , the outputs of first and second flip-flops 106 and 108 define the most-significant bit (MSB) and least-significant bit (LSB), respectively, of a two-bit counter circuit that counts in response to the rising edge of the input clock signal (CLK). Third D flip-flop 110 receives the counter LSB and provides a output (FEDGE_LSB) representing the LSB in response to the falling edge of input clock signal (CLK). That is, the output of third D flip-flop 110 is the counter LSB delayed by a half clock cycle. Second NOR gate 114 combines the counter LSB with the delayed version of the LSB. Thus, the output (CLK/3) of divide-by-3 circuit 102 has a frequency of f/3 and a 50 percent duty cycle. It can be noted that divide-by-3 circuit 102 consists of relatively few elements, operates without logic glitches, and immediately enters a steady state of operation after being started up regardless of the initial states of logic elements.

As illustrated in FIG. 4 , PLL-based frequency doubler circuit 104 includes a comparison circuit 120 , a loop filter 122 , a voltage-controlled oscillator (VCO) 124 , and a loop divider circuit 126 . Comparison circuit 120 compares the input of frequency doubler circuit 104 with a feedback loop signal provided by loop divider circuit 126 . Loop divider circuit 126 receives the output of VCO 124 . The output of comparison circuit 120 is coupled to the input of loop filter 122 . The output of loop filter 122 is coupled to the input of VCO 124 . The output of VCO 124 defines the output of PLL-based frequency doubler circuit 104 .

As illustrated in FIG. 5 , PLL-based frequency doubler circuit 104 ( FIG. 4 ) can be embodied, for example, in the form of PLL-based frequency doubler circuit 104 A. PLL-based frequency doubler circuit 104 A includes a phase-frequency detector (PFD) 120 A that serves as a comparison circuit, an RC low-pass filter 122 A that serves as a loop filter, a ring VCO 124 A, and a divide-by-2 circuit 126 A that serves as a loop divider circuit. Divide-by-2 circuit 126 A can consist of a single D flip-flop. The PFD 120 A compares the input of frequency doubler circuit 104 A with a feedback loop signal provided by divide-by-2 circuit 126 A. Divide-by-2 circuit 126 A receives the output of ring VCO 124 A. The output of PFD 120 A is coupled to the input of RC low-pass filter 122 A. The output of RC low-pass filter 122 A is coupled to the input of ring VCO 124 A. In operation, the output of PFD 120 A is filtered and adjusts the VCO frequency up or down until the two inputs of PFD 120 A are in phase with each other. When the two inputs of PFD 120 A are in phase with each other, ring VCO 124 A outputs a signal having a frequency twice the frequency of the signal provided as the input of PLL-based frequency doubler circuit 104 A. The output of ring VCO 124 A defines the output of PLL-based frequency doubler circuit 104 A.

As illustrated in FIG. 6 , PLL-based frequency doubler circuit 104 ( FIG. 4 ) alternatively can be embodied, for example, in the form of PLL-based frequency doubler circuit 104 B. PLL-based frequency doubler circuit 104 B includes an exclusive-OR (XOR) gate 120 B that serves as a comparison circuit, an RC low-pass filter 122 B that serves as a loop filter, a ring VCO 124 B, and a divide-by-2 circuit 126 B that serves as a loop divider circuit. Divide-by-2 circuit 126 B can consist of a single D flip-flop. The XOR gate 120 B compares the input of frequency doubler circuit 104 B with a feedback loop signal provided by divide-by-2 circuit 126 B. Divide-by-2 circuit 126 B receives the output of ring VCO 124 B. The output of XOR 120 B is coupled to the input of RC low-pass filter 122 B. The output of RC low-pass filter 122 B is coupled to the input of ring VCO 124 B. In operation, the output of XOR gate 120 B is filtered and adjusts the VCO frequency up or down until the two inputs of XOR gate 120 B are in phase with each other. When the two inputs of XOR gate 120 B are in phase with each other, ring VCO 124 B outputs a signal having a frequency twice the frequency of the signal provided as the input of PLL-based frequency doubler circuit 104 B. The output of ring VCO 124 B defines the output of PLL-based frequency doubler circuit 104 B.

As illustrated in FIG. 7 , PLL-based frequency doubler circuit 104 ( FIG. 4 ) alternatively can be embodied, for example, in the form of PLL-based frequency doubler circuit 104 C. PLL-based frequency doubler circuit 104 C includes a pre-divide-by-two circuit 130 , a phase-frequency detector (PFD) 120 C that serves as a comparison circuit, an RC low-pass filter 122 C that serves as a loop filter, a ring VCO 124 C, and a loop divide-by-4 circuit 132 that serves as a loop divider circuit. The inclusion of pre-divide-by-two circuit 130 and loop divide-by-four circuit 132 promotes the use of economical semiconductor fabrication technologies, such as CMOS, for fabricating PFD 120 C, since such a PFD 120 C need not be operable above operating frequencies that are characteristic of such fabrication technologies. Note that PFD 120 C operates at half the frequency at which PFD 120 A ( FIG. 5 ) operates. Pre-divide-by-two circuit 130 defines the input of PLL-based frequency doubler circuit 104 C. The output of pre-divide-by-2 circuit 130 is coupled to the input of PFD 120 C. The PFD 120 C compares the output of pre-divide-by-2 circuit 130 with a feedback loop signal provided by loop divide-by-4 circuit 132 . Loop divide-by-4 circuit 132 , in turn, receives the output of ring VCO 124 C. The output of PFD 120 C is coupled to the input of RC low-pass filter 122 C. The output of RC low-pass filter 122 C is coupled to the input of ring VCO 124 C. Loop divide-by-4 circuit 132 can consist of two divide-by-2 circuits 134 and 136 in series with each other. Each of divide-by-2 circuits 130 , 134 and 136 can consist of a single D flip-flop. In operation, the output of PFD 120 C is filtered and adjusts the VCO frequency up or down until the two inputs of PFD 120 C are in phase with each other. When the two inputs of PFD 120 C are in phase with each other, ring VCO 124 C outputs a signal having a frequency twice the frequency of the signal provided as the input of PLL-based frequency doubler circuit 104 C. The output of ring VCO 124 C defines the output of PLL-based frequency doubler circuit 104 C.

As illustrated in FIG. 8 , PLL-based frequency doubler circuit 104 ( FIG. 4 ) alternatively can be embodied, for example, in the form of PLL-based frequency doubler circuit 104 D. PLL-based frequency doubler circuit 104 D includes a pre-divide-by-two circuit 138 , an XOR gate 120 D that serves as a comparison circuit, an RC low-pass filter 122 D that serves as a loop filter, a ring VCO 124 D, and a loop divide-by-4 circuit 140 that serves as a loop divider circuit. Pre-divide-by-two circuit 138 defines the input of PLL-based frequency doubler circuit 104 D. The output of pre-divide-by-2 circuit 138 is coupled to the input of XOR gate 120 D. The XOR gate 120 D compares the output of pre-divide-by-2 circuit 138 with a feedback loop signal provided by loop divide-by-4 circuit 140 . Loop divide-by-4 circuit 140 receives the output of ring VCO 124 D. The output of XOR gate 120 D is coupled to the input of RC low-pass filter 122 D. The output of RC low-pass filter 122 D is coupled to the input of ring VCO 124 D. Loop divide-by-4 circuit 140 can consist of two divide-by-2 circuits 142 and 144 in series with each other. Each of divide-by-2 circuits 138 , 142 and 144 can consist of a single D flip-flop. In operation, the output of XOR gate 120 D is filtered and adjusts the VCO frequency up or down until the two inputs of XOR gate 120 D are in phase with each other. When the two inputs of XOR gate 120 D are in phase with each other, ring VCO 124 D outputs a signal having a frequency twice the frequency of the signal provided as the input of PLL-based frequency doubler circuit 104 D. The output of ring VCO 124 D defines the output of PLL-based frequency doubler circuit 104 D.

As illustrated in FIG. 9 , any of ring VCOs 124 A- 124 D can be embodied in the form of a ring VCO 150 . Ring VCO 150 receives an input signal (CTRL) that controls the gain of two cross-coupled inverters 152 and 154 through a PFET 156 . The output of inverter 154 is coupled to the input of a buffer 158 . The output of buffer 158 defines the output of ring VCO 150 .

One or more illustrative embodiments of the invention have been described above. However, it is to be understood that the invention is defined by the appended claims and is not limited to the specific embodiments described.