Method of fabricating semiconductor device structure

1. Field of Invention

This invention is related to a semiconductor process, and particularly to a method of fabricating a semiconductor device structure.

2. Description of Related Art

MOS is a basic structure widely applied to various semiconductor devices, such as memory devices, image sensors and display devices. The traditional MOS transistor is difficult to scale down due to the limitation of the fabricating process, and strained source/drain is therefore developed. In the strained source/drain process, a single etching process is performed to form recesses beside the gate electrode, and a semiconductor compound having a lattice parameter different from that of the material of the substrate is grown in the recesses.

However, since a longer time is required to etch the thick gate dielectric layer, the gate dielectric layer under the gate electrode may be etched in the lateral direction. Therefore, an undercut is observed in the gate dielectric layer under the gate electrode. As a result, the semiconductor compound may contact with the gate electrode to cause a short circuit and the process margin can be decreased.

In view of the foregoing, this invention provides a method of fabricating a semiconductor device structure so as to prevent undercut from being formed in the gate dielectric layer under the gate electrode.

A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

In an embodiment of the invention, the treating includes performing an implant process with boron or carbon.

In an embodiment of the invention, the first etching process is performed to thin the gate dielectric layer exposed by the gate electrode

In an embodiment of the invention, a thickness of the thinned gate dielectric layer is less than 15 Å.

In an embodiment of the invention, a thickness of the thinned gate dielectric layer is ranged form 5 to 15 Å.

In an embodiment of the invention, the first etching process is performed to expose the substrate.

In an embodiment of the invention, the step of performing the first etching process includes performing a dry etching process, a wet etching process, or a combination thereof.

In an embodiment of the invention, the method further includes forming a patterned hard mask layer on the gate electrode.

In an embodiment of the invention, the patterned hard mask layer includes a multi-layer structure.

In an embodiment of the invention, the multi-layer structure includes, from bottom to top, a first hard mask layer, a second hard mask layer and a third hard mask layer.

In an embodiment of the invention, a material of the third hard mask layer is different from a material of the gate dielectric layer.

In an embodiment of the invention, the first hard mask layer, the second hard mask layer and the third hard mask layer comprise silicon nitride, silicon oxide and silicon nitride, respectively.

In an embodiment of the invention, the step of forming the gate electrode and the step of forming the patterned hard mask layer includes the following steps. A conductive layer is formed on the gate dielectric layer. A hard mask layer is formed on the conductive layer. The hard mask layer and the conductive layer are patterned to form the patterned hard mask layer and the gate electrode.

In an embodiment of the invention, the method further comprises forming a semiconductor compound in the recesses.

In an embodiment of the invention, the semiconductor compound includes SiGe or SiP.

In an embodiment of the invention, the method of forming the semiconductor compound includes an epitaxial process.

In the method of this invention, since the gate dielectric layer exposed by the gate electrode is treated before the recesses are formed in the substrate, and thus the etching rate of the treated gate dielectric layer is greater than the etching rate of the untreated gate dielectric layer. Therefore, the gate dielectric layer covered by the gate electrode can remain substantially intact without undercut during the first and second etching process. Moreover, it is easy and simple to integrate the method of the invention into the existing CMOS process, thereby achieving competitive advantages over competitors.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.

FIG. 1A to FIG. 1G are schematic cross-sectional views illustrating a method of forming a semiconductor device structure according to an embodiment of the present invention.

FIG. 1A to FIG. 1G are schematic cross-sectional views illustrating a method of forming a semiconductor device structure according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. At least one shallow trench isolation (STI) structure (not shown) is formed in the substrate 100 for providing electrical isolation.

A gate dielectric layer 102 is formed on the surface of the substrate 100 , and the gate dielectric layer 102 may include silicon oxide or silicon oxynitride, silicon nitride, or a high-k material (i.e. a dielectric material with a dielectric constant greater than 4). The high-k material can be metal oxide, such as rare earth metal oxide. The high-k material can be selected from the group consisting of hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), wherein x is between 0 and 1. The gate dielectric layer 102 can be formed by a furnace process, a deposition process such as a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process, or a spin coating process. The thickness of the gate dielectric layer 102 may range from 50 to 70 Å.

Thereafter, a conductive layer 104 is foinied over the gate dielectric layer 102 . In an embodiment, the conductive layer 104 includes a polycrystalline silicon (polysilicon) layer. The polysilicon layer can be doped or undoped. In another embodiment, the conductive layer 104 may include a work function layer and a low-resistivity metal material layer on the work function layer. For a P-type device, the work function metal layer includes titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC) or aluminum titanium nitride (TiAlN). For an N-type device, the work function metal layer includes titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl) or hafnium aluminide (HfAl). The method of forming the work function layer includes performing a radio frequency PVD (RFPVD) process. The low-resistivity metal material layer includes W, Al, Cu or an alloy thereof, or a combination thereof, and the forming method thereof includes performing a deposition process such as PVD or CVD.

A hard mask layer 106 is formed over the conductive layer 104 . The hard mask layer 106 may be a multi-layer structure. In an embodiment, the hard mask layer 106 includes, from bottom to top, a first hard mask layer 108 , a second hard mask layer 110 , and a third hard mask layer 112 . The first hard mask layer 108 and the second hard mask layer 110 include different materials, for example, silicon nitride and silicon oxide, respectively, while the second hard mask layer 110 and the third hard mask layer 112 include different materials, for example, silicon oxide and silicon nitride, respectively. In addition, the third hard mask layer 112 and the gate dielectric layer 102 include different materials, for example, silicon nitride and silicon oxide, respectively. However, the materials of the hard mask layer 106 are not limited thereto, and may include other dielectric materials such as silicon oxynitirde, silicon carbide, or other suitable dielectric material, or combinations thereof. The forming method of the hard mask layer 106 includes performing a deposition process such as PVD or CVD. The thicknesses of the first hard mask layer 108 , the second hard mask layer 110 , and the third hard mask layer 112 may range from 200 to 600 Å, from 400 to 600 Å, and from 100 to 300 Å, respectively.

Referring to FIG. 1B , the hard mask layer 106 and the conductive layer 104 may be patterned to form gate structures 116 by a lithography process and an etching process, for example. Each of the gate structures 116 includes a patterned hard mask layer 106 a and a gate electrode 104 a.

Referring to FIG. 1B , a treatment step 117 is performed to the gate dielectric layer exposed by gate dielectric layer 102 . The treatment step 117 includes performing an implant process with carbon or boron, for example. After the treatment step 117 , the etching rate of the treated gate dielectric layer 102 a exposed by the patterned hard mask layers 106 a is greater than the etching rate of the untreated gate dielectric layer 102 b covered by the patterned hard mask layers 106 a.

Referring to FIG. 1C , at least an implant process 118 is then performed to the substrate 100 so as to form S/D extension regions 120 . In an embodiment, the implant process 118 may include an N-type S/D extension implant step that forms S/D extension regions of the NMOS devices, or include an N-type S/D extension implant step and a P-type pocket implant step (the P-type pocket doped regions are not shown). In an other embodiment, the implant process 116 may include a P-type S/D extension implant step that foams S/D extension regions of the PMOS devices, or include a P-type S/D extension implant step and an N-type pocket implant step (the N-type pocket doped regions are not shown).

Referring to FIG. 1D , a first etching process is performed to remove at least a portion of the gate dielectric layer 102 a , so as to thin the gate dielectric layer 102 a and therefore form a thinned gate dielectric layer 102 c . Besides, a portion of the third hard mask layer 112 may be simultaneously removed during the first etching process. The thickness of the thinned gate dielectric layer 102 c may be less than 15 Å. In an embodiment, the thickness of the thinned gate dielectric layer 102 c may range from 5 Å to 15 Å. The first etching process may be a dry etching process, a wet etching process or a combination thereof. The dry etching process or the wet etching process has etching parameters that can be tuned such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, etchant flow rate, and other suitable parameters. For example, the recipe of the dry etching process may include an etching gas that includes CF 4 , Cl 2 or a combination thereof. The recipe of the wet etching process may include an etchant that includes diluted hydrofluoric acid (HF). In another embodiment, upon the process requirements, the first etching process may be performed to remove the entirety of the gate dielectric layer 102 a so as to expose the substrate 100 .

Since the treated gate dielectric layer 102 a has a higher etching rate than that of the untreated gate dielectric layer 102 b , the untreated gate dielectric layer 102 b remains substantially intact after the first etching process. Thus, the conventional undercut is not observed during the first etching process. In addition, the first etching process can be considered a self-aligned step by using the patterned hard mask layers 106 a as a mask.

Thereafter, referring to FIG. 1E , a spacer 122 is formed on the sidewall of each gate structure 116 and on the sidewall of the gate dielectric layer 102 b . The material of the spacer 122 is different from that of the thinned gate dielectric layer 102 c . The spacers 122 may include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. The method of forming the spacers 122 includes depositing a spacer material layer on the substrate 100 , and then performing an anisotropic etching process to the spacer material layer.

Referring to FIG. 1F , by using the spacers 122 and the gate structures 116 as a mask layer, a second etching process is performed to remove the thinned gate dielectric layer 102 c and a portion of the substrate 100 and therefore form a gate dielectric layer 102 d and to form recesses 124 in the substrate 100 beside the gate structures 116 . Besides, the third hard mask layer 112 may be simultaneously removed during the second etching process. Since the thinned gate dielectric layer 102 c thin enough, it may be easily removed during the second etching process in a short time. Thus, the conventional undercut is not found during the second etching process. Further, the gate dielectric layer 102 b is surrounded by the thinned gate dielectric layer 102 c and the etching rate of the gate dielectric layer 102 b is lower than the etching rate of the thinned gate dielectric layer 102 c , so that the gate dielectric layer 102 b is not subjected to a lateral etching during the second etching process.

Referring to FIG. 1G , a semiconductor compound 126 is formed in the recesses 124 . In an embodiment, for the PMOS devices, the semiconductor compound 126 may include SiGe, and may be formed by an epitaxial process with in-situ P-type doping. In another embodiment, for the NMOS devices, the semiconductor compound 126 may include silicon phosphorous (SiP), and may be formed by an epitaxial process with in-situ N-type doping.

Referring to FIG. 1G , the semiconductor device structure 200 of this invention includes at least one gate structure 116 disposed over the substrate 100 and a spacer 122 on the sidewall of the gate structure 116 . The gate structure 116 includes, from bottom to top, a dielectric layer 102 e , a gate electrode 104 a , and a patterned hard mask layer 106 a . In an embodiment, the dielectric layer 102 e includes a gate dielectric layer 102 d and a gate dielectric layer 102 b . The gate dielectric layer 102 b is positioned under the gate electrode 104 a , while the gate dielectric layer 102 d is positioned under the spacer 122 . The gate dielectric layer 102 b is surrounded by the gate dielectric layer 102 d , and the thickness of the gate dielectric layer 102 b is greater than the thickness of the gate dielectric layer 102 d . In other words, the dielectric layer 102 e has a reverse-T shape. The patterned hard mask layer 106 a includes the first hard mask layer 108 and the second hard mask layer 110 . The first hard mask layer 108 and the second hard mask layer 110 include different materials.

The semiconductor device structure further includes S/D extension regions 120 in the substrate 100 beside the gate structure 116 and the semiconductor compound 126 in recesses 124 in the substrate 100 adjacent to the S/D extension regions 120 .

In view of the above, the gate dielectric layer 102 b under the gate electrode 104 a is surrounded by the gate dielectric layer 102 d under the spacer 122 and no undercut is found in the gate dielectric layer 102 b . Therefore, the conventional short circuit between the semiconductor compound 126 and the gate electrode 104 a does not occur.

In summary, in the present invention, since the gate dielectric layer exposed by the gate electrode is treated before the recesses are foamed in the substrate, and thus the etching rate of the treated gate dielectric layer is greater than the etching rate of the untreated gate dielectric layer. Therefore, the gate dielectric layer covered by the gate electrode can remain substantially intact without undercut during the first etching process.

Further, in an embodiment, the gate dielectric layer covered by the gate electrode is surrounded by the gate dielectric layer under the spacer, and no undercut is found in the gate dielectric layer covered by the gate electrode. In the case that undercuts are not present in the gate dielectric layer, the conventional short circuit between the semiconductor compound and the gate electrode does not occur and the device performance is accordingly improved. In addition, it is easy and simple to integrate the method of the invention into the existing CMOS process, thereby achieving competitive advantages over competitors.

This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.