Driving method of display apparatus

This application is a Continuation of International Patent Application No. PCT/JP2012/005004, filed on Aug. 7, 2012, which claims the priority of Japanese Patent Application No. 2011-173515 filed on Aug. 9, 2011, the disclosures of which are incorporated herein by reference.

The present disclosure relates to a driving method of an active-matrix display apparatus employing a current light emitting device.

An organic EL (electroluminescence) display apparatus has a large number of arrayed self luminous organic EL devices. The EL display apparatus does not require a backlight and does not have any viewing angle restrictions. Accordingly, it has been developed as a next generation display apparatus.

The organic EL device is a current light emitting device which can control luminance in response to an amount of current flow. Methods for driving the organic EL device include a simple-matrix method and an active-matrix method. The simple-matrix method allows a pixel circuit to be made simple, but it is difficult to achieve a large-sized and high definition display. For this reason, the active-matrix organic EL display apparatus, which has driving transistors for every pixel circuit, has been mainly used in recent years.

The driving transistor and its peripheral circuit are formed generally by TFT (Thin Film Transistors) made of poly-silicon or amorphous silicon. Although TFT has the disadvantage of a high threshold voltage fluctuation due to its low mobility, the TFT is suitable for a large-sized organic EL display apparatus because large sized TFT is easy to make and the cost of TFT is low. Further, a method for overcoming the disadvantage (fluctuation of the threshold voltage) has been studied by improving a pixel circuit. For example, Japanese Patent Application Publication JP2009-169145A1 describes an organic EL display apparatus which compensates the threshold voltage of the driving transistor.

The compensation of threshold voltage is performed as follows. First, a voltage larger than the threshold voltage is applied between a gate and source of the driving transistor in order to generate a current-flow in the driving transistor and to discharge a capacitor connected between the gate and the source of the driving transistor. The current in the driving transistor stops flowing when a terminal to terminal voltage of the capacitor (i.e. voltage between two terminals of the capacitor) decreases to the threshold voltage of the driving transistor. This terminal to terminal voltage is added to an image signal and an image is thereby displayed independently of the threshold voltage of the driving transistor.

If the terminal to terminal voltage of the capacitor is much higher than the threshold voltage, the capacitor is discharged rapidly because the current flowing in the driving transistor is large. However, as the terminal to terminal voltage of capacitor decreases toward the threshold voltage, the amount of current flowing in the driving transistor decreases. As a result, the discharging speed of the capacitor becomes slow. Thus, a long time is required before the terminal to terminal voltage of capacitor falls to the threshold voltage of the driving transistor. Practically, 10-100 micro-seconds, for example, may be required.

However, according to the pixel circuit and the driving method described in JP2009-169145A1, a data line for supplying an image signal is used for compensating the threshold voltage. This limits the time available for the writing operation, and makes it difficult to achieve a large-sized or high definition display apparatus having a large numbers of pixels.

The present disclosure relates to a driving method of a display apparatus. The display apparatus has a plurality of arrayed pixel circuits. Each of the pixel circuits includes:

a current light emitting device;

a driving transistor supplying current to the current light emitting device;

a first capacitor having a first terminal connected to a gate of the driving transistor;

a second capacitor connected between a second terminal of the first capacitor and a source of the driving transistor;

a first switch applying a reference voltage to the gate of the driving transistor;

a second switch supplying an image signal voltage to a node at which the first and the second capacitors are connected;

a third switch supplying an initialization voltage to the source of the driving transistor, and

a fourth switch configured to short circuit the first capacitor.

The driving method comprises:

(a) dividing one-frame period into an initializing period, a threshold detection period, a writing period, and a luminescence period;

(b) applying, in the initializing period, a differential voltage between the reference voltage and the initializing voltage to the second capacitor by setting a second switch OFF and setting the first, third and fourth switches ON;

(c) reducing, in the threshold detection period, the voltage of the second capacitor, by closing current path including the second capacitor and the driving transistor, where the current path is closed by setting the second and third switches OFF and setting the first and fourth switches ON;

(d) applying, in the writing period, a differential voltage between the reference voltage and the image signal voltage to the first capacitor by setting the third and fourth switches OFF and setting the first and second switches ON, and

(e) applying, in the luminescence period, a current to the driving transistor and the current light emitting device corresponding to the image signal voltage by setting the first, second, third and fourth switches OFF.

The foregoing structure allows performing a writing operation at a high speed, and compensating the threshold value voltage of the driving transistor.

FIG. 1 is a block diagram illustrating a structure of a display apparatus according to one embodiment.

FIG. 2 is a circuit diagram of a pixel circuit of the display apparatus.

FIG. 3 is a timing diagram illustrating an operation of the display apparatus.

FIG. 4 is a timing diagram illustrating an operation of the pixel circuit in the display apparatus.

FIG. 5 is a circuit diagram for illustrating an operation of the pixel circuit during an initialization period.

FIG. 6 is a circuit diagram for illustrating an operation of the pixel circuit during a threshold detecting period.

FIG. 7 is a circuit diagram for illustrating an operation of the pixel circuit during a writing period.

FIG. 8 is a circuit diagram for illustrating an operation of the pixel circuit during a luminescence period.

An embodiment of a display apparatus of the present disclosure will be described with reference to the accompanying drawings. Hereafter, as an example of the display apparatus, an active-matrix organic EL display apparatus that emit light from EL devices (which is an example of current light emitting devices) using a driving transistor is described. However, the present disclosure is not limited to the organic EL display apparatus. The present disclosure may be applicable to various active-matrix display apparatus employing arrayed pixel circuits, each having a current light emitting device that controls luminance in response to an amount of current flow and a driving transistor which supplies current to the current light emitting device.

FIG. 1 is a block diagram illustrating a structure of display apparatus 10 according to this embodiment. Display apparatus 10 has a large number of arrayed (n-rows, m-column) pixel circuits 12 ( i, j ) (where, 1<=i<=n and 1<=j<=m), source driving circuit 14 , gate driving circuit 16 , and power supply circuit 18 .

Source driving circuit 14 supplies an image signal voltage Vsg (j) (j represents each of the pixel columns 1 to m, m being the highest number) to each of data lines 20 ( j ). The pixel circuits 12 ( 1 , j )- 12 ( n, j ), which are aligned in column (j) of the pixel circuit 12 , are connected commonly with the data line 20 ( j ).

Gate driving circuit 16 supplies control signals CNT 21 ( i ) to CNT 24 ( i ) (i represents each of the pixel rows 1 to n, n being the highest number) to each of control signal lines 21 ( i ) to 24 ( i ). The pixel circuits 12 ( i , 1 )- 12 ( i, m ) which are aligned in row (i) of the pixel circuit 12 , are connected commonly with the control signal lines 21 ( i )- 24 ( i ). In this embodiment, four kinds of control signals CNT 21 ( i ) to CNT 24 ( i ) are supplied to one pixel circuit 12 ( i, j ). However, the number of control signals is not limited to four.

Power supply circuit 18 supplies a high-voltage Vdd to power source lines 31 and supplies a low-voltage Vss to power source lines 32 . The lines 31 and 32 are connected to all pixel circuits 12 ( 1 , 1 ) to 12 ( n, m ). The voltages Vdd and Vss are provided so that the organic EL device, described later, can emit light. Reference voltage Vref is supplied to voltage line 33 , and initialization voltage Vint is supplied to voltage line 34 . The lines 33 and 34 are connected to all of pixel circuits 12 ( i, j ).

FIG. 2 is a circuit diagram of a pixel circuit 12 ( i, j ) of the display apparatus 10 . The pixel circuit 12 ( i, j ) has an organic EL device D 20 , (an example of current light emitting device), driving transistor Q 20 , first capacitor C 21 , second capacitor C 22 , and transistors Q 21 to Q 24 which operate as switches.

Driving transistor Q 20 supplies current to organic EL device D 20 . First capacitor C 21 stores image signal voltage Vsg which varies in response to image signal (j). Second capacitor C 22 stores threshold voltage Vth of driving transistor Q 20 . Transistor Q 21 is a switch for applying reference voltage Vref to one terminal of first capacitor C 21 . Transistor Q 22 is a switch for writing (charging) image signal voltage Vsg (j) to first capacitor C 21 . Transistor Q 23 is a switch for applying initialization voltage Vint to one terminal of second capacitor C 22 . Transistor Q 24 is a switch for short-circuiting first capacitor C 21 .

In this embodiment, all of driving transistor Q 20 and transistors Q 21 to Q 24 are N-channel TFT and enhancement type transistors. However, other types of transistors can be employed. Each of the transistors can be a P-channel TFT, or a depletion type transistor. Further, it is desirable to adopt a transistor having small leakage current in OFF state and having low ON resistance for transistors Q 21 -Q 24 which operate as switches. In this context, “ON resistance” means resistance between a drain electrode and a source electrode of a transistor when the transistor is ON.

Pixel circuit 12 ( i, j ) has a structure that driving transistor Q 20 and organic EL device D 20 are connected between power source lines 31 and 32 . That is, a drain of driving transistor Q 20 is connected to power source line 31 , a source of driving transistor Q 20 is connected to an anode of organic EL device D 20 , and a cathode of organic EL device D 20 is connected to power source line 32 .

First capacitor C 21 and second capacitor C 22 are connected in series between a gate and source of driving transistor Q 20 . That is, one terminal (first terminal) of first capacitor C 21 is connected to the gate of driving transistor Q 20 , and the other terminal (second terminal) of first capacitor C 21 is connected to one terminal of second capacitor C 22 . The other terminal of second capacitor C 22 is connected to the source of driving transistor Q 20 . Hereafter, a node to which the gate of transistor Q 20 and first capacitor C 21 are connected is called “node Tp 1 ”. A node to which first capacitor C 21 and second capacitor C 22 are connected is called “node Tp 2 ”. Anode to which second capacitor C 22 and the source of transistor Q 20 are connected is called “node Tp 3 ”.

A drain of transistor Q 21 (first switch) is connected to voltage line 33 which supplies reference voltage Vref. A source of the transistor Q 21 is connected to node Tp 1 . A gate of the transistor Q 21 is connected to control signal line 21 ( i ). Transistor Q 21 thus applies reference voltage Vref to the gate of driving transistor Q 20 . The transistor may be a P-channel TFT, instead of an N-channel TFT. When the transistor is P-channel TFT, the position of gate and source are reverse to that of N-channel TFT. The same mechanism can be applied to the transistors (Q 22 , Q 23 , Q 24 ) described below.

A drain of transistor Q 22 (second switch) is connected to node Tp 2 . A source of transistor Q 22 is connected to data line 20 ( j ) which supplies image signal voltage Vsg. A gate of transistor Q 22 is connected to control signal line 22 ( i ). Transistor Q 22 thus supplies image signal voltage Vsg to node Tp 2 of first capacitor C 21 and second capacitor C 22 .

A drain of transistor Q 23 (third switch) is connected to node Tp 3 . A source of transistor Q 23 is connected to voltage line 34 which supplies initialization voltage Vint. A gate of transistor Q 23 is connected to control signal line 23 ( i ). Transistor Q 23 thus supplies initialization voltage Vint to the source of driving transistor Q 20 .

A drain of transistor Q 24 (fourth switch) is connected to node Tp 1 . A source of transistor Q 24 is connected to node Tp 2 . A gate of transistor Q 24 is connected to control signal line 24 ( i ). Transistor Q 24 thus short-circuits first capacitor C 21 .

Control signals CNT 21 ( i ) to CNT 24 ( i ) are supplied respectively to control signal lines 21 ( i ) to 24 ( i ).

As described above, pixel circuit 12 ( i, j ) according to this embodiment has

first capacitor C 21 having a first terminal connected to a gate of driving transistor Q 20 ;

second capacitor C 22 connected between a second terminal of first capacitor C 21 and a source of driving transistor Q 20 ;

transistor Q 21 (first switch) applying reference voltage Vref to gate of driving transistor Q 20 ;

transistor Q 22 (second switch) supplying image signal voltage Vsg to node Tp 2 to which the capacitors C 21 and C 22 are connected to;

transistor Q 23 (third switch) supplying initialization voltage Vint to the source of driving transistor Q 20 , and

transistor Q 24 (fourth switch) short-circuiting first capacitor C 21 .

In this embodiment, the minimum voltage between the anode and the cathode of organic EL device D 20 is 1(V) (this minimum voltage is called Vled hereafter) when a current flows in the device D 20 . The capacity between the anode and cathode of organic EL device D 20 is 1 (pF) when a current does not flow in the device D 20 . Threshold voltage Vth of driving transistor Q 20 is about 1.5(V). The electric capacity of first capacitor C 21 and second capacitor C 22 are 0.5 (pF). Regarding the driving voltage, high-voltage Vdd is 10(V), low-voltage Vss is 0(V), reference voltage Vref is 1(V), and initialization voltage Vint is −1(V).

However, these values can be changed according to the specification of the display apparatus or characteristics of each device. Thus, the driving voltage can be optimally set according to the specification of the display apparatus or characteristic of the devices.

Next, an operation of pixel circuit 12 ( i, j ) of this embodiment is described. FIG. 3 is a timing diagram illustrating an operation of display apparatus 10 in this embodiment.

As shown in FIG. 3 , one frame period is divided into four periods (i.e. initialization period T 1 , threshold detecting period T 2 , writing period T 3 , and luminescence period T 4 ) in order to control organic EL devices D 20 in each of the pixel circuits 12 ( i,j ).

In initialization period T 1 , second capacitor C 22 is charged to a predetermined voltage.

In threshold detecting period T 2 , threshold voltage Vth of driving transistor Q 20 is detected and then threshold voltage Vth is charged to second capacitor C 22 .

In writing period T 3 , image signal voltage Vsg, corresponding to the image signal (j), is written (charged) to first capacitor C 21 .

In luminescence period T 4 , a sum of terminal to terminal voltage of first capacitor C 21 and terminal to terminal voltage of second capacitor C 22 is applied between the gate and source of driving transistor Q 20 in order to generate a current-flow in organic EL device D 20 and to emit light from the device D 20 .

Hereafter, the terminal to terminal voltage of first capacitor C 21 is referred to as voltage V 21 , and the terminal to terminal voltage of second capacitor C 22 is referred to as voltage V 22 .

The timing of these four periods are set so that the pixel circuits belonging in the same row (i), (i.e. pixel circuits 12 ( i , 1 ) to 12 ( i, m )) operates with substantially same timings. Meanwhile, the timings of writing period T 3 are set so that the period T 3 in the different rows does not overlap each other. Accordingly, while a writing operation is being performed on one pixel row, the other pixel rows can execute an operation other than the writing. Thus, driving period can be used efficiently.

FIG. 4 is a timing diagram illustrating an operation of pixel circuit 12 ( i, j ) of display apparatus 10 according to the first embodiment. In FIG. 4 , changes of the voltages in nodes Tp 1 to Tp 3 are also illustrated. The operation of pixel circuit 12 ( i, j ) is detailed hereafter for each of the divided periods.

Initialization Period T 1

FIG. 5 is a circuit diagram for illustrating an operation of pixel circuit 12 ( i, j ) during initialization period T 1 . In FIG. 5 , the transistors Q 21 to Q 24 (of FIG. 2 ) are shown by symbols of switches. The path through which current does not flow is shown in dotted line.

At time t 1 , while control signal CNT 22 ( i ) is set to low level to set transistor Q 22 OFF, control signals CNT 24 ( i ), CNT 21 ( i ), and CNT 23 ( i ) are set to high level to set transistors Q 24 , Q 21 , and Q 23 ON. Reference voltage Vref is thereby applied to node Tp 1 via transistor Q 21 , and to node Tp 2 via transistor Q 24 . Initialization voltage Vint is applied to node Tp 3 via transistor Q 23 .

Reference voltage Vref is set to a voltage lower than a sum of low-voltage Vss and voltage Vled, i.e. Vref<Vss+Vled. Accordingly, organic EL device D 20 does not emit light during initialization period T 1 because source voltage of driving transistor Q 20 is lower than voltage (Vss+Vled).

Initialization voltage Vint is set to a voltage such that the difference from reference voltage Vref is larger than threshold voltage Vth of driving transistor Q 20 , i.e. Vref−Vint>Vth. When transistors Q 21 , Q 24 and Q 23 are set to ON, voltage Vref is applied to first terminal, and voltage Vint is applied to second terminal of second capacitor C 22 . That is, voltage (Vref−Vint) is charged to second capacitor C 22 . Accordingly, the voltage (Vref−Vint) is applied between the gate and source of driving transistor Q 20 . Since the voltage (Vref−Vint) is higher than threshold voltage Vth of driving transistor Q 20 , a current is supplied from the power supply of high-voltage Vdd to the power supply of initialization voltage Vint via driving transistor Q 20 and transistor Q 23 .

In this embodiment, initialization period T 1 is set to 1 micro second.

Threshold Detection Period T 2

FIG. 6 is a circuit diagram for illustrating an operation of pixel circuit 12 ( i, j ) during threshold detection period T 2 .

At time t 2 , control signal CNT 23 ( i ) is set to low level to set transistor Q 23 OFF. At this point, the current flows continuously in driving transistor Q 20 because voltage V 22 , which is larger than threshold voltage Vth of driving transistor Q 20 , is applied between the gate and source of driving transistor Q 20 . Due to this current, second capacitor C 22 is discharged and voltage V 22 starts decreasing.

While voltage V 22 is higher than threshold voltage Vth, current keeps flowing in transistor Q 20 although the amount of the current continues to decrease. Voltage V 22 thereby decreases gradually to threshold voltage Vth. When voltage V 22 falls to threshold voltage Vth, the current in driving transistor Q 20 stops flowing and the voltage V 22 also stops decreasing.

The current flowing in driving transistor Q 20 decreases as voltage V 22 decreases because driving transistor Q 20 operates as a current source which is controlled by the voltage applied between the gate and source of driving transistor Q 20 . As a result, a long time is required before voltage V 22 falls to threshold voltage Vth. Moreover, the longtime requirement is further caused because the large electric capacity of organic EL device D 20 is added to the electric capacity of second capacitor C 22 . Practically, this takes 10 to 100 times longer than the case of discharging the capacitor by transistor-switching. For this reason, threshold detection period T 2 is set to 10 micro seconds in this embodiment.

Writing Period T 3

FIG. 7 is a circuit diagram for illustrating an operation of pixel circuit 12 ( i, j ) during writing period T 3 .

At time t 3 , image signal voltage Vsg (j) corresponding to the image signal, which is to be displayed, is supplied to data line 20 ( j ). However, as shown in FIG. 4 , a substantial time is required before the voltage Vsg (j) being stable because data line 20 ( j ) has a rather large equivalent capacity and data line 20 ( j ) itself has a substantial amount of impedance.

At time t 4 , where image signal voltage Vsg (j) becomes stable, control signal CNT 24 ( i ) is set to low level to set transistor Q 24 OFF. Then control signal CNT 22 ( i ) is set to high level to set transistor Q 22 ON. As a result, the voltage of node Tp 2 turns to image signal voltage Vsg (j), and the voltage (Vref−Vsg) is charged between two terminals of first capacitor C 21 . Hereafter, this voltage (Vref−Vsg) is indicated as image signal voltage Vsg′.

At this point, voltage (Vsg′+Vth) is applied between the gate and source of driving transistor Q 20 . This voltage is equivalent to a sum of the voltages charged in the first capacitor C 21 and the second capacitor C 22 (i.e. image signal voltage Vsg′ is charged to the capacitor C 21 ; and threshold voltage Vth is charged to the capacitor C 22 ). While image signal voltage Vsg′ is larger than zero, current flows in driving transistor Q 20 because the voltage applied between the gate and source of driving transistor Q 20 is higher than threshold voltage Vth of the transistor Q 20 . Due to this current, voltage V 22 decreases.

In this embodiment, writing period T 3 is set to 2 micro seconds. Assuming that time before image signal voltage Vsg (j) being stable is 1 micro second, the time for charging first capacitor C 21 (by setting transistor Q 22 ON) is set to 1 micro second. Since the time when transistor Q 22 stays ON is set short, voltage V 22 decreases a little during this period T 3 .

Luminescence Period T 4

FIG. 8 is a circuit diagram for illustrating an operation of pixel circuit 12 ( i, j ) during luminescence period T 4 .

At time t 5 , control signal CNT 22 ( i ) is set to low level to set transistor Q 22 OFF. Control signal CNT 21 ( i ) is set to low level to set transistor Q 21 OFF. Consequently, nodes Tp 1 to Tp 3 temporarily enter a floating state and voltage (Vsg′+Vth), that is larger than threshold voltage Vth, is applied between the gate and source of driving transistor Q 20 . Accordingly, a current corresponding to the voltage applied between the gate and source of driving transistor Q 20 is supplied to organic EL device D 20 .

At this point, current (I) satisfies

I=K *( VGS−Vth )= K*Vsg′

where,

VGS: voltage applied between the gate and source of the transistor Q 20 , K: a constant value.

This equation is free from threshold voltage Vth.

As discussed above, current flowing in organic EL device D 20 is not influenced by threshold voltage Vth. Therefore, the current flowing in the device D 20 is free from being affected by dispersion of threshold voltage Vth of driving transistor Q 20 . Even when threshold voltage Vth changes with the time, organic EL device D 20 can emit a light with luminosity corresponding to the image signal.

After luminescence period T 4 , a non-light emitting period can be provided. This period can be achieved by setting one of the transistors Q 24 , Q 21 , and Q 23 ON.

During threshold detection period T 2 , it is desirable to set transistor Q 24 ON. However, if the leakage current of first capacitor C 21 is negligible, transistor Q 24 can be set to OFF. In this case, control signals CNT 24 ( i ) and CNT 23 ( i ) can be shared because transistors Q 23 and Q 24 can be controlled by the same signal throughout these four period.

As described above, one-frame period is divided into initialization period T 1 , threshold detecting period T 2 , writing period T 3 , and luminescence period T 4 in this embodiment.

In initialization period T 1 , transistor Q 22 (second switch) is set to OFF, while transistors Q 21 (first switch), Q 23 (third switch), and Q 24 (fourth switch) are set to ON. The voltage (Vref−Vint) is thereby applied to second capacitor C 22 .

Next, in threshold detecting period T 2 , transistors Q 22 (second switch) and Q 23 (third switch) are set to OFF, while transistors Q 21 (first switch) and Q 24 (fourth switch) ON are set to ON. A closed-circuit including second capacitor C 22 and driving transistor Q 20 is thereby formed, and the current in transistor Q 22 is decreased.

In subsequent writing period T 3 , transistors Q 23 and Q 24 are set to OFF, while transistors Q 21 and Q 22 are set to ON. Voltage (Vref−Vsg) is thereby applied to first capacitor C 21 .

Then in luminescence period T 4 , transistors Q 21 , Q 22 , Q 23 and Q 24 are set to OFF. The current corresponding to the image signal voltage Vsg is thereby supplied to organic EL device D 20 (current light emitting device) and driving transistor Q 20 . The device D 20 thus emits light for displaying an image.

As described above, the driving method of the display apparatus according to this embodiment allows the threshold voltage of the driving transistor to be detected independently of image signal voltage Vsg (j). Writing period T 3 can be thereby shortened, as long as the writing period T 3 is larger than a sum of a time needed for determining image signal voltage Vsg (j) and a time needed for charging first capacitor C 21 (by turning transistor Q 22 ON).

This embodiment allows high speed writing, and thereby achieves a display apparatus that has a large number of pixels and high definition.

In the embodiment, each of the numerical values, e.g. voltage is an exemplary value, and these values are preferably set according to the characteristics of organic EL device or the display apparatus.

The present disclosure is useful as a driving method for an active-matrix display device employing a current light emitting device.