Multi-chip semiconductor device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-208586, filed on Sep. 21, 2012, the entire contents of which are incorporated herein by reference.

1. Technical Field

The disclosure relates to a multi-chip semiconductor device which is configured to connect semiconductor chips having individual functions to each other.

2. Related Art

In related art, a multi-chip semiconductor device having a plurality of functions is manufactured by connecting semiconductor chips having individual functions to each other.

Techniques for manufacturing such a multi-chip semiconductor device are known. In one technique, a groove is formed on an electrode forming surface of one semiconductor chip constituting the multi-chip semiconductor device and another semiconductor chip is inserted into the groove. With this structure, the two semiconductor chips are connected so as to be vertical to each other with good alignment accuracy, and heat dissipation efficiency of the multi-chip semiconductor device can be improved (see Japanese Patent Application Laid-open No. 2002-76244, for example).

In some embodiments, a multi-chip semiconductor device, includes a first semiconductor chip that is plate-shaped and includes a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a second semiconductor chip that is plate-shaped and includes a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first connection portion and the second connection portion includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces. The first connection portion and the second connection portion are connected to each other such that the first main surface of the first semiconductor chip and the second main surface of the second semiconductor chip are vertical to each other.

The above and other features, advantages and technical and industrial significance of this invention will be better understood by reading the following detailed description of presently preferred embodiments of the invention, when considered in connection with the accompanying drawings.

FIG. 1 is a cross-sectional view of a multi-chip semiconductor device according to a first embodiment of the invention;

FIG. 2 is a cross-sectional view of a multi-chip semiconductor device according to a second embodiment of the invention;

FIG. 3 is a perspective view of a second semiconductor chip illustrated in FIG. 2 ;

FIG. 4 is a cross-sectional view of a multi-chip semiconductor device according to a first modified example of the second embodiment;

FIG. 5 is a cross-sectional view of a multi-chip semiconductor device according to a second modified example of the second embodiment;

FIG. 6 is a cross-sectional view of a multi-chip semiconductor device according to a third embodiment of the invention; and

FIG. 7 is a cross-sectional view of a multi-chip semiconductor device according to a modified example of the third embodiment.

Exemplary embodiments will be described below with reference to accompanying drawings. The invention is not limited to these embodiments. In addition, the same components are denoted by the same symbols in the description of the drawings. It is noted that the drawings are merely schematic and a relation between a thickness and a width of each member and a ratio of each member are different from actual ones. Even drawings seem to be mutually related, the components having different dimensional relation and ratio may be included.

First Embodiment

FIG. 1 is a cross-sectional view of a multi-chip semiconductor device 100 according to a first embodiment of the invention. In the multi-chip semiconductor device 100 , a second connection portion 4 , which is formed on a side surface of a second semiconductor chip 2 , is fitted into and connected to a groove-shaped first connection portion 3 formed on a first semiconductor chip 1 .

The first semiconductor chip 1 is plate-shaped and includes the groove-shaped first connection portion 3 formed on a main surface “a” of the first semiconductor chip 1 . The first connection portion 3 includes a first inclined surface 5 and a second inclined surface 6 which are inclined with respect to the main surface “a” of the first semiconductor chip 1 , and a bottom surface 7 parallel to the main surface “a” of the first semiconductor chip 1 . In addition, a plurality of first semiconductor chip electrodes 8 are formed on the first connection portion 3 at a specified interval such that the first semiconductor chip electrodes 8 are insulated by an insulation member.

The second semiconductor chip 2 is plate-shaped and includes the second connection portion 4 which is formed on a side surface vertical to a main surface “b” of the second semiconductor chip 2 . The second connection portion 4 includes a third inclined surface 9 and a fourth inclined surface 10 which are inclined with respect to the main surface “b” of the second semiconductor chip 2 , and a bottom surface 11 vertical to the main surface “b” of the second semiconductor chip 2 . Second semiconductor chip electrodes 12 , which are the same in number as the first semiconductor chip electrodes 8 , are formed on the second connection portion 4 at a specified interval along a direction vertical to the drawings such that the second semiconductor chip electrodes 12 are insulated by an insulation member.

In the multi-chip semiconductor device 100 , the second connection portion 4 is fitted into and connected to the first connection portion 3 such that the main surface “a” of the first semiconductor chip 1 and the main surface “b” of the second semiconductor chip 2 are vertical to each other. In this specification, the state in which the main surface “a” of the first semiconductor chip 1 and the main surface “b” of the second semiconductor chip 2 are vertical to each other indicates that an angle (θ) between the main surface “a” and the main surface “b” satisfies 80°<θ<110°. Preferably, the angle (θ) between the first semiconductor chip 1 and the second semiconductor chip 2 is 90°. The first connection portion 3 and the second connection portion 4 are connected to each other by a conductive member such as solder. Thus, the first semiconductor chip electrodes 8 and the second semiconductor chip electrodes 12 are electrically connected to each other.

Preferably, a periphery of a connection between the first connection portion 3 and the second connection portion 4 is reinforced by a reinforcement member 13 . The reinforcement member 13 is made of a reinforced resin and the like. Since the periphery of the connection is reinforced by the reinforcement member 13 , a mechanical strength of the multi-chip semiconductor device 100 can be improved.

In the multi-chip semiconductor device 100 according to the first embodiment, the first semiconductor chip 1 and the second semiconductor chip 2 are connected to each other through the first connection portion 3 and the second connection portion 4 which include the inclined surfaces. With this structure, an electrical connection area can be increased, resistance value of the connection portions can be lowered, and thus the effect on a transmission signal can be reduced. In the multi-chip semiconductor device 100 , furthermore, since each of the first connection portion 3 and the second connection portion 4 has a tapered shape, it is possible to reduce stress concentration and thus prevent damage to the semiconductor chips when an external force is exerted on the connection portions. Moreover, since the first semiconductor chip 1 and the second semiconductor chip 2 are connected to each other such that the second connection portion 4 is fitted into the groove-shaped first connection portion 3 , alignment can be easily achieved and also accuracy can be improved.

Second Embodiment

FIG. 2 is a cross-sectional view of a multi-chip semiconductor device 100 A according to a second embodiment of the invention. FIG. 3 is a perspective view of a second semiconductor chip illustrated in FIG. 2 . In the multi-chip semiconductor device 100 A according to the second embodiment, a first semiconductor chip 1 A and a second semiconductor chip 2 A are connected to each other on side surfaces of the first semiconductor chip 1 A and the second semiconductor chip 2 A.

The first semiconductor chip 1 A is plate-shaped and includes a first connection portion 3 A in which first semiconductor chip electrodes 8 A are formed on the side surface vertical to a main surface “a”. The first connection portion 3 A includes an inclined surface 14 which is inclined with respect to the main surface “a” of the first semiconductor chip 1 A and a vertical surface 15 which is vertical to the main surface “a” of the first semiconductor chip 1 A. The first semiconductor chip electrodes 8 A, which are the same in number as second semiconductor chip electrodes to be described below, are formed on the inclined surface 14 at a specified interval such that the plurality of first semiconductor chip electrodes 8 A are insulated by an insulation member.

The second semiconductor chip 2 A is plate-shaped and includes a second connection portion 4 A in which second semiconductor chip electrodes 12 A are formed on the side surface which is vertical to a main surface “b”, as illustrated in FIG. 3 . The second connection portion 4 A includes an inclined surface 16 which is inclined with respect to the main surface “b” of the second semiconductor chip 2 A and a vertical surface 17 which is vertical to the main surface “b” of the second semiconductor chip 2 A. In FIG. 3 , as an example, four second semiconductor chip electrodes 12 A are formed on the inclined surface 16 at a specified interval, but the invention is not limited thereto. The plurality of second semiconductor chip electrodes 12 A are insulated by an insulation member 19 .

In the multi-chip semiconductor device 100 A according to the second embodiment, the inclined surface 14 inclined with respect to the main surface “a” of the first semiconductor chip 1 A and the inclined surface 16 inclined with respect to the main surface “b” of the second semiconductor chip 2 A are connected so as to face each other, and thus the main surface “a” of the first semiconductor chip 1 A and the main surface “b” of the second semiconductor chip 2 A are vertical to each other. The inclined surface 14 and the inclined surface 16 are connected by a conductive member such as solder, and thus the first semiconductor chip electrodes 8 A and the second semiconductor chip electrodes 12 A are electrically connected to each other.

The multi-chip semiconductor device 100 A includes a reinforcement-member filling space 18 which is a space enclosed by the vertical surface 15 vertical to the main surface “a” of the first semiconductor chip 1 A and the vertical surface 17 vertical to the main surface “b” of the second semiconductor chip 2 A. The mechanical strength of the multi-chip semiconductor device 100 A can be improved by the reinforcement member 13 filled in the reinforcement-member filling space 18 and by reinforcing the other side of a connection surface between the first semiconductor chip 1 A and the second semiconductor chip 2 A with the reinforcement member 13 . Furthermore, as the reinforcement member 13 , the reinforced resin can be used, for example, and the conductive member such as solder can also be used.

The mechanical strength of the multi-chip semiconductor device 100 A can be improved by the reinforcement-member filling space 18 provided in the multi-chip semiconductor device 100 A. Moreover, since the reinforcement-member filling space 18 is formed in the space enclosed by the vertical surface 15 and the vertical surface 17 , it is possible to reduce a height H of the multi-chip semiconductor device 100 A.

According to the multi-chip semiconductor device 100 A of the second embodiment, since the semiconductor chips are connected to each other through a connection surface inclined with respect to the main surface of each semiconductor chip, the electrical connection area can be increased, the resistance value of the connection portions can be lowered, and thus the effect on the transmission signal can be reduced. In the multi-chip semiconductor device 100 A, furthermore, the reinforcement member 13 is filled in the reinforcement-member filling space 18 , and thus it is possible to improve the connection strength while suppressing an increase in size.

As a first modified example of the second embodiment, an exemplary multi-chip semiconductor device is illustrated in FIG. 4 . In a multi-chip semiconductor device 100 B, as the reinforcement member 13 which is filled in the reinforcement-member filling space 18 , the conductive member is used. First semiconductor chip electrodes 8 B are formed on an inclined surface 14 B and a vertical surface 15 B, and second semiconductor chip electrodes 12 B are formed on an inclined surface 16 B and a vertical surface 17 B. With this structure, the electrical connection area of the multi-chip semiconductor device 100 B can be increased more than that of the multi-chip semiconductor device 100 A according to the second embodiment. Thus, the resistance of the connection portions can be further reduced.

If reduction in size is unnecessary, a multi-chip semiconductor device illustrated in FIG. 5 can be used. In a multi-chip semiconductor device 100 C illustrated in FIG. 5 , a first connection portion 3 C including only an inclined surface 14 C and a second connection portion 4 C including only an inclined surface 16 C are connected to each other. According to the multi-chip semiconductor device 100 C, the semiconductor chips are connected to each other such that the inclined surface 14 C and the inclined surface 16 C, which are inclined with respect to the main surfaces of the respective semiconductor chip, face each other, as with the multi-chip semiconductor device 100 A according to the second embodiment. With this structure, the electrical connection area of the multi-chip semiconductor device 100 C can be increased, the resistance value of the connection portions can be lowered, and thus the effect on the transmission signal can be reduced.

Third Embodiment

FIG. 6 is a cross-sectional view of a multi-chip semiconductor device 100 D according to a third embodiment of the invention. In the multi-chip semiconductor device 100 D according to the third embodiment, a first semiconductor chip 1 D and a second semiconductor chip 2 D are connected to each other on side surfaces of the first semiconductor chip 1 D and the second semiconductor chip 2 D.

The first semiconductor chip 1 D is plate-shaped and includes a first connection portion 3 D in which first semiconductor chip electrodes 8 D are formed on the side surface which is vertical to a main surface “a”. The first connection portion 3 D includes an inclined surface 14 D inclined with respect to the main surface “a” of the first semiconductor chip 1 D and a parallel surface 20 parallel to the main surface “a” of the first semiconductor chip 1 D. The first semiconductor chip electrodes 8 D are formed on the inclined surface 14 D and the parallel surface 20 at a specified interval such that each of the first semiconductor chip electrodes 8 D is insulated by the insulation member.

The second semiconductor chip 2 D is plate-shaped and includes a second connection portion 4 D in which second semiconductor chip electrodes 12 D are formed on the side surface which is vertical to a main surface “b”. The second connection portion 4 D includes an inclined surface 16 D inclined with respect to the main surface “b” of the second semiconductor chip 2 D and a vertical surface 17 D vertical to the main surface “b” of the second semiconductor chip 2 D. The second semiconductor chip electrodes 12 D, which are the same in number as the first semiconductor chip electrodes 8 D, are formed on the inclined surface 16 D and the vertical surface 17 D at a specified interval such that the second semiconductor chip electrodes 12 D are insulated by an insulation member.

The first connection portion 3 D can be formed by etching. For example, if the first connection portion 3 D including the parallel surface 20 and the inclined surface 14 D is formed by the etching in the first semiconductor chip 1 D made of silicon, the inclined surface 14 D having a specified inclined angle can be formed because etching rates vary depending on directions of crystal plane.

In the multi-chip semiconductor device 100 D according to the third embodiment, the parallel surface 20 parallel to the main surface “a” of the first semiconductor chip 1 D and the vertical surface 17 D vertical to the main surface “b” of the second semiconductor chip 2 D are connected so as to face each other, and thus the main surface “a” of the first semiconductor chip 1 D and the main surface “b” of the second semiconductor chip 2 D are vertical to each other. The parallel surface 20 and the vertical surface 17 D are connected by the conductive member such as solder.

The multi-chip semiconductor device 100 D includes a reinforcement-member filling space 18 D which is a space mainly enclosed by the inclined surface 14 D inclined with respect to the main surface “a” of the first semiconductor chip 1 D and the inclined surface 16 D inclined with respect to the main surface “b” of the second semiconductor chip 2 D. By filling the conductive member as the reinforcement member 13 in the reinforcement-member filling space 18 D, the mechanical strength of the multi-chip semiconductor device 100 D can be improved, the connection area between the first semiconductor chip electrodes 8 D and the second semiconductor chip electrodes 12 D can be increased, the resistance value of the connection portions can be lowered, and thus the effect on the transmission signal can be reduced.

According to the multi-chip semiconductor device 100 D of the third embodiment, the semiconductor chips are connected such that the parallel surface 20 and the vertical surface 17 D face each other, and the conductive member is filled in the reinforcement-member filling space 18 D. With this structure, the mechanical strength of the multi-chip semiconductor device 100 D can be improved, and the resistance of the connection portions can be lowered.

As a modified example of the third embodiment, an exemplary multi-chip semiconductor device 100 E is illustrated in FIG. 7 . In the multi-chip semiconductor device 100 E, by adjusting a length ratio between an inclined surface 14 E and a parallel surface 20 E and a length ratio between an inclined surface 16 E and a vertical surface 17 E, a space which is not connected to the parallel surface 20 E is formed on the vertical surface 17 E. The reinforcement member 13 can be filled in the above-described space, thereby improving the mechanical strength of the multi-chip semiconductor device 100 E and also mounting other chips.

In some embodiments, the above-described multi-chip semiconductor devices are useful in an imaging module such as a digital camera, a digital video camera, a mobile phone having an imaging function, or an endoscope system for observing internal organs of a subject.

According to some embodiments, it is possible to easily achieve position adjustment with high accuracy and to reduce deterioration of transmission signal through the connection portions having the connection surfaces inclined with respect to the main surfaces of the semiconductor chips.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

1 , 1 A, 1 B, 10 , 1 D, 1 E first semiconductor chip

2 , 2 A, 2 B, 2 C, 2 D, 2 E second semiconductor chip

3 , 3 A, 3 B, 3 C, 3 D, 3 E first connection portion

4 , 4 A, 4 B, 4 C, 4 D, 4 E second connection portion

5 first inclined surface

6 second inclined surface

7 , 11 bottom surface

8 , 8 A, 8 B, 8 C, 8 D, 8 E first semiconductor chip electrode

9 third inclined surface

10 fourth inclined surface

12 , 12 A, 12 B, 12 C, 12 D, 12 E second semiconductor chip electrode

13 reinforcement member

14 , 14 B, 14 C, 14 D, 14 E, 16 , 16 B, 16 C, 16 D, 16 E inclined surface

15 , 15 B, 17 , 17 B, 17 D, 17 E vertical surface

18 , 18 D reinforcement-member filling space insulation member

20 , 20 E parallel surface

100 , 100 A, 100 B, 100 C, 100 D, 100 E multi-chip semiconductor device