Crystal-less clock generator and operation method thereof

This application claims the priority benefit of Taiwan application serial no. 102120125, filed on Jun. 6, 2013. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The technical field relates to a crystal-less clock generator (CLCG) and an operation method thereof.

Along with the development of electronic systems, the sizes of different electronic elements have been constantly reduced, and the number of transistors per unit area in a chip has been increased accordingly. Modularizing all circuits in a product and integrating the functions of these modules into a single chip is one of the trends in the future development of electronic systems. Clock signal perform synchronization in various electronic systems. In a portable electronic device or an electronic biomedical product, a clock source with low power consumption and small surface area may extend the lifespan of the product. Presently, a clock signal is usually generated using a crystal oscillator, micro electro mechanical systems (MEMS), or through a CMOS process. The frequency of a crystal oscillator or MEMS is stable at different temperatures and voltages. As to the circuit system structure, an oscillating circuit realized through a CMOS process possesses integration superiority over oscillating circuits realized through other techniques.

Existing CMOS oscillators come in three types of main structures. The first type of main structure adopts a LC oscillator for high-frequency system operations. The second type of main structure adopts a relaxation oscillator, in which the frequency oscillation is controlled by charging/discharging loads including at least a resistor and/or at least a capacitor. The third type of main structure is an all-digital oscillating structure, in which a digital signal processor and a clock generator are integrated into a single chip so that the system area is effectively reduced. Because the frequency stability of a CMOS circuit is sensitive to temperature, how to respond to an environmental variation in a CMOS structure is a subject to be resolved.

Accordingly, the present disclosure is directed to a crystal-less clock generator (CLCG) and an operation method thereof, in which an output frequency is automatically calibrated.

The present disclosure provides a CLCG including a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

The present disclosure provides an operation method of a CLCG. The operation method includes following steps. An output clock signal of the CLCG is generated by a first oscillation circuit according to a control signal. A reference clock signal is generated by a second oscillation circuit. The control signal is generated for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

Several exemplary embodiments accompanied with figures are described in detail below to further describe the disclosure in details.

The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, explain the principles of the disclosure.

FIG. 1 is a circuit block diagram of a crystal-less clock generator (CLCG) according to an embodiment of the present disclosure.

FIG. 2 is a flowchart of an operation method of a CLCG according to an embodiment of the present disclosure.

FIG. 3 is a circuit block diagram of a first oscillation circuit in FIG. 1 according to an embodiment of the present disclosure.

FIG. 4 is a circuit block diagram of a main loop inverter in FIG. 3 according to an embodiment of the present disclosure.

FIG. 5 is a circuit block diagram of the first oscillation circuit in FIG. 1 according to another embodiment of the present disclosure.

FIG. 6 is a circuit block diagram of the first oscillation circuit in FIG. 1 according to yet another embodiment of the present disclosure.

FIG. 7 is a circuit diagram of a varactor according to an embodiment of the present disclosure.

FIG. 8 is a flowchart of an operation method of a CLCG according to another embodiment of the present disclosure.

FIG. 9 is a circuit block diagram of a CLCG according to an embodiment of the present disclosure.

FIG. 10 is a flowchart of an operation method of a CLCG according to yet another embodiment of the present disclosure.

FIG. 11 is a circuit block diagram of a time-to-digital converter according to an embodiment of the present disclosure.

FIG. 12 is a signal timing diagram of the time-to-digital converter in FIG. 11 according to an embodiment of the present disclosure.

FIG. 13 is an input/output comparison diagram of the time-to-digital converter in FIG. 11 according to an embodiment of the present disclosure.

FIG. 14 is a circuit block diagram of a CLCG according to an embodiment of the present disclosure.

FIG. 15 is a flowchart of an operation method of a CLCG according to still another embodiment of the present disclosure.

FIG. 16 is a circuit block diagram of a first time amplifier (TA) in FIG. 14 according to an embodiment of the present disclosure.

FIG. 17 is a diagram illustrating the temperature-frequency relationship in the CLCG in FIG. 14 according to an embodiment of the present disclosure.

FIG. 18 is a circuit block diagram of a CLCG according to an embodiment of the present disclosure.

FIG. 19 is a circuit block diagram of a CLCG according to an embodiment of the present disclosure.

FIG. 20 is a circuit block diagram of a compensator in FIG. 19 according to an embodiment of the present disclosure.

FIG. 21 is a circuit block diagram of a digital filter in FIG. 19 according to an embodiment of the present disclosure.

FIG. 22 is a graph illustrating the temperature-output frequency relationship in the CLCG in FIG. 19 according to an embodiment of the present disclosure.

FIG. 23 is a circuit block diagram of a CLCG according to an embodiment of the present disclosure.

The term “couple” used throughout the present disclosure (including the claims) can refer to any direct or indirect connection. For example, if a first device is described as being coupled to a second device, the first device can be directly connected to the second device or indirectly connected to the second device through any other device or any connection technique. In addition, wherever possible, same or similar devices/elements/steps are referred to with same reference numerals throughout the present disclosure and accompanying drawings. Devices/elements/steps with the same reference numerals or terms in different embodiments can be referred to each other.

FIG. 1 is a circuit block diagram of a crystal-less clock generator (CLCG) 100 according to an embodiment of the present disclosure. The CLCG 100 can be implemented in an all-digital manner. The CLCG 100 can operate at a high speed with a low voltage supply (for example, 0.5 V), and the CLCG 100 offers a compensation function for environmental variations. The CLCG 100 can be applied to any electronic system, such as a printer, a photocopier, a liquid crystal screen, a CD-ROM, a radio frequency (RF) related transceiving circuit, a digital biomedical chip integrated system, or any other portable electronic device.

FIG. 2 is a flowchart of an operation method of a CLCG according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 2 , the CLCG 100 includes a first oscillation circuit 110 , a second oscillation circuit 120 , and a control circuit 130 . The first oscillation circuit 110 is controlled by a control signal Sc, and in step S 210 , the first oscillation circuit 110 generates an output clock signal CLK of the CLCG 100 according to the control signal Sc. The output clock signal CLK can be a single-phase clock signal or a multi-phase clock signal. A multi-phase clock signal can be applied broadly, such as being provided to a clock and data recovery (CDR) circuit in high-speed serial data transmission or being used for clock synthesis in a frequency multiplication application.

The first oscillation circuit 110 includes a digital controlled oscillator (DCO) or any other controllable oscillation circuit. FIG. 3 is a circuit block diagram of the first oscillation circuit 110 in FIG. 1 according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 3 , the first oscillation circuit 110 includes a main loop. The main loop includes N main loop inverters MLI 1 , MLI 2 , . . . , and MLI N that are serially connected with each other, wherein N is an integer. As shown in FIG. 3 , the input terminal of the main loop inverter MLI 1 is coupled to the output terminal of the main loop inverter MLI N , and the input terminal of the main loop inverter MLI i is coupled to the output terminal of the main loop inverter MLI i−1 , wherein i is an integer between 1 and N. At least one (or multiple) of the main loop inverters MLI 1 -MLI N is controlled by the control signal Sc. For example, the control signal Sc controls the delay time or driving current of the main loop inverter MLI 1 and/or other main loop inverters. The output terminal of one (or more) of the main loop inverters MLI 1 -MLI N generates a single clock signal (or multiple clock signals having different phases) as the output clock signal CLK of the CLCG 100 . Thus, the first oscillation circuit 110 can generate a single-phase or a multi-phase output clock signal CLK, and can adjust the frequency of the output clock signal CLK according to the control signal Sc.

In the present embodiment, these main loop inverters MLI 1 -MLI N can be implemented through any technique. Taking the main loop inverter MLI 1 as an example, FIG. 4 is a circuit block diagram of the main loop inverter MLI 1 in FIG. 3 according to an embodiment of the present disclosure, and the rest main loop inverters can be implemented by referring to descriptions related to the main loop inverter MLI 1 . Referring to FIG. 4 , the main loop inverter MLI 1 includes a first inverter 410 and a plurality of second inverters. Herein five second inverters 420 _ 1 , 420 _ 2 , . . . , and 420 _ 5 are taken as examples, but the number of the second inverters is not limited in other embodiments. The sizes of the second inverters 420 _ 1 - 420 _ 5 are different from each other. For example, the size of the second inverter 420 _ 2 is twice that of the second inverter 420 _ 1 , and the size of the second inverter 420 _ 5 is 16 times of that of the second inverter 420 _ 1 . The driving current of an inverter increases with the size of the inverter.

The first inverter 410 and the second inverters 420 _ 1 - 420 _ 5 are connected with each other in parallel, as shown in FIG. 4 . The second inverters 420 _ 1 - 420 _ 5 may be tri-invs. In the present embodiment, the control signal Sc includes bits C<0>, C<1>, . . . , and C<4>. These bits C<0>-C<4> respectively determine the operation states of the second inverters 420 _ 1 - 420 _ 5 . The bits C<0>-C<4> of the control signal Sc are used for controlling the on/off of the tri-invs. For example, when the bit C<0> is logic 0, the second inverter 420 _ 1 is disabled, and when the bit C<0> is logic 1, the second inverter 420 _ 1 is enabled. Larger value of the control signal Sc results in larger driving currents of the second inverters 420 _ 1 - 420 _ 5 . In other words, larger value of the control signal Sc results in larger the equivalent size of the main loop inverter MLI 1 , and accordingly the output driving current increase. Thus, the control signal Sc can determine the driving current of the main loop inverter MLI 1 . When the driving currents of the main loop inverters increase, the output frequency of the first oscillation circuit 110 in FIG. 3 increases accordingly.

FIG. 5 is a circuit block diagram of the first oscillation circuit 110 in FIG. 1 according to another embodiment of the present disclosure. The embodiment illustrated in FIG. 5 can be referred to descriptions related to FIG. 3 . Referring to FIG. 1 and FIG. 5 , besides the main loop inverters MLI 1 -MLI N , the first oscillation circuit 110 further includes at least one secondary loop inverter, such as the secondary loop inverter SLI 1 in FIG. 5 . The secondary loop inverter SLI 1 can be implemented with any technique. In the present embodiment, the implementation of the secondary loop inverter SLI 1 can be referred to descriptions related to FIG. 4 . The secondary loop inverter SLI 1 may be controlled by the control signal Sc to adjust the output frequency of the first oscillation circuit 110 .

The input terminal of the secondary loop inverter SLI 1 is coupled to the output terminal of the main loop inverter MLI 2 , and the output terminal of the secondary loop inverter SLI 1 is coupled to the input terminal of the main loop inverter MLI 1 , as shown in FIG. 5 . The output terminal of the main loop inverter MLI 1 is coupled to the input terminal of the main loop inverter MLI 2 . Thus, the serially connected main loop inverter MLI 1 , main loop inverter MLI 2 , and secondary loop inverter SLI 1 constitute a secondary loop.

FIG. 6 is a circuit block diagram of the first oscillation circuit 110 in FIG. 1 according to yet another embodiment of the present disclosure. The embodiment illustrated in FIG. 6 can be referred to descriptions related to FIG. 3 or FIG. 5 . In the embodiment illustrated in FIG. 6 , the first oscillation circuit 110 is implemented by using a ten-stage ring oscillator (including 10 main loop inverters MLI 1 -MLI 10 ) to generate a ten-phase output (i.e., the outputs of the main loop inverters MLI 1 -MLI 10 ). The clock signal generated by the output terminal of one (or more) of the main loop inverters MLI 1 -MLI 10 can be the output clock signal CLK of the CLCG 100 . In other embodiments, different number of stages of the ring oscillator in the first oscillation circuit 110 of FIG. 6 can be implemented by analogy with descriptions related to FIG. 6 .

Referring to FIG. 1 and FIG. 6 , besides the main loop inverters MLI 1 -MLI 10 , the first oscillation circuit 110 further includes 10 secondary loop inverters SLI 1 -SLI 10 . The input terminal of the secondary loop inverter SLI; is coupled to the output terminal P<i+1> of the main loop inverter MLI i+1 , and the output terminal of the secondary loop inverter SLI i is coupled to the input terminal of the main loop inverter MLI i (i.e., the output terminal P<i−1> of the main loop inverter MLI i−1 ), wherein i is an integer. For example, the input terminal of the secondary loop inverter SLI 3 is coupled to the output terminal P<4> of the main loop inverter MLI 4 , and the output terminal of the secondary loop inverter SLI 3 is coupled to the input terminal of the main loop inverter MLI 3 (i.e., the output terminal P<2> of the main loop inverter MLI 2 ). The secondary loop inverters SLI 1 -SLI 10 can be implemented with any technique. In the present embodiment, the implementation of the secondary loop inverters SLI 1 -SLI 10 can be referred to descriptions related to FIG. 4 . The main loop inverters MLI 1 -MLI 10 and the secondary loop inverters SLI 1 -SLI 10 may be controlled by the control signal Sc to adjust the output frequency of the first oscillation circuit 110 . The operating frequency of the first oscillation circuit 110 in FIG. 6 does not decrease severely with the increase of the stage number.

In another embodiment, the control signal Sc includes a coarse-tuning signal C (for example, the bits C<0>-C<4> in FIG. 4 ) and a fine-tuning signal F, and the first oscillation circuit 110 further includes at least one varactor VC i . The at least one varactor VC i is coupled to the output terminal of one of the main loop inverters MLI 1 -MLI 10 (for example, to the output terminal P<i> of the i th main loop inverter MLI i ). The at least one varactor VC i is controlled by the fine-tuning signal F. The number of the at least one varactor VC i can be determined according to the actual design requirement. For example, 10 varactors VC 1 -VC 10 (not shown) are disposed in the first oscillation circuit 110 illustrated in FIG. 6 , where the varactors VC 1 -VC 10 are respectively coupled to the output terminals P<1>-P<10> of the main loop inverters MLI 1 -MLI 10 .

The at least one varactor VC i can be implemented with any technique. FIG. 7 is a circuit diagram of a varactor VC i according to an embodiment of the present disclosure. The varactor VC i includes a plurality of metal-oxide semiconductor (MOS) capacitors. Herein it is assumed that the varactor VC i includes 7 MOS capacitors C 1 , C 2 , . . . , and C 7 . However, the number of the MOS capacitors is not limited in other embodiments. The sizes of the MOS capacitors C 1 -C 7 are different from each other. For example, the size of the MOS capacitor C 2 is twice that of the MOS capacitor C 1 , and the size of the MOS capacitor C 7 is 64 times of that of the MOS capacitor C 1 . The first ends of the MOS capacitors C 1 -C 7 are all coupled to the output terminal P<i> of the i th main loop inverter MLI i in the first oscillation circuit 110 illustrated in FIG. 6 . The second ends of the MOS capacitors C 1 -C 7 respectively receive the bits F<0>, F<1>, . . . , and F<6> in the fine-tuning signal F of the control signal Sc. Thus, the varactor VC i is controlled by the fine-tuning signal F of the control signal Sc. Referring to FIG. 6 and FIG. 7 , the main loop inverters MLI 1 -MLI 10 and the secondary loop inverters SLI 1 -SLI 10 are controlled by the bits C<0>-C<4> of the control signal Sc to perform coarse frequency tuning, and the varactor VC i is controlled by the bits F<0>-F<6> of the control signal Sc to perform fine frequency tuning, so that high-resolution frequency adjustment can be accomplished.

Referring to FIG. 1 , the second oscillation circuit 120 generates a reference clock signal CKr in step S 220 . In some embodiments, the circuit structure of the second oscillation circuit 120 is the same as that of the first oscillation circuit 110 . In other embodiments, the second oscillation circuit 120 includes a ring oscillator for generating the reference clock signal CKr.

The control circuit 130 is coupled to the first oscillation circuit 110 to receive the output clock signal CLK and is coupled to the second oscillation circuit 120 to receive the reference clock signal CKr. In step S 230 , the control circuit 130 generates the control signal Sc for the first oscillation circuit 110 according to the relationship between the output clock signal CLK and the reference clock signal CKr to correct a frequency error/accuracy of the output clock signal CLK caused by an environmental variation. The environmental variation includes a temperature variation, a voltage variation, a process variation, or a variation in any other environmental condition. Regarding voltage variation, process drift, and temperature variation, the control circuit 130 can compensate for the operating frequency of the first oscillation circuit 110 . When a temperature variation causes the frequency of the output clock signal CLK to drift, the control circuit 130 can compensate for the frequency by a compensation mechanism.

As described above, the embodiment of the present disclosure provides a CLCG, in which when frequency drift is caused by an environmental variation (for example, the variation of temperature or any other environmental condition), the frequency of the output clock signal can be automatically adjusted to the target operating frequency.

FIG. 8 is a flowchart of an operation method of a CLCG according to another embodiment of the present disclosure. Steps S 810 , S 820 , and S 830 in FIG. 8 can be referred to steps S 210 , S 220 , and S 230 in FIG. 2 . In the embodiment illustrated in FIG. 8 , step S 830 further includes sub-steps S 831 , S 832 , and S 833 . Referring to FIG. 1 and FIG. 8 , in step S 831 , the control circuit 130 calculates a difference (referred to as a first difference thereinafter) between the frequency of the output clock signal CLK and a first reference frequency, and in step S 832 , the control circuit 130 calculates a difference (referred to as a second difference thereinafter) between the frequency of the reference clock signal CKr and a second reference frequency.

Aforementioned first reference frequency and second reference frequency can be determined according to the design requirement. For example, the first reference frequency can be the rated output frequency (or target frequency) of the first oscillation circuit 110 , and the second reference frequency can be the rated output frequency (or target frequency) of the second oscillation circuit 120 . As another example, the control circuit 130 can take the frequency of the output clock signal CLK measured for the first time after the first oscillation circuit 110 is initialized to serve as the first reference frequency, and take the frequency of the reference clock signal CKr measured for the first time after the second oscillation circuit 120 is initialized to serve as the second reference frequency.

In step S 833 , based on the relationship between the first difference and the second difference, the control circuit 130 generates the control signal Sc for the first oscillation circuit 110 to correct the frequency error/accuracy of the output clock signal CLK caused by the temperature variation. When the temperature of the CLCG 100 changes, the frequency of the output clock signal CLK of the first oscillation circuit 110 and the frequency of the reference clock signal CKr of the second oscillation circuit 120 change with the temperature. During the operation, the control circuit 130 constantly monitors the relationship between the first difference and the second difference and adjusts the control signal Sc accordingly until the first difference is equal to the second difference.

FIG. 9 is a circuit block diagram of a CLCG 900 according to an embodiment of the present disclosure. The CLCG 900 illustrated in FIG. 9 can be referred to descriptions related to the CLCG 100 illustrated in FIG. 1 . In the embodiment illustrated in FIG. 9 , the control circuit 130 includes a time-to-digital converter (TDC) 910 and a controller 920 . The TDC 910 is coupled to the first oscillation circuit 110 and the second oscillation circuit 120 . The controller 920 is coupled to the output terminal of the TDC 910 . The TDC 910 converts time into a digital code and provides the digital code to the controller 920 . For example, the TDC 910 converts the period of the output clock signal CLK (or reference clock signal CKr) into a corresponding digital code. Or, when the output clock signal CLK (or reference clock signal CKr) contains two signals of different phases, the TDC 910 may convert the phase difference between the two signals into a corresponding digital code.

FIG. 10 is a flowchart of an operation method of a CLCG according to yet another embodiment of the present disclosure. Steps S 1010 , S 1020 , and S 1030 in FIG. 10 can be referred to descriptions related to steps S 210 , S 220 , and S 230 in FIG. 2 . Referring to FIG. 9 and FIG. 10 , step S 1030 further includes sub-steps S 1031 , S 1032 , and S 1033 . In step S 1031 , the TDC 910 converts the output clock signal CLK into an output clock characteristic value, and in step S 1032 , the TDC 910 converts the reference clock signal CKr into a reference clock characteristic value.

The TDC 910 can be implemented with any technique. FIG. 11 is a circuit block diagram of the TDC 910 according to an embodiment of the present disclosure. To increase the resolution, produce a sufficient measurement range, and obtain a low power consumption and a low cost, the TDC 910 is implemented through a vernier technique. Referring to FIG. 11 , the TDC 910 includes a first gate circuit 1110 , a second gate circuit 1120 , a first vernier oscillator 1130 , a second vernier oscillator 1140 , a phase detector 1150 , a first counter 1160 , a second counter 1170 , and a subtractor 1180 . The output clock signal CLK generated by the first oscillation circuit 110 will be taken as an example to explain how the TDC 910 converts the time of the output clock signal CLK into a digital code in the following description. The conversion of the reference clock signal CKr generated by the second oscillation circuit 120 can be referred to descriptions related to the output clock signal CLK.

In the present embodiment, the output clock signal CLK includes a plurality of clock signals having different phases, where two clock signals are respectively transmitted to the first gate circuit 1110 and the second gate circuit 1120 through the input terminals VRO in1 and VRO in2 of the TDC 910 . The first gate circuit 1110 and the second gate circuit 1120 can enable the first vernier oscillator 1130 and the second vernier oscillator 1140 in a working state. Thus, the first gate circuit 1110 and the second gate circuit 1120 can respectively transmit the clock signals of the input terminals VRO in1 and VRO in2 to the enabling terminals of the first vernier oscillator 1130 and the second vernier oscillator 1140 .

FIG. 12 is a signal timing diagram of the TDC 910 in FIG. 11 according to an embodiment of the present disclosure. Referring to FIG. 11 and FIG. 12 , the first gate circuit 1110 and the second gate circuit 1120 in the working state respectively transmit the clock signals of the input terminals VRO in1 and VRO in2 to the enabling terminals of the first vernier oscillator 1130 and the second vernier oscillator 1140 . When the signal at the enabling terminal of the first vernier oscillator 1130 is in an enabling state (for example, logic 1), the first vernier oscillator 1130 generates an oscillation signal OSC slow having a frequency Freq 1 . When the signal at the enabling terminal of the first vernier oscillator 1130 is in a disabling state (for example, logic 0), the oscillation signal OSC slow of the first vernier oscillator 1130 remains at logic 0 (no oscillation). The operation of the second gate circuit 1120 is the same as that of the first vernier oscillator 1130 , and the second gate circuit 1120 selectively generates an oscillation signal OSC fast having a frequency Freq 2 . Herein the oscillation frequency Freq 1 of the first vernier oscillator 1130 is different from the oscillation frequency Freq 2 of the second gate circuit 1120 . For example, the oscillation frequency Freq 1 of the first vernier oscillator 1130 is 324.36 MHz, while the oscillation frequency Freq 2 of the second gate circuit 1120 is 334.06 MHz.

Two input terminals of the phase detector 1150 are respectively coupled to the output terminals of the first vernier oscillator 1130 and the second vernier oscillator 1140 to receive the oscillation signal OSC slow and the oscillation signal OSC fast . The phase detector 1150 detects the phase relationship between the oscillation signal OSC slow and the oscillation signal OSC fast and outputs a detection result VRO out . When the rising edge of the oscillation signal OSC slow and the rising edge of the oscillation signal OSC fast are aligned, the phase detector 1150 outputs a gate signal S to the first gate circuit 1110 and the second gate circuit 1120 to change the operation state of the first gate circuit 1110 and the second gate circuit 1120 from the working state to a standby state. In the standby state, the clock signals of the input terminals VRO in1 and VRO in2 cannot reach to the enabling terminals of the first vernier oscillator 1130 and the second vernier oscillator 1140 , so that the first vernier oscillator 1130 and the second vernier oscillator 1140 are disabled.

The second counter 1170 is coupled to the second vernier oscillator 1140 . The second counter 1170 counts the number of pulses of the oscillation signal OSCin 2 and outputs the counting result as a fine-tuning signal F out of the output clock characteristic value of the output clock signal CLK. The first counter 1160 is coupled to the first vernier oscillator 1130 . The first counter 1160 counts the number of pulses of the oscillation signal OSCin 1 and outputs the counting result. The subtractor 1180 is coupled to the output ten iinals of the first counter 1160 and the second counter 1170 . The subtractor 1180 calculates the difference between the two counting results and outputs the calculation result as a coarse-tuning signal C out of the output clock characteristic value of the output clock signal CLK. The TDC 910 offers both a coarse tuning function and a fine tuning function such that the measurement range can be greatly broadened without sacrificing the high resolution.

FIG. 13 is an input/output comparison diagram of the TDC 910 in FIG. 11 according to an embodiment of the present disclosure. In FIG. 13 , the abscissa indicates the input (in unit of ns) of the TDC 910 , and the ordinate indicates the output (a digital code) of the TDC 910 . When the clock signals of the input terminals VRO in1 and VRO in2 have different time (phases), the TDC 910 outputs a corresponding digital code.

Referring to FIG. 9 and FIG. 10 , in step S 1033 , the controller 920 generates the control signal Sc for the first oscillation circuit 110 according to the relationship between the output clock characteristic value of the output clock signal CLK and the reference clock characteristic value of the reference clock signal CKr to correct the frequency error/accuracy of the output clock signal CLK caused by a temperature variation. How the controller 920 generates the control signal Sc can be referred to descriptions related to the control circuit 130 in FIG. 1 .

FIG. 14 is a circuit block diagram of a CLCG 1400 according to an embodiment of the present disclosure. The CLCG 1400 illustrated in FIG. 14 can be referred to descriptions related to the CLCG 100 illustrated in FIG. 1 or the CLCG 900 illustrated in FIG. 9 . Unlike that in the embodiment illustrated in FIG. 9 , in the embodiment illustrated in FIG. 14 , the control circuit 130 includes a first time amplifier (TA) 1410 , a second TA 1420 , a time-to-digital converter (TDC) 1430 , and a controller 1440 . The TDC 1430 and the controller 1440 can be referred to descriptions related to the TDC 910 and the controller 920 in FIG. 9 . The input terminal of the first TA 1410 is coupled to the output terminal of the first oscillation circuit 110 . The input terminal of the second TA 1420 is coupled to the output terminal of the second oscillation circuit 120 .

FIG. 15 is a flowchart of an operation method of a CLCG according to still another embodiment of the present disclosure. Steps S 1510 , S 1520 , and S 1530 in FIG. 15 can be referred to descriptions related to steps S 210 , S 220 , and S 230 in FIG. 2 or to descriptions related to steps S 1010 , S 1020 , and S 1030 in FIG. 10 . Referring to FIG. 14 and FIG. 15 , step S 1530 further includes sub-steps S 1531 , S 1532 , S 1533 , S 1534 , and S 1535 . In step S 1531 , the first TA 1410 amplifies the time of the output clock signal CLK according to a first gain-adjustment signal G 1 and outputs the amplified output clock signal CLK to the TDC 1430 , where the gain of the first TA 1410 is controlled by the first gain-adjustment signal G 1 . In step S 1532 , the second TA 1420 amplifies the time of the reference clock signal CKr according to a second gain-adjustment signal G 2 and outputs the amplified reference clock signal CKr to the TDC 1430 , where the gain of the second TA 1420 is controlled by the second gain-adjustment signal G 2 . The first gain-adjustment signal G 1 and/or the second gain-adjustment signal G 2 can be determined according to the process drift.

The first gain-adjustment signal G 1 and/or the second gain-adjustment signal G 2 can be implemented with any technique. FIG. 16 is a circuit block diagram of the first TA 1410 in FIG. 14 according to an embodiment of the present disclosure. The implementation of the second TA 1420 can be referred to descriptions related to the first TA 1410 . Referring to FIG. 16 , the first TA 1410 is a multi-modulus TA. The first TA 1410 includes n modulus circuits (frequency divider circuits) 1610 _ 1 , 1610 _ 2 , . . . , and 1610 — n . For example, the modulus circuits 1610 _ 1 - 1610 — n are divide-by-2 or divide-by-3 frequency divider circuits. The frequency dividing factor of the modulus circuits 1610 _ 1 - 1610 — n are controlled by the first gain-adjustment signal G 1 . In the present embodiment, the first gain-adjustment signal G 1 includes bits MC 0 , MC 1 , . . . , and MC n-1 for respectively controlling the frequency dividing factor of the modulus circuits 1610 _ 1 - 1610 — n . Taking the modulus circuit 1610 _ 1 as an example, when the bit MC 0 is logic 0, the modulus circuit 1610 _ 1 is a divide-by-2 frequency divider circuit, and when the bit MC 0 is logic 1, the modulus circuit 1610 _ 1 is a divide-by-3 frequency divider circuit.

The modulus circuits 1610 _ 1 - 1610 — n are connected with each other in series, as shown in FIG. 16 . The input terminal in of the modulus circuit 1610 _ 1 receives the output clock signal CLK, and the output terminal out of the modulus circuit 1610 — n generates the amplified output clock signal CLK for the TDC 1430 . When a temperature variation occurs, the frequency of the first oscillation circuit 110 changes with the temperature. In this case, the output period difference of the first oscillation circuit 110 caused by the temperature variation is amplified by the first TA 1410 , and the amplified time width is then sent to the TDC 1430 to be analyzed. The function of the first TA 1410 in the entire system is as shown in FIG. 17 .

FIG. 17 is a diagram illustrating the temperature-frequency relationship in the CLCG 1400 in FIG. 14 according to an embodiment of the present disclosure. In FIG. 17 , different gain selections are illustrated, and the temperature compensation system curves illustrated in FIG. 17 represent different slope changes. For example, if the first gain-adjustment signal G 1 (or the gain of the first TA 1410 ) is 4, the temperature-frequency relationship of the amplified output clock signal CLK is indicated by the curve 1710 . If the first gain-adjustment signal G 1 (or the gain of the first TA 1410 ) is 5, the temperature-frequency relationship of the amplified output clock signal CLK is indicated by the curve 1720 . The second TA 1420 has similar operations. The TA 1410 and/or 1420 can further adjust the slope of the compensated frequency along with process variations, so as to achieve a stable output frequency in the changing temperature.

Referring to FIG. 14 and FIG. 15 , the TDC 1430 is coupled to the output terminal of the first TA 1410 to convert the output signal of the first TA 1410 into an output clock characteristic value of the output clock signal CLK (step S 1533 ). The TDC 1430 is also coupled to the output terminal of the second TA 1420 to convert the output signal of the second TA 1420 into a reference clock characteristic value of the reference clock signal CKr (step S 1534 ). The controller 1440 is coupled to the output terminal of the TDC 1430 . The controller 1440 generates the control signal Sc for the first oscillation circuit 110 according to the relationship between the output clock characteristic value of the output clock signal CLK and the reference clock characteristic value of the reference clock signal CKr to correct the frequency error/accuracy of the output clock signal CLK caused by the temperature variation (step S 1535 ).

As shown in FIG. 17 , it is assumed that the first gain-adjustment signal G 1 (or the gain of the first TA 1410 ) is 5 (i.e., the temperature-frequency relationship of the amplified output clock signal CLK is indicated by the curve 1720 ). Equivalently, the controller 1440 generates the compensation curve 1730 in FIG. 17 according to the relationship between the output clock signal CLK and the reference clock signal CKr. Thus, the compensation curve 1730 can compensate the frequency error/accuracy (as indicated by the curve 1720 ) caused by the temperature variation, so that the temperature-frequency relationship of the compensated output clock signal CLK of the first oscillation circuit 110 is as indicated by the curve 1740 .

FIG. 18 is a circuit block diagram of a CLCG 1800 according to an embodiment of the present disclosure. The CLCG 1800 illustrated in FIG. 18 can be referred to descriptions related to the CLCG 100 illustrated in FIG. 1 or the CLCG 1400 illustrated in FIG. 14 . Unlike that in the embodiment illustrated in FIG. 14 , in the embodiment illustrated in FIG. 18 , the control circuit 130 includes a first TA 1810 , a second TA 1820 , a multiplexer 1830 , a time-to-digital converter (TDC) 1840 , and a controller 1850 . The first TA 1810 , the second TA 1820 , the TDC 1840 , and the controller 1850 can be referred to descriptions related to the first TA 1410 , the second TA 1420 , the TDC 1430 , and the controller 1440 in FIG. 14 .

The input terminal of the first TA 1810 is coupled to the output terminal of the first oscillation circuit 110 . The input terminal of the second TA 1820 is coupled to the output terminal of the second oscillation circuit 120 . The first input terminal of the multiplexer 1830 is coupled to the output terminal of the first TA 1810 . The second input terminal of the multiplexer 1830 is coupled to the output terminal of the second TA 1820 . The input terminal of the TDC 1840 is coupled to the output terminal of the multiplexer 1830 . The multiplexer 1830 selectively pass the output of the first TA 1810 or the second TA 1820 to the TDC 1840 . The TDC 1840 alternatively converts the output signal of the first TA 1810 into an output clock characteristic value and converts the output signal of the second TA 1820 into a reference clock characteristic value.

The controller 1850 is coupled to the output terminal of the TDC 1840 . The controller 1850 generates the control signal Sc for the first oscillation circuit 110 according to the relationship between the output clock characteristic value of the output clock signal CLK and the reference clock characteristic value of the reference clock signal CKr to correct the frequency error/accuracy of the output clock signal CLK caused by the temperature variation. How the controller 1850 generates the control signal Sc can be referred to descriptions related to the control circuit 130 in FIG. 1 .

FIG. 19 is a circuit block diagram of a CLCG 1900 according to an embodiment of the present disclosure. The CLCG 1900 illustrated in FIG. 19 can be referred to the CLCG 100 illustrated in FIG. 1 or the CLCG 1800 illustrated in FIG. 18 . Unlike that in the embodiment illustrated in FIG. 18 , in the embodiment illustrated in FIG. 19 , the controller 1850 includes a demultiplexer 1910 , a first register 1921 , a second register 1922 , a third register 1923 , a fourth register 1924 , a compensator 1930 , and a digital filter 1940 . The first TA 1810 , the second TA 1820 , the multiplexer 1830 , and the TDC 1840 can be referred to descriptions related to the first TA 1810 , the second TA 1820 , the multiplexer 1830 , and the TDC 1840 in FIG. 18 .

The input terminal of the demultiplexer 1910 is coupled to the output terminal of the TDC 1840 . The first register 1921 is coupled to the first output terminal of the demultiplexer 1910 for recording a first reference frequency. The second register 1922 is coupled to the second output terminal of the demultiplexer 1910 for recording a second reference frequency. The third register 1923 is coupled to the third output terminal of the demultiplexer 1910 for recording the current output clock characteristic value of the output clock signal CLK. The fourth register 1924 is coupled to the fourth output terminal of the demultiplexer 1910 for recording the current reference clock characteristic value of the reference clock signal CKr.

At the initial temperature, the TDC 1840 converts the output clock signal CLK of the first oscillation circuit 110 into a digital code and records the digital code related to the output clock signal CLK into the first register 1921 through the demultiplexer 1910 as the first reference frequency. At this initial temperature, the TDC 1840 also converts the reference clock signal CKr of the second oscillation circuit 120 into a digital code and records this digital code related to the reference clock signal CKr into the second register 1922 through the demultiplexer 1910 as the second reference frequency.

During the operation, the temperature of the CLCG 1900 may change. The temperature variation causes the frequencies of the first oscillation circuit 110 and the second oscillation circuit 120 to drift. The TDC 1840 converts the output clock signal CLK of the first oscillation circuit 110 into a digital code at the current temperature and records the digital code related to the output clock signal CLK into the third register 1923 through the demultiplexer 1910 as the output clock characteristic value. The TDC 1840 also converts the reference clock signal CKr of the second oscillation circuit 120 into a digital code at the current temperature and records the digital code related to the reference clock signal CKr into the fourth register 1924 through the demultiplexer 1910 as the reference clock characteristic value.

The compensator 1930 is coupled to the first register 1921 , the second register 1922 , the third register 1923 , and the fourth register 1924 . The compensator 1930 generates the control signal Sc according to the contents of the first register 1921 , the second register 1922 , the third register 1923 , and the fourth register 1924 . For example, in the present embodiment, the compensator 1930 calculates the difference (referred to as a first difference) between the output clock characteristic value recorded in the third register 1923 and the first reference frequency recorded in the first register 1921 and calculates the difference (referred to as a second difference) between the reference clock characteristic value recorded in the fourth register 1924 and the second reference frequency recorded in the second register 1922 . The compensator 1930 generates the control signal Sc based on the relationship between the first difference and the second difference. When the temperature of the CLCG 1900 changes, the contents in the third register 1923 and the fourth register 1924 change with the temperature. During the operation, the compensator 1930 constantly monitors the relationship between the first difference and the second difference and adjusts the control signal Sc accordingly until the first difference is equal to the second difference. In other embodiments, the first difference and the second difference are respectively multiplied by a first weight and a second weight, and the compensator 1930 constantly monitors the relationship between the first difference and the second difference and adjusts the control signal Sc accordingly until the product of the first difference and the first weight is equal to the product of the second difference and the second weight.

In the present embodiment, the compensator 1930 can be implemented with any technique. FIG. 20 is a circuit block diagram of the compensator 1930 in FIG. 19 according to an embodiment of the present disclosure. The compensator 1930 includes a first subtractor 1931 , a fifth register 1932 , an adder 1933 , a sixth register 1934 , and a second subtractor 1935 . The first subtractor 1931 is coupled to the second register 1922 and the fourth register 1924 . The first subtractor 1931 calculates and outputs the difference (i.e., the second difference) between the contents of the second register 1922 and the fourth register 1924 . The fifth register 1932 is coupled to the output terminal of the first subtractor 1931 for recording the second difference output by the first subtractor 1931 . The adder 1933 is coupled to the first register 1921 and the fifth register 1932 . The adder 1933 calculates and outputs the sum of the contents of the first register 1921 and the fifth register 1932 . The sixth register 1934 is coupled to the output terminal of the adder 1933 for recording the output of the adder 1933 . The second subtractor 1935 is coupled to the third register 1923 and the sixth register 1934 . The second subtractor 1935 calculates the difference between the contents of the third register 1923 and the sixth register 1934 and outputs the difference as the control signal Sc to the digital filter 1940 .

Referring to FIG. 19 , the digital filter 1940 is coupled to the compensator 1930 . The digital filter 1940 receives and accumulates the operation result output by the compensator 1930 to obtain an accumulation result. The digital filter 1940 also generates an appropriate digital control code (i.e., the control signal Sc) for a digital oscillator (i.e., the first oscillation circuit 110 ) according to the stability requirement of the system loop and the accumulation result, so as to determine/modulate the oscillation frequency of the output clock signal CLK. The digital filter 1940 filters the control signal Sc generated by the compensator 1930 and transmits the filtered control signal Sc to the first oscillation circuit 110 . In the present embodiment, the digital filter 1940 can be implemented with any technique. For example, the digital filter 1940 can be realized by using a digital loop filter (DLF).

FIG. 21 is a circuit block diagram of the digital filter 1940 in FIG. 19 according to an embodiment of the present disclosure. The digital filter 1940 includes an amplifier K P , an amplifier K I , an adder 1943 , an adder 1944 , a flip-flop 1945 , and a flip-flop 1946 . The amplifier K P and the amplifier K I respectively shift the operation result of the compensator 1930 . The adder 1943 is coupled to the output terminal of the amplifier K P and the output terminal of the flip-flop 1945 . The adder 1943 calculates and outputs the sum of the output of the amplifier K P and the output signal D of the flip-flop 1945 . Two input terminals of the adder 1944 are respectively coupled to the output terminal of the amplifier K I and the output terminal of the flip-flop 1945 . The adder 1944 calculates and outputs the sum of the output of the amplifier K I and the output signal D of the flip-flop 1945 . The input terminal of the flip-flop 1945 is coupled to the output terminal of the adder 1944 , and the trigger terminal of the flip-flop 1945 is coupled to a sample signal Ts. The adder 1944 and the flip-flop 1945 constitute an accumulative circuit such that the output of the amplifier K I can be accumulated according to the timing of the sample signal Ts. Through the shifting operations of the amplifier K P and the amplifier K I , the output signal D of the flip-flop 1945 is sent back to the adder 1944 to be accumulated and is stored in the flip-flop 1945 .

The output signal D of the flip-flop 1945 is sent to the adder 1943 to be added to the output of the amplifier K P . The input terminal of the flip-flop 1946 is coupled to the output terminal of the adder 1943 , the trigger terminal of the flip-flop 1945 is coupled to the sample signal Ts, and the output terminal of the flip-flop 1946 outputs the filtered control signal Sc to the first oscillation circuit 110 . The sample signal Ts may be a signal obtained by dividing the frequency of the output clock signal CLK of the first oscillation circuit 110 . The flip-flop 1946 synchronizes the output signal with the sample signal and eliminates any glitch produced by the adder 1943 . Based on the relationship between the first difference and the second difference calculated by the compensator 1930 , the digital filter 1940 accumulates the operation result of the compensator 1930 and constantly adjusts the control signal Sc accordingly until the first difference is equal to the second difference (i.e., until the operation result of the compensator 1930 is 0).

Thus, the digital filter 1940 can accumulate the operation result output by the compensator 1930 and generate an appropriate control signal Sc for the first oscillation circuit 110 according to the stability requirement of the system loop and the accumulation result, so as to modulate the oscillation frequency of the output clock signal CLK accordingly. Herein the sampling frequency and the digital filter modulation signal (Kp and Ki) affect the overall loop stability.

FIG. 22 is a graph illustrating the temperature-output frequency relationship in the CLCG 1900 in FIG. 19 according to an embodiment of the present disclosure. In FIG. 22 , the ordinate indicates the frequency of the output clock signal CLK of the first oscillation circuit 110 , and the abscissa indicates the temperature of the CLCG 1900 . Herein the simulation condition is that the first gain-adjustment signal G 1 has a fixed value and the second gain-adjustment signal G 2 has a fixed value. FIG. 22 illustrates the simulated frequency error of the output clock signal CLK when the temperature variation is 0° C.-100° C. Herein it is assumed that the operating voltage of the CLCG 1900 is 0.5 V, and with a typical-typical (TT) process and a temperature of 25° C., the power consumption of the CLCG 1900 is 1.2 mW. The simulation result of the frequency accuracy with a temperature variation is shown. The frequency accuracy is within ±3%.

FIG. 23 is a circuit block diagram of a CLCG 2300 according to an embodiment of the present disclosure. The CLCG 2300 illustrated in FIG. 23 can be referred to descriptions related to the CLCG 100 illustrated in FIG. 1 or the CLCG 1900 illustrated in FIG. 19 , therefore will not be described herein. Unlike that in the embodiment illustrated in FIG. 19 , in the embodiment illustrated in FIG. 23 , the control circuit 130 further includes a multiplexer 2310 . The first input terminal of the multiplexer 2310 is coupled to the output terminal of the controller 1850 for receiving the control signal Sc 1 , the second input terminal of the multiplexer 2310 receives the external control signal Sc 2 , and the output terminal of the multiplexer 2310 is coupled to the first oscillation circuit 110 . The multiplexer 2310 selectively pass the control signal Sc 1 or the external control signal Sc 2 to the first oscillation circuit 110 as the control signal Sc.

During the initialization of the CLCG 2300 , the multiplexer 2310 pass the external control signal Sc 2 to the first oscillation circuit 110 as the control signal Sc. Thus, the CLCG 2300 can be calibrated through the external control signal Sc 2 , so as to adjust the output clock signal CLK of the first oscillation circuit 110 to have the system target frequency. This technique can adjust the frequency drift of a chip caused by process drift. After the CLCG 2300 is initialized, the multiplexer 2310 pass the control signal Sc 1 output by the controller 1850 to the first oscillation circuit 110 as the control signal Sc. Herein the temperature compensation mechanism of the control circuit 130 is enabled. The temperature compensation mechanism of the control circuit 130 has been described in detail in foregoing embodiments, therefore will not be described herein.

As described above, in the embodiments described above, a system-target operating frequency can be set up at a normal temperature. After that, the operating frequency is dynamically compensated through the temperature compensation mechanism of the control circuit 130 , so as to calibrate the operating frequency of the system. When the temperature changes, the control circuit 130 detects any change in the output frequencies of the first oscillation circuit 110 and the second oscillation circuit 120 and converts the output clock signal CLK and the reference clock signal CKr into digital values by a time-to-digital converter (TDC). Next, the control circuit 130 performs a calculation on the digital values and sends the calculation result into a digital filter, so as to calibrate the frequency of the first oscillation circuit 110 . Additionally, in some embodiments, a TA is disposed before the TDC. The TA can further adjust the slope of the compensated frequency according to any process variation, so as to achieve a stable output frequency at a changing temperature. The first oscillation circuit 110 may provide a multi-phase output clock signal.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.