High efficiency zero-voltage switching (ZVS) assistance circuit for power converter

This invention was made with government support under Contract No. N00014-09-D-0726 awarded by the United States Navy. The U.S. government has certain rights in the invention.

This disclosure is generally directed to power converters. More specifically, this disclosure is directed to a high efficiency zero-voltage switching (ZVS) assistance circuit for a power converter.

Power converters are used to convert electrical energy from one form to another form. For example, direct current-to-direct current (DC-to-DC) power converters are used to convert power from one DC form to another DC form. Efficiency is often an important characteristic of power converters. Power converters with higher efficiencies dissipate less energy during the conversion process than power converters with lower efficiencies. This can have significant impact on, for example, the length of time that a device can be used before recharging of a power supply in the device is needed.

Switched mode power converters repeatedly turn various transistors on and off to control the conversion of power from one form to another. Phase shift modulation (PSM) is one type of control technique that can be used to control the transistors in a switched mode power converter. PSM control can maintain low switching losses and low noise by operating in a “zero-voltage switching” (ZVS) mode of operation. In this mode, transistors are switched on and off at or near a zero voltage, which can help to reduce or minimize switching losses in the transistors. Combined with high switching frequencies, ZVS can be used to achieve compact and low-loss power converters.

Unfortunately, there are various problems associated with conventional power converters that operate using zero-voltage switching. For example, losses within conventional power converters typically increase when lighter loads are connected to the power converters. Also, conventional power converters can experience excessive reactive power at higher input levels. One method of providing ZVS introduces a source of additional inductive (lagging) current into switching nodes of a PSM-controlled power converter. This approach helps to increase the power converter's efficiency at lighter loads, but it also typically compromises the power converter's efficiency at mid-range loads and full loads. This approach also does not address the problem of reducing reactive power processed by a power converter at higher input levels.

This disclosure provides a high efficiency zero-voltage switching (ZVS) assistance circuit for a power converter.

In a first embodiment, an apparatus includes a power converter configured to convert input power into output power. The power converter includes first and second converter bridges, where each converter bridge includes multiple transistors. The apparatus also includes a zero-voltage switching (ZVS) assistance circuit having first and second inverse controlled rectifiers (ICRs). Each of the first and second ICRs is configured to provide current to the transistors in the first and second converter bridges.

In a second embodiment, a system includes a power converter configured to convert input power into output power. The power converter includes first and second converter bridges, where each converter bridge includes multiple transistors. The system also includes a zero-voltage switching (ZVS) assistance circuit having first and second inverse controlled rectifiers (ICRs). Each of the first and second ICRs is configured to provide current to the transistors in the first and second converter bridges. The system further includes a controller configured to control operation of the first and second converter bridges and the ZVS assistance circuit.

In a third embodiment, a method includes converting input power into output power using first and second converter bridges of a power converter. Each converter bridge includes multiple transistors. The method also includes providing current to the transistors in the first and second converter bridges using a zero-voltage switching (ZVS) assistance circuit. The ZVS assistance circuit includes first and second inverse controlled rectifiers (ICRs) that provide the current.

Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.

For a more complete understanding of this disclosure and its features, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 3B illustrate an example power converter with a high efficiency zero-voltage switching (ZVS) assistance circuit and related details according to this disclosure;

FIGS. 4 through 15 illustrate example operational characteristics of a power converter with a high efficiency ZVS assistance circuit according to this disclosure; and

FIG. 16 illustrates an example method for performing power conversion with ZVS assistance according to this disclosure.

FIGS. 1 through 16 , described below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any type of suitably arranged device or system.

This disclosure provides a zero-voltage switching (ZVS) assistance topology that uses Inverse Controlled Rectifiers (ICRs) and a related system and method. The ZVS assistance topology disclosed here helps to resolve various problems associated with conventional circuits, such as a loss of efficiency at lighter loads and excessive reactive power at higher input levels. Moreover, the ZVS assistance topology disclosed here provides additional advantages, such as improved reliability and efficiency, compared to conventional circuits.

FIGS. 1 through 3B illustrate an example power converter 100 with a high efficiency zero-voltage switching (ZVS) assistance circuit and related details according to this disclosure. In this example, the power converter 100 generally receives a direct current (DC) input defined across two input pins DC IN and DC IN Return. The power converter 100 converts the DC input into a DC output defined across two output pins DC OUT and DC OUT Return. An input capacitor 102 (C IN ) is coupled across the input pins to smooth variations in the input signal. The input capacitor 102 includes any suitable capacitive structure having any suitable capacitance.

As shown in FIG. 1 , the power converter 100 includes two primary series resonant converter (SRC) bridges 104 - 106 . Each primary SRC bridge 104 - 106 generally denotes a circuit arrangement that causes an inductance and a capacitance to resonate in order to improve the efficiency of a power conversion. Each capacitance in the primary SRC bridges 104 - 106 represents any suitable capacitive structure having any suitable capacitance. Each inductance in the primary SRC bridges 104 - 106 represents any suitable inductive structure having any suitable inductance. Among other things, the primary SRC bridges 104 - 106 are used to feed first and second auxiliary transformers (denoted Ta 1 and Ta 2 ).

Each primary SRC bridge 104 - 106 also includes four transistors 108 a - 114 a (denoted Q 1 -Q 4 ) and 108 b - 114 b (denoted Q 1 ′-Q 4 ′), respectively. The transistors 108 a - 110 a are coupled to node A in the SRC bridge 104 , and transistors 112 a - 114 a are coupled to node B in the SRC bridge 104 . The transistors 108 b - 110 b are coupled to node A 1 in the SRC bridge 106 , and transistors 112 b - 114 b are coupled to node B 1 in the SRC bridge 106 . The transistors 108 a - 114 a , 108 b - 114 b can be switched on and off to control the power conversion in the converter 100 . Each transistor 108 a - 114 a , 108 b - 114 b includes any suitable switching device, such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).

The power converter 100 also includes two secondary SRC bridges 116 - 118 . The secondary bridges 116 - 118 receive electrical power from the primary bridges 104 - 106 , respectively, via two main transformers (not shown). The secondary bridges 116 - 118 output the electrical power as the DC output of the power converter 100 . Each secondary bridge 116 - 118 includes any suitable structure for receiving and outputting electrical power.

The power converter 100 further includes two Inverse Controlled Rectifiers (ICRs) 120 - 122 . The ICR 120 is fed by the first auxiliary transformer, and the ICR 122 is fed by the second auxiliary transformer. The ICR 120 - 122 include rectifiers 124 a - 124 b , respectively, and regulators 126 a - 126 , respectively. Each rectifier 124 a - 124 b receives a voltage from the associated auxiliary transformer and rectifies the voltage. Each regulator 126 a - 126 b regulates the current flowing through the associated ICR 120 - 122 . Each rectifier 124 a - 124 b includes any suitable structure for rectifying a signal, such as an uncontrolled bridge rectifier. Each regulator 126 a - 126 b includes any suitable structure for regulating a current flow, such as a pulse width modulation (PWM) controlled MOSFET or IGBT. Note, however, that each ICR 120 - 122 could be implemented using any other converter topology, such as a buck converter topology.

As noted above, the power converter 100 includes first and second auxiliary transformers. The first auxiliary transformer is formed using transformer windings 128 - 132 (denoted Ta 1 - 1 through Ta 1 - 3 ). The transformer winding 128 is coupled between the transistors 108 a - 110 a and the transistors 112 a - 114 a in the SRC bridge 104 , and the transformer winding 130 is coupled between the transistors 108 b - 110 b and the transistors 112 b - 114 b in the SRC bridge 106 . The transformer winding 132 is coupled to the rectifier 124 a in the ICR 120 . In particular embodiments, the windings 128 - 130 can have an equal number of turns, and the winding 132 can have a greater number of turns.

The second auxiliary transformer is formed using transformer windings 134 - 138 (denoted Ta 2 - 1 through Ta 2 - 3 ). The transformer winding 134 is coupled between the transistors 108 a - 110 a in the SRC bridge 104 and the transistors 112 b - 114 b in the SRC bridge 106 . The transformer winding 136 is coupled between the transistors 108 b - 110 b in the SRC bridge 106 and the transistors 112 a - 114 a in the SRC bridge 104 . The transformer winding 138 is coupled to the rectifier 124 b in the ICR 122 . In particular embodiments, the windings 134 - 136 can have an equal number of turns, and the winding 138 can have a greater number of turns.

The transformer windings 128 - 130 here are said to be coupled to SRC bridge “diagonals,” meaning they would lie on diagonals of a square if the transistors 108 a - 114 a or 108 b - 114 b were arranged in a square configuration. The diagonals are defined as the path directly between nodes A and B in the SRC bridge 104 and the path directly between nodes A 1 and B 1 in the SRC bridge 106 . Also, the transformer windings 134 - 136 here are said to be “cross-bridge” windings since they are connected to multiple SRC bridges 104 - 106 . The cross-bridge paths are defined as the path directly between nodes A and A 1 in the SRC bridges 104 - 106 and the path directly between nodes B and B 1 in the SRC bridges 104 - 106 .

In this arrangement, the primary SRC bridges 104 - 106 and the transformer windings form an inductor-linked dual SRC design. The ICRs 120 - 122 represent regulated inverse rectifiers connected to an input source (the source providing the input voltage). During operation, energy flows from the input source through the primary SRC bridges 104 - 106 . This creates a voltage and a current flow in the secondary bridges 116 - 118 , providing the DC output. Part of the energy flowing through the primary SRC bridges 104 - 106 can flow into the ICRs 120 - 122 via the transformer windings. The ICRs 120 - 122 therefore take energy from the switching nodes A, A 1 , B, and B 1 and send it back to the input source. The reactive (“circulating”) energy flow provides ZVS assistance to the primary SRC bridges 104 - 106 when needed.

As noted above, each regulator 126 a - 126 b could be implemented using a transistor, such as a PWM-controlled MOSFET or IGBT. To help reduce power losses in the power converter 100 , pre-shaped voltages can be applied to the transistors forming the regulators 126 a - 126 b . The pre-shaped voltages can enable zero-loss or substantially zero-loss turn-off commutation for the transistors forming the regulators 126 a - 126 b . If the regulators 126 a - 126 b operate with discontinuous currents, their dominant switching losses can be caused by the discharge of their equivalent capacitances at turn-on. The pre-shaped voltages feeding the regulators 126 a - 126 b can be derived from the primary SRC bridges 104 - 106 .

FIG. 2 illustrates the power converter 100 along with associated control circuitry 200 . The control circuitry 200 in this example includes a PSM controller 202 for the bridges 104 - 106 , 116 - 118 and a PWM controller 204 for the regulators 126 a - 126 b . The PSM controller 202 receives measurements of the power converter's input and output voltages and input and output currents. Using that information, the PSM controller 202 generates gate pulses for controlling the various transistors in the bridges 104 - 106 , 116 - 118 . The PSM controller 202 includes any suitable structure for controlling other structures using phase-shift modulation.

The PWM controller 204 receives a feedback signal, such as one or more direct measurements of the currents flowing through the transistors 108 a - 114 a , 108 b - 114 b in the primary SRC bridges 104 - 106 . For each feedback signal, an error amplifier 206 amplifies a difference between the feedback signal and a reference signal, and a comparator 208 compares an output of the error amplifier 206 to an output of a voltage ramp generator 210 . A latch 212 captures an output of the comparator 208 based on a clock signal from an oscillator 214 . Digital logic 216 processes the captured comparator output, and gate drivers 218 are used to drive the transistors in the regulators 126 a - 126 b . The PWM controller 204 includes any suitable structure for controlling other structures using pulse width modulation.

In some embodiments, the regulators' currents in the ICRs 120 - 122 lead the corresponding SRC currents in the primary SRC bridges 104 - 106 , so the PWM controller 204 controls the ICRs 120 - 122 using leading-edge PWM control. The error amplifier 206 can compare the measured transistor currents with reference values corresponding to the charges used to provide ZVS of the given nodes (A, A 1 , B, and B 1 ). Each pair of transistors in the primary SRC bridges 104 - 106 (Q 1 and Q 1 ′, Q 2 and Q 2 ′, Q 3 and Q 3 ′, and Q 4 and Q 4 ′) can be driven using identical gate drive signals.

As can be seen in FIG. 2 , the bridges 104 - 106 and 116 - 118 can be controlled using phase-shift modulation, while the regulators 126 a - 126 b can be controlled using pulse width modulation. The pulse width modulation is used to ensure that the ICRs 120 - 122 provide assistance currents when needed, and the assistance currents are independently controlled using the PWM controller 204 .

FIGS. 3A and 3B illustrate a more detailed circuit schematic of one possible implementation of the power converter 100 . As shown in FIGS. 3A and 3B , an input voltage V IN creates the DC input across the input capacitor 102 . Two series-coupled capacitors Cq 1 and Cq 2 are coupled to node A of the primary SRC bridge 104 , and two series-coupled capacitors Cq 3 and Cq 4 are coupled to node B of the primary SRC bridge 104 . The capacitors Cq 1 and Cq 2 are coupled in parallel across the transistors 108 a - 114 a , and the capacitors Cq 3 and Cq 4 are coupled in parallel across the transistors 108 a - 114 a . Additional capacitors Cq 1 ′-Cq 4 ′ are coupled to nodes A 1 and B 1 of the primary SRC bridge 106 in a similar arrangement. Each transistor 108 a - 114 a , 108 b - 114 b in the primary SRC bridges 104 - 106 is also coupled in parallel with an associated diode.

The primary SRC bridge 104 also includes four additional diodes D 1 -D 4 . Diodes D 1 -D 2 are coupled in series, and diodes D 3 -D 4 are coupled in series. Diodes D 1 -D 2 are also coupled to node A via a resonant inductor L r1 and a transformer winding T 1 - 1 , which represents a winding of a first main transformer. Diodes D 3 -D 4 are also coupled to node B via a resonant inductor L r2 and a transformer winding T 1 - 2 , which represents another winding of the first main transformer. The diodes D 1 -D 4 are further coupled to a resonant capacitor C r . The primary SRC bridge 106 has a similar design with diodes D 1 ′-D 4 ′, resonant inductors L r1 ′ and L r2 ′, and resonant capacitor C r ′. Also, T 2 - 1 and T 2 - 2 represent windings of a second main transformer.

The transformer winding 128 is coupled in series with a capacitor Ca 1 , and the transformer winding 130 is coupled in series with a capacitor Ca 2 . The transformer winding 134 is coupled in series with a capacitor Ca 1 ′ between nodes A and A 1 , and the transformer winding 136 is coupled in series with a capacitor Ca 2 ′ between nodes B and B 1 .

As shown in FIGS. 3A and 3B , the secondary bridge 116 is electrically coupled to the primary SRC bridge 104 using a transformer winding T 1 - 3 , which represents a third winding of the first main transformer. Similarly, the secondary bridge 118 is electrically coupled to the primary SRC bridge 106 using a transformer winding T 2 - 3 , which represents a third winding of the second main transformer. Each secondary bridge 116 - 118 is implemented using two pairs of transistors, where each transistor pair is coupled in parallel with an output capacitor C OUT . An output voltage V OUT is created across the output capacitor C OUT .

In the ICR 120 , the rectifier 124 a includes four diodes Da 1 -Da 4 . Diodes Da 1 -Da 2 are coupled in series, and diodes Da 3 -Da 4 are coupled in series. The transformer winding 132 and a capacitor Ca 3 are connected to a node between the diodes Da 1 -Da 2 , and an auxiliary inductor La 1 (an AC inductor) and a resistor Ra 1 are connected to a node between the diodes Da 3 -Da 4 . The transformer winding 132 and the auxiliary inductor La 1 are coupled in series, and the capacitor Ca 3 and the resistor Ra 1 are coupled in series. The rectifier 124 b in the ICR 122 has the same design with diodes Da 1 ′-Da 4 ′, capacitor Ca 4 , auxiliary inductor La 2 (an AC inductor), resistor Ra 2 , and the transformer winding 138 . The regulators 126 a - 126 b in the ICRs 120 - 122 are formed using transistors Qa 1 -Qa 2 , respectively, each of which has a parallel-coupled diode.

In this example, the voltage V A-B between nodes A and B and the voltage V A1-B1 between nodes A 1 and B 1 are coupled to the regulator 126 a through the auxiliary transformer Ta 1 . This provides an assist to the leading SRC transistors Q 1 , Q 2 , Q 1 ′, and Q 2 ′. Also, the voltage V A-A1 between nodes A and A 1 and the voltage V B-B1 between nodes B and B 1 are coupled to the regulator 126 b through the auxiliary transformer Ta 2 . This provides an assist to the lagging SRC transistors Q 3 , Q 4 , Q 3 ′, and Q 4 ′.

As noted above, each ICR 120 - 122 could be implemented using any other converter topology, such as a buck converter topology. If a buck converter topology is used, each auxiliary inductor La 1 -La 2 in the ICRs 120 - 122 can be moved from the diagonal of the ICR bridge rectifier to the DC side at the output of the rectifier.

Each component shown in FIGS. 3A and 3B could be implemented in any suitable manner. For example, Table 1 provides example values or types for different components or parameters in FIGS. 3A and 3B .

Note, however, that the power converter 100 could be implemented in any other suitable manner.

The power converter 100 could be used in a wide range of applications. For example, the power converter 100 could form part of a galvanically-isolated power converter. The power converter 100 could also be used in high-density power converters and micro-grids. The power converter 100 could be used in any other suitable application.

Although FIGS. 1 through 3B illustrate one example of a power converter 100 with a high efficiency ZVS assistance circuit and related details, various changes may be made to FIGS. 1 through 3B . For example, the power converter 100 in FIG. 1 uses the ICRs 120 - 122 connected only to the primary SRC bridges 104 - 106 . However, ICRs could be coupled only to the secondary bridges 116 - 118 , or ICRs could be coupled to both the primary SRC bridges 104 - 106 and the secondary bridges 116 - 118 . Also, any other control circuitry could be used in conjunction with the power converter 100 , and the circuitry shown in FIGS. 3A and 3B represents one example way of implementing the power converter 100 and does not limit the scope of this disclosure. Further, any type of converter bridges could be used, and the ZVS assistance circuit is not limited to use with SRC bridges. In addition, note that the numbers of components in the power converter 100 are for illustration only and other number(s) of component(s) could be used. For instance, the power converter 100 could include more than two primary SRC bridges, more than two secondary SRC bridges, and more than two ICRs.

FIGS. 4 through 15 illustrate example operational characteristics of a power converter with a high efficiency ZVS assistance circuit according to this disclosure. In particular, FIGS. 4 through 15 illustrate operational characteristics that can be achieved using a particular implementation of the power converter 100 , namely the implementation shown in FIGS. 3A and 3B . Note, however, that other power converters with ZVS assistance circuits could have different operational characteristics depending on their implementations.

FIG. 4 illustrates example operation of the power converter 100 at no load or light load (such as at 1% or less of full load). Here, VgateQ 1 -VgateQ 4 and VgateQ 1 ′-VgateQ 4 ′ represent the voltages placed on the gates of the transistors 108 a - 114 a , 108 b - 114 b in the SRC bridges 104 - 106 . Also, VReg 1 and VReg 2 represent the voltages across the regulators 126 a - 126 b . When operating in this manner, the power converter 100 supplies nearly all current for recharging the capacitances (including self-capacitances) of the transistors 108 a - 114 a , 108 b - 114 b in the SRC bridges 104 - 106 , and pulses in the VReg 1 and VReg 2 signals have a maximum width. This corresponds to the largest leading phase angle between pulses in the VReg 1 and VReg 2 signals and pulses in the VgateQ 1 -VgateQ 4 and VgateQ 1 ′-VgateQ 4 ′ signals.

FIG. 5 illustrates the currents in the power converter 100 under no or light load. Here, IQ 1 and IQ 4 denote the currents through the transistors 108 a / 108 b and 114 a / 114 b , and VQ 1 and VQ 4 denote the voltages across the transistors 108 a / 108 b and 114 a / 114 b . Also, ICQ 1 and ICQ 4 denote the currents through the capacitors Cq 1 and Cq 4 , and Ireg 1 and Ireg 2 denote the currents through the regulators 126 a - 126 . As seen here, the regulator currents Ireg 1 and Ireg 2 start ramping up from zero ahead of the currents in the SRC transistors 108 a / 108 b and 114 a / 114 b . Note that the peak ZVS assistance current corresponds to the peak transistor current.

FIG. 6 illustrates operating conditions with respect to the transistors Qa 1 -Qa 2 in the regulators 126 a - 126 b under no or light load. Here, VgateReg 1 and VgateReg 2 represent the voltages placed on the gates of the transistors Qa 1 -Qa 2 in the regulators 126 a - 126 b , VReg 1 and VReg 2 represent the voltages across the regulators 126 a - 126 b , and IReg 1 and IReg 2 represent the currents through the regulators 126 a - 126 b . Also, Rect(Va−Va 1 ) represents the rectified difference between the voltages at nodes A and A 1 , and Rect(Va−Vb) represents the rectified difference between the voltages at nodes A and B. As shown here, the transistors Qa 1 -Qa 2 in the regulators 126 a - 126 b work in discontinuous conduction. Because their drain voltages decay to zero prior to turn-off, the only source of switching losses can be the discharge of transistor capacitance at turn-on. The low switching stress allows the application of higher voltages (and lower currents) to the regulators 126 a - 126 b , as well as the use of slower higher-voltage devices (such as IGBTs).

FIG. 7 illustrates operating conditions with respect to the diodes in the regulators 126 a - 126 b under light load. Here, VDReg 1 and VDReg 2 represent the voltages placed on the diodes in the regulators 126 a - 126 b , and IDReg 1 and IDReg 2 represent the currents through the diodes in the regulators 126 a - 126 b . The diodes in the regulators 126 a - 126 b can operate with near-zero losses, allowing the use of relatively slow components. Note that two avalanche-rated lower voltage components may be series-connected and used in place of the diodes to sustain the stepped-up voltage.

FIGS. 8-11 illustrate example operations of the power converter 100 and its components at full load (100%). In this case, the SRC bridges 104 - 106 need minimum or no ZVS assistance, and pulses in the gate signals for the transistors Qa 1 -Qa 2 in the regulators 126 a - 126 b are at a minimum. As expected, the magnitude of the ICR currents is reduced accordingly. This condition corresponds to increased pulse widths of the source voltage applied to the bridge diagonals (V A-B and V A1-B1 ) and reduced pulse widths of the cross-bridge voltages (V A-A1 and V B-B1 ).

FIGS. 12-15 illustrate example operations of the power converter 100 and its components at full load with zero regulator pulse widths. In this case, the ICR currents are reduced to zero. This may occur when the ZVS assistance network is shut down to maintain high efficiency when a sufficient load current is available.

Although FIGS. 4 through 15 illustrate examples of operational characteristics of a power converter with a high efficiency ZVS assistance circuit, various changes may be made to FIGS. 4 through 15 . For example, as noted above, the operational characteristics shown here are associated with a particular implementation of the power converter 100 , and other implementations could be used.

FIG. 16 illustrates an example method 1600 for providing ZVS assistance for a power converter according to this disclosure. As shown in FIG. 16 , an input signal is received at a first primary converter bridge at step 1602 . This could include, for example, providing a DC input signal to a first primary SRC bridge 104 . Energy from the input signal is passed through the first primary converter bridge and a second primary converter bridge at step 1604 . This could include, for example, passing energy from the DC input signal through the primary SRC bridges 104 - 106 . This causes the generation of an output signal via first and second secondary converter bridges at step 1606 . This could include, for example, generating a DC output signal using the secondary SRC bridges 116 - 118 . Current flow can be created in the secondary SRC bridges 116 - 118 via main transformer windings T 1 - 3 and T 2 - 3 .

During this time, input energy is passed from the primary converter bridges to ICRs at step 1608 . This could include, for example, passing the input energy to the ICRs 120 - 122 via the auxiliary transformer windings Ta 1 - 1 through Ta 1 - 3 and Ta 2 - 1 through Ta 2 - 3 . Assistance currents are provided to the converter bridges using the ICRs as needed at step 1610 . This could include, for example, the ICRs 120 - 122 providing currents to the transistors 108 a - 114 a , 108 b - 114 b in the primary SRC bridges 104 - 106 . As noted above, however, ICRs could alternatively or also provide currents to transistors in the secondary bridges 116 - 118 . The regulators 126 a - 126 b could receive pre-shaped voltages during this time to help provide substantially zero-loss operation of the ICRs 120 - 122 .

Although FIG. 16 illustrates one example of a method 1600 for providing ZVS assistance for a power converter, various changes may be made to FIG. 16 . For example, while shown as a series of steps, various steps in FIG. 16 can overlap, occur in parallel, occur in a different order, or occur multiple times.

It may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and/or. The phrase “associated with,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, have a relationship to or with, or the like.

While this disclosure has described certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of example embodiments does not define or constrain this disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure, as defined by the following claims.