Display apparatus

This application is the Continuation of International Application No. PCT/JP2012/005002, filed on Aug. 7, 2012, which in turn claims the benefit of Japanese Application No. 2011-173508, filed on Aug. 9, 2011, the disclosures of which Applications are incorporated by reference herein.

The present disclosure relates to an active-matrix display apparatus employing a current light emitting device.

An organic EL (electroluminescence) display apparatus has a large number of arrayed self-luminous organic EL devices. The EL display apparatus does not require a backlight and does not have viewing angle restrictions. Accordingly, it has been developed as a next generation display apparatus.

The organic EL device is a current light emitting device which can control luminosity with an amount of current flow. Methods for driving the organic EL device include a simple-matrix method and an active-matrix method. The simple-matrix method needs only a simple pixel circuit but it is difficult to achieve a large-sized and high definition display. For this reason, recently the active-matrix organic EL display apparatus, which employs driving transistors for every pixel circuit, is mainly used.

The driving transistor and the peripheral circuit are formed generally of TFT (Thin Film Transistors) made of poly-silicon or amorphous silicon. Although TFT has the disadvantage of a high threshold voltage fluctuation due to its low mobility, it is suitable for a large-sized organic EL display apparatus because large sized TFT is easy to make and the cost of TFT is low. Further, a method for overcoming the disadvantage (fluctuation of threshold voltage) has been studied by improving a pixel circuit. For example, Patent Literature JP2009-169145A1, describes an organic EL display apparatus which compensates the threshold voltage of the driving transistor.

The compensation of threshold voltage is performed as follows. First, a voltage larger than the threshold voltage is applied between the gate and source of the driving transistor in order to generate current-flow in the transistor and to discharge a capacitor connected between the gate and source of the driving transistor. The current in the driving transistor stops flowing when a terminal to terminal voltage of the capacitor (i.e. voltage between two terminals of the capacitor) decreases to the threshold voltage of the driving transistor. Then, this terminal to terminal voltage is added to an image signal. An image is thereby displayed independently of the threshold voltage of the driving transistor.

If the terminal to terminal voltage of the capacitor is much higher than the threshold voltage, the capacitor is discharged rapidly because the current flowing in the driving transistor is large. However, as the terminal to terminal voltage of capacitor decreases toward the threshold voltage, the amount of the current flowing in the driving transistor decreases. As a result, the discharging speed of capacitor becomes slow. Thus, a long time is required before the terminal to terminal voltage of capacitor falls to the threshold voltage of the driving transistor. Practically, 10-100 micro-seconds, for example, may be required.

However, according to the pixel circuit and the driving method described in the JP2009-169145A1, a data line for supplying an image signal is also used for compensating the threshold voltage. This limits the time available for the writing operation and makes it difficult to achieve a large-sized or high definition display apparatus having a large numbers of pixels.

The present disclosure relates to a display apparatus having an arrayed pixel circuits, each of the pixel circuits includes:

a current light emitting device;

a driving transistor supplying current to the current light emitting device;

a first capacitor having a first terminal connected with a gate of the driving transistor;

a second capacitor connected between a second terminal of the first capacitor and a source of the driving transistor;

a first switch applying a reference voltage to a node of the first capacitor and the second capacitor to which the first capacitor and the second capacitor are connected;

a second switch supplying an image signal voltage to the gate of the driving transistor;

a third switch supplying an initialization voltage to the source of the driving transistor, and

a fourth switch short circuiting the node of the first and second capacitor and the gate of the driving transistor; or applying the reference voltage to the gate of the driving transistor.

Foregoing structure allows achieving writing operation at a high speed, and compensating the threshold value voltage of the driving transistor.

FIG. 1 is a block diagram illustrating a structure of the display apparatus according to a first embodiment.

FIG. 2 is a circuit diagram of a pixel circuit of the display apparatus.

FIG. 3 is a timing diagram illustrating an operation of the display apparatus.

FIG. 4 is a timing diagram illustrating an operation of the pixel circuit of the display apparatus.

FIG. 5 is a circuit diagram for illustrating an operation of the pixel circuit during the initialization period.

FIG. 6 is a circuit diagram for illustrating an operation of the pixel circuit during the threshold detecting period.

FIG. 7 is a circuit diagram for illustrating an operation of the pixel circuit during the writing period.

FIG. 8 is a circuit diagram for illustrating an operation of the pixel circuit during the luminescence period.

FIG. 9 is a circuit diagram of a pixel circuit of the display apparatus according to a second embodiment.

FIG. 10 is a circuit diagram of a pixel circuit of the display apparatus according to a third embodiment.

FIG. 11 is a timing diagram illustrating an operation of the pixel circuit.

FIG. 12 is a circuit diagram of a pixel circuit of the display apparatus according to a fourth embodiment.

FIG. 13 is a timing diagram illustrating an operation of the pixel circuit.

The embodiments of a display apparatus of the present disclosure will be described hereafter with reference to the drawings. The present disclosure describes an active-matrix organic EL display apparatus which drives EL devices using a driving transistor, as an example of the display apparatus.

The present disclosure is not limited to the organic EL display apparatus and may be applicable to various active-matrix display apparatus employing an arrayed pixel circuits having a current light emitting device that controls luminosity with an amount of current flow and a driving transistor which supplies current to the current light emitting device.

First Embodiment

FIG. 1 is a block diagram illustrating a structure of display apparatus 10 according to the first embodiment. Display apparatus 10 has a large number of arrayed (n-rows, m-column) pixel circuits 12 (i, j) (1<=i<=n and 1<=j<=m), source driving circuit 14 , gate driving circuit 16 , and power supply circuit 18 .

As shown in FIG. 1 , source driving circuit 14 supplies image signal voltage Vsg (j) to each of data lines 20 (j) that is connected commonly to pixel circuits 12 (1, j) to 12 (n, j) (j represents each of the pixel columns 1 to m, m being the highest number). The pixel circuits 12 (1, j) to 12 (n, j) are aligned in column. Gate driving circuit 16 supplies control signals CNT 21 (i), CNT 22 (i), CNT 25 (i), CNT 26 (i), CNT 27 (i) to control signal lines 21 (i), 22 (i), 25 (i), 26 (i), 27 (i) which are connected commonly to pixel circuits 12 (i, 1) to 12 (i, m) (i represents each of the pixel rows 1 to n, n being the highest number). The pixel circuits 12 (i, 1) to 12 (i, m) are aligned in row direction. In this embodiment, four kinds of control signals CNT 21 (i) to CNT 24 (i) are supplied to one pixel circuit 12 (i, j). However, the number of control signals is not limited to four.

Power supply circuit 18 supplies the high-voltage Vdd to power source lines 31 and the low-voltage Vss to power source lines 32 . These power source lines are connected to all pixel circuits 12 (1, 1) to 12 (n, m). The voltages Vdd and Vss are provided so that the organic EL device, which is described later, can emit light. Reference voltage Vref is supplied to voltage line 33 which are connected to all of pixel circuits 12 (i, j). Initialization voltage Vint is supplied to voltage line 34 which are also connected to all of pixel circuits 12 (i, j).

FIG. 2 is a circuit diagram of pixel circuit 12 (i, j) of display apparatus 10 of the first embodiment. Pixel circuit 12 (i, j) has organic EL device D 20 (an example of a current light emitting device), driving transistor Q 20 , first capacitor C 21 , second capacitor C 22 , and transistors Q 21 to Q 24 which operate as switches.

Driving transistor Q 20 supplies current to organic EL device D 20 . First capacitor C 21 stores image signal voltage Vsg which varies in response to image signal (j). Transistor Q 22 is a switch for writing (charging) image signal voltage Vsg (i) to first capacitor C 21 . Second capacitor C 22 stores threshold voltage Vth of driving transistor Q 20 . Transistor Q 21 is a switch for applying reference voltage Vref to one terminal of first capacitor C 21 . Transistor Q 23 is a switch for applying initialization voltage Vint to one terminal of second capacitor C 22 .

All of driving transistor Q 20 and transistors Q 21 to Q 24 are N-channel TFT (Thin Film Transistors) and enhancement type transistors. However, present disclosure is not limited to such a configuration.

Pixel circuit 12 (i, j) has a structure that driving transistor Q 20 and organic EL device D 20 are connected between power source lines 31 and 32 . To be specific, a drain of driving transistor Q 20 is connected to power source line 31 , a source of driving transistor Q 20 is connected to an anode of organic EL device D 20 , and a cathode of organic EL device D 20 is connected to power source line 32 .

First capacitor C 21 and second capacitor C 22 are connected in series between a gate and source of driving transistor Q 20 . That is, one terminal (first terminal) of first capacitor C 21 is connected to the gate of driving transistor Q 20 , and second capacitor C 22 is connected between the other terminal (a second terminal) of first capacitor C 21 and the source of driving transistor Q 20 . Hereafter, a node to which the gate of driving transistor Q 20 and first capacitor C 21 are connected is called “node Tp 1 ”. A node to which first capacitor C 21 and second capacitor C 22 are connected is called “node Tp 2 ”. A node to which second capacitor C 22 and the source of transistor Q 20 are connected is called “node Tp 3 ”.

A drain of transistor Q 21 (first switch) is connected to voltage line 33 which supplies reference voltage Vref. A source of transistor Q 21 is connected to node Tp 2 . A gate of transistor Q 21 is connected to control signal line 21 (i). Transistor Q 21 thereby applies reference voltage Vref to node Tp 2 . Transistor Q 21 may be a P-channel TFT instead of the N-channel TFT. When the transistor is P-channel TFT, the positions of the gate and source are reverse to that of the N-channel TFT. The same can be applied to the transistors (Q 22 , Q 23 , Q 24 ) described below.

A drain of transistor Q 22 (second switch) is connected to node Tp 1 . A source of transistor Q 22 is connected to data line 20 (j) which supplies image signal voltage Vsg. A gate of transistor Q 22 is connected to control signal line 22 (i). Transistor Q 22 thereby supplies image signal voltage Vsg to the gate of driving transistor Q 20 .

A drain of transistor Q 23 (third switch) is connected to node Tp 3 . A source of transistor Q 23 is connected to voltage line 34 which supplies initialization voltage Vint. A gate of transistor Q 23 is connected to control signal line 23 (i). Transistor Q 23 thereby supplies initialization voltage Vint to the source of driving transistor Q 20 .

A drain of transistor Q 24 (fourth switch) is connected to node Tp 1 . A source of transistor Q 24 is connected to node Tp 2 . A gate of transistor Q 24 is connected to control signal line 24 (i). Transistor Q 24 thereby short-circuits node Tp 2 and the gate of driving transistor Q 20 .

Here, each of control signals CNT 21 (i) to CNT 24 (i) is supplied respectively to each of control signal lines 21 (i) to 24 (i).

As described above, pixel circuit 12 (i, j) in this embodiment includes:

first capacitor C 21 having a first terminal connected to a gate of driving transistor Q 20 ;

second capacitor C 22 connected between a second terminal of first capacitor C 21 and a source of driving transistor Q 20 ;

transistor Q 21 (first switch) supplying reference voltage Vref to node Tp 2 of the capacitors C 21 and C 22 ;

transistor Q 22 (second switch) applying image signal voltage Vsg to the gate of driving transistor Q 20 ;

transistor Q 23 (third switch) supplying initialization voltage Vint to the source of driving transistor Q 20 , and

transistor Q 24 (fourth switch) short-circuiting node Tp 2 and the gate of driving transistor Q 20 .

In this embodiment, the minimum voltage between anode and cathode for supplying current in organic EL device D 20 is 1(V)(this minimum voltage is called Vled hereafter). The capacity between anode and cathode when current does not flow in the organic EL device D 20 is 1 (pF). Threshold voltage Vth of driving transistor Q 20 is about 1.5(V). The electric capacity of first capacitor C 21 and second capacitor C 22 is 0.5 (pF). Regarding to the driving voltage, high-voltage Vdd is 10(V), low-voltage Vss is 0(V), reference voltage Vref is 1(V), and initialization voltage Vint is −1(V). However, these values may change according to the specification of the display apparatus or characteristic of each device. Thus, it is desirable to set the driving voltage optimally according to the specification of the display apparatus or characteristic of the devices.

Next, the operation of pixel circuit 12 (i, j) according to this embodiment is described. FIG. 3 is a timing diagram illustrating an operation of display apparatus 10 of the first embodiment.

As shown in FIG. 3 , one frame period is divided into four periods (i.e. initialization period T 1 , threshold detecting period T 2 , writing period T 3 , and luminescence period T 4 ) in order to control organic EL device D 20 included in each of the pixel circuits 12 (i, j).

In initialization period T 1 , second capacitor C 22 is charged to a predetermined voltage.

In threshold detecting period T 2 , threshold voltage Vth of driving transistor Q 20 is detected.

In writing period T 3 , image signal voltage Vsg, which varies in response to image signal (j), is written (charged) to first capacitor C 21 .

In luminescence period T 4 , a sum of terminal to terminal voltages of first capacitor C 21 and second capacitor C 22 is applied between the gate and source of driving transistor Q 20 . This leads to generate a current-flow in organic EL device D 20 so that the device D 20 can emit light.

The timings of these four periods are set to same so that the pixel circuits belonging in the same row (i.e. pixel circuits 12 (i, 1) to 12 (i, m)) operates with same timings. Meanwhile, the timings of writing periods T 3 are set so that the periods T 3 in the different rows do not overlap each other. Accordingly, while a writing operation is being performed on one pixel row, the other pixel rows can execute an operation other than the writing. Thus, driving period can be used efficiently.

FIG. 4 is a timing diagram illustrating an operation of pixel circuit 12 (i, j) of display apparatus 10 according to the first embodiment. In FIG. 4 , changes of the voltages in nodes Tp 1 to Tp 3 are also illustrated. Hereafter, operation of pixel circuit 12 (i, j) is detailed for each of the divided period.

Initialization Period T 1

FIG. 5 is a circuit diagram for illustrating an operation of pixel circuit 12 (i, j) during initialization period T 1 . In FIG. 5 , transistors Q 21 to Q 24 (of FIG. 2 ) are shown by symbols of switches. The path through which current does not flow is shown in dotted line.

At time t 1 , while control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF, control signals CNT 21 (i), CNT 23 (i), and CNT 24 (i) are set to high level to set transistors Q 21 , Q 23 , and Q 24 ON. Reference voltage Vref is thereby applied to node Tp 2 via transistor Q 21 , and to node Tp 1 via transistor Q 24 . Initialization voltage Vint is applied to node Tp 3 via transistor Q 23 .

Reference voltage Vref is set to a voltage lower than a sum of low-voltage Vss and voltage Vled, i.e. Vref<Vss+Vled. Accordingly, organic EL device D 20 does not emit light during initialization period T 1 because source voltage of driving transistor Q 20 is lower than voltage (Vss+Vled).

Initialization voltage Vint is set to a voltage such that the difference from reference voltage Vref is larger than threshold voltage Vth of driving transistor Q 20 . When transistors Q 21 , Q 24 and Q 23 are turned ON, voltage Vref is applied to first terminal, and voltage Vint is applied to the second terminal of second capacitor C 22 . That is, voltage (Vref−Vint) is charged to second capacitor C 22 . Accordingly, the voltage (Vref−Vint) is also charged between the gate and source of driving transistor Q 20 . Since the voltage (Vref−Vint) is higher than the threshold voltage Vth of the driving transistor, as derived from the Condition 2 , a current is supplied from the power supply of high-voltage Vdd to the power supply of initialization voltage Vint via driving transistor Q 20 and transistor Q 23 .

In this embodiment, initialization period T 1 is set to 1 micro second.

Threshold Detection Period T 2

FIG. 6 is a circuit diagram for illustrating an operation during threshold detection period T 2 in pixel circuit 12 (i, j) of the first embodiment.

At time t 2 , control signal CNT 23 (i) is set to low level to set transistor Q 23 OFF. At this point, current flows continuously in driving transistor Q 20 because the terminal to terminal voltage of second capacitor C 22 (this terminal to terminal voltage is referred to as voltage V 22 hereafter) is applied between the gate and source of driving transistor Q 20 . Due to this current, second capacitor C 22 is discharged and voltage V 22 starts decreasing.

While the voltage V 22 is higher than threshold voltage Vth, current keeps flowing although the amount of the current continues to decrease in driving transistor Q 20 . Voltage V 22 thereby decreases gradually to threshold voltage Vth. When the voltage V 22 falls to threshold voltage Vth, the current in driving transistor Q 20 stops flowing. The voltage V 22 also stops decreasing.

The current flowing in driving transistor Q 20 decreases as the voltage V 22 decreases because the driving transistor Q 20 operates as a current source which is controlled by the voltage applied between the gate and source of driving transistor Q 20 (this voltage is referred to as “G-S voltage” hereafter). As a result, a long time is required before voltage V 22 falls to threshold voltage Vth. Moreover, the long time requirement is further caused because the large electric capacity of organic EL device D 20 is added to the electric capacity of second capacitor C 22 . Practically, this takes 10 to 100 times longer than the case of discharging the capacitor by transistor-switching. For this reason, threshold detection period T 2 is set to 10 micro seconds in this embodiment.

Writing Period T 3

FIG. 7 is a circuit diagram for illustrating an operation of pixel circuit 12 (i, j) during writing period T 3 according to the first embodiment.

At time t 3 , control signal CNT 24 (i) is set to low level to set transistor Q 24 OFF. Then, control signal CNT 22 (i) is set to high level to set transistor Q 22 ON. As a result, the voltage of node Tp 1 turns to image signal voltage Vsg (j), and voltage (Vref−Vsg) is charged between two terminals of first capacitor C 21 . Hereafter, this voltage (Vref−Vsg) is referred to as image signal voltage Vsg′.

At this point, voltage (Vsg′+Vth) is applied between the gate and source of driving transistor Q 20 . This voltage is equivalent to a sum of the voltages charged in the first capacitor C 21 and the second capacitor C 22 (i.e. image signal voltage Vsg′ is charged to the capacitor C 21 ; and threshold voltage Vth is charged to the capacitor C 22 ). While image signal voltage Vsg′ is larger than zero, current flows in driving transistor Q 20 because the voltage applied between the gate and source of driving transistor Q 20 is higher than threshold voltage Vth of the transistor Q 20 . Due to this current, the voltage V 22 decreases. However, the decrease in voltage V 22 is only a little because writing period T 3 is set to very short time (less than 1 micro second).

Luminescence Period T 4

FIG. 8 is a circuit diagram for illustrating an operation of pixel circuit 12 (i, j) during luminescence period T 4 .

At time t 4 , control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF. Control signal CNT 21 (i) is set to low level to set transistor Q 21 OFF. Consequently, nodes Tp 1 to Tp 3 temporarily enter a floating state and voltage (Vsg′+Vth), which is higher than threshold voltage Vth is applied between the gate and source of driving transistor Q 20 . Accordingly, a current corresponding to the G-S voltage of driving transistor Q 20 is supplied to organic EL device D 20 .

At this point, the current (I) satisfies I=K*(VGS−Vth)=K*Vsg′ (where, VGS is the G-S voltage, and K is a constant value), and is free from threshold voltage Vth.

As discussed above, current flowing in organic EL device D 20 is not influenced by threshold voltage Vth. Therefore, the current flowing in organic EL device D 20 is free from dispersion of threshold voltage Vth of driving transistor Q 20 . Further, even when threshold voltage Vth changes with the time, organic EL device D 20 can emit light with luminosity corresponding to the image signal.

After luminescence period T 4 , non-light emitting period can be provided. This period can be achieved by turning ON one of the transistors Q 21 , Q 23 , and Q 24 .

In threshold detection period T 2 , it is desirable to turn transistor Q 24 ON. However, if the leakage current of first capacitor C 21 is negligible, transistor Q 24 can be set to OFF. In this case, control signals CNT 24 (i) and CNT 23 (i) can be shared because the transistors Q 23 and Q 24 can be controlled by the same signal.

Second Embodiment

The structure of display device 10 in the second embodiment is similar to that of the first embodiment illustrated in FIG. 1 . However, structure of pixel circuit 12 (i, j) differs from that of first embodiment.

FIG. 9 is a circuit diagram of pixel circuit 12 (i, j) of display apparatus 10 according to the second embodiment. In the description of this embodiment, components which were described earlier in the first embodiment have the same reference numerals and may not be described in detail. Pixel circuit 12 (i, j) has organic EL device D 20 , driving transistor Q 20 , first capacitor C 21 , second capacitor C 22 , and transistors Q 21 to Q 23 which operate as switches.

However, in the second embodiment, transistor Q 44 , (fourth switch) which applies reference voltage Vref to a gate of driving transistor Q 20 , is provided instead of transistor Q 24 (which short-circuits between node Tp 2 and the gate of driving transistor Q 20 ). A drain of transistor Q 44 is connected to voltage line 33 which supplies reference voltage Vref, a source of transistor Q 44 is connected to node Tp 1 , and the gate of transistor Q 44 is connected to control signal line 44 (i) which supplies control signal CNT 44 (i).

Next, an operation of pixel circuit 12 (i, j) in the second embodiment is described. Similarly to the first embodiment, one-frame period is divided into four periods (i.e. initialization period T 1 , threshold detection period T 2 , writing period T 3 , and luminescence period T 4 ). The timing diagram of image signal voltage Vsg (j), control signals CNT 21 (i), CNT 22 (i), and CNT 23 (i) are the same as those of first embodiment shown in FIG. 4 . The timing diagram of control signal CNT 44 (i) is same as control signal CNT 24 (i) of the first embodiment shown in FIG. 4 .

Initializing Period T 1

At time t 1 , while control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF, control signals CNT 44 (i), CNT 21 (i), and CNT 23 (i) are set to high level to set transistors Q 44 , Q 21 , and Q 23 ON. Reference voltage Vref is thereby applied to node Tp 1 via transistor Q 44 and to node Tp 2 via transistor Q 21 . Initialization voltage Vint is applied to node Tp 3 via transistor Q 23 .

Consequently, second capacitor C 22 is charged to voltage (Vref−Vint) which is higher than threshold voltage Vth, similarly to the first embodiment. This leads to apply a voltage higher than threshold voltage Vth (i.e. Vref−Vint) between the gate and source of driving transistor Q 20 so that the current corresponding to the G-S voltage is supplied from power line 31 to voltage line 34 via driving transistor Q 20 and transistor Q 23 .

In this embodiment, initialization period T 1 is also set to 1 micro second.

Threshold Detecting Period T 2

At time t 2 , control signal CNT 23 (i) is set to low level to set transistor Q 23 OFF. Second capacitor C 22 is thus discharged, and voltage V 22 falls toward threshold voltage Vth.

Similarly to the first embodiment, threshold detection period T 2 is set to 10 micro seconds because a long time is required before the voltage V 22 falls to threshold voltage Vth.

Writing Period T 3

At time t 3 , control signal CNT 44 (i) is set to low level to set transistor Q 44 OFF. Then, similarly to the first embodiment, control signal CNT 22 (i) is set to high level to set transistor Q 22 ON. Voltage of node Tp 1 then turns to image signal voltage Vsg (j), and terminal to terminal voltage of the first capacitor C 21 turns to voltage (Vref−Vsg) which corresponds to image signal voltage Vsg′.

Writing period T 3 is set to 1 micro second in this embodiment also.

Luminescence Period T 4

The operation during luminescence period T 4 is similar to that described in the first embodiment. At time t 4 , control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF, and control signal CNT 21 (i) is set to low level to set transistor Q 21 OFF. As a result, voltage (Vsg′+Vth) is applied between the gate and sources of driving transistor Q 20 . This leads to supply current to organic EL device D 20 having a current amount corresponding to the G-S voltage of driving transistor Q 20 .

As discussed above, transistor Q 44 is provided as a switch for applying reference voltage Vref to node Tp 1 instead of applying reference voltage Vref to node Tp 1 via transistor Q 24 . This structure also allows preventing an adverse influence originated from the dispersion of threshold voltage Vth of driving transistor Q 20 . Further, even when threshold voltage Vth changes with the time, organic EL device D 20 can emit light with luminosity corresponding to the image signal.

After luminescence period T 4 , a non-light emitting period can be provided. This period can be formed by turning ON one of the transistors Q 21 , Q 23 , and Q 44 .

In threshold detection period T 2 , it is desirable to turn transistor Q 44 ON. However, transistor Q 44 can be set to OFF if the leakage current of first capacitor C 21 is negligibly small. In this case, control signals CNT 44 (i) and CNT 23 (i) can be shared because transistors Q 23 and Q 44 can be controlled by the same signal.

According to the second embodiment, reference voltage Vref is applied to node Tp 1 via transistor Q 44 . However, voltage other than reference voltage Vref can be applied to node Tp 1 via transistor Q 44 .

Third Embodiment

The structure of display device 10 in the third embodiment is similar to that of first embodiment illustrated in FIG. 1 . However, structure of pixel circuit 12 (i, j) differs from that of first embodiment.

FIG. 10 is a circuit diagram of pixel circuit 12 (i, j) according to the third embodiment. In the description of this embodiment, components which were described earlier in the first embodiment have the same reference numerals and may not be described in detail. Pixel circuit 12 (i, j) has organic EL device D 20 , driving transistor Q 20 , first capacitor C 21 , second capacitor C 22 , and transistors Q 21 to Q 24 which operate as switches.

In the third embodiment, transistor Q 45 (fifth switch) for cutting off the current in organic EL device D 20 is further provided. To be specific, a drain of driving transistor Q 20 is connected to power source line 31 ; a source of driving transistor Q 20 is connected to a drain of transistor Q 45 ; a source of transistor Q 45 is connected to an anode of organic EL device D 20 ; a cathode of organic EL device D 20 is connected to power source line 32 , and a gate of the transistor Q 45 is connected with control signal line 45 (i) which supplies control signal CNT 45 (i).

Next, an operation of pixel circuit 12 (i, j) according to the third embodiment is described.

Similarly to the first embodiment, one-frame period is divided into four periods (i.e. initialization period T 1 , threshold detection period T 2 , writing period T 3 , and luminescence period T 4 ).

FIG. 11 is a timing diagram illustrating an operation of pixel circuit 12 (i, j) according to the third embodiment. Image signal voltage Vsg (j), control signals CNT 21 (i) to CNT 24 (i) are similar to those in the first embodiment shown in FIG. 4 .

Initialization Period T 1

At time t 1 , control signal CNT 45 (i) is set to low level to set transistor Q 45 OFF. Similarly to the first embodiment, control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF. Control signals CNT 21 (i), CNT 23 (i), and CNT 24 (i) are set to high level to set transistors Q 21 , Q 23 , and Q 24 ON. As a result, reference voltage Vref is applied to nodes Tp 1 and Tp 2 . Initialization voltage Vint is applied to node Tp 3 .

Similarly to the first embodiment, the second capacitor C 22 is thus charged to voltage (Vref−Vint) which is higher than threshold voltage Vth. Further, since transistor Q 45 is OFF, current corresponding to the G-S voltage of driving transistor Q 20 is supplied from power line 31 to voltage line 34 via driving transistor Q 20 and transistor Q 23 .

In this embodiment, initialization period T 1 is set to 1 micro second also.

Threshold Detecting Period T 2

At time t 2 , control signal CNT 23 (i) is set to low level to set transistor Q 23 OFF. Similarly to the first embodiment, second capacitor C 22 is thus discharged so that the voltage V 22 decreases to threshold voltage Vth.

Similarly to foregoing embodiments, threshold detection period T 2 is set to 10 micro seconds because a long time is required before the voltage V 22 falls to threshold voltage Vth.

Writing Period T 3

At time t 3 , control signal CNT 24 (i) is set to low level to set transistor Q 24 OFF, and control signal CNT 22 (i) is set to high level to set transistor Q 22 ON. As a result, voltage of node Tp 1 turns to image signal voltage Vsg (j) and first capacitor C 21 is charged to voltage (Vref−Vsg) which corresponds to image signal voltage Vsg′.

Writing period T 3 is set to 1 micro second in this embodiment also.

Luminescence Period T 4

At time t 4 , control signal CNT 45 (i) is set to high level to set transistor Q 45 ON. Then, similarly to the first embodiment, control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF. Control signal CNT 21 (i) is set to low level to set transistor Q 21 OFF. As a result, voltage (Vsg′+Vth) is applied between the gate and sources of driving transistor Q 20 , and the current corresponding to the G-S voltage of driving transistor Q 20 is supplied to organic EL device D 20 .

After the luminescence period T 4 , non-light emitting period can be provided. This period can be formed by turning transistor Q 45 off. This period can be formed also by turning transistor Q 23 ON after writing period T 3 , and then turning transistor Q 45 OFF. In this case, the non-lighting period can be returned to light emitting period again by restoring transistor Q 45 back to ON and then restoring transistor Q 23 to OFF.

In the third embodiment, transistor Q 45 (a switch for cutting off the current in organic EL device D 20 ) is provided on a source side of driving transistor Q 20 . The adverse influence caused by the dispersion in threshold voltage Vth of driving transistor Q 20 is thereby reduced. Further, even when threshold voltage Vth changes with the time, the organic EL device D 20 can emit light with luminosity corresponding to image signal.

Further, in the structure of the third embodiment, reference voltage Vref can be set larger than a sum of low-voltage Vss and voltage Vled of organic EL device D 20 because current in organic EL device D 20 can be cut off by setting transistor Q 45 OFF. For example, in this embodiment, high-voltage Vdd is 10(V), low-voltage Vss is 0(V), reference voltage Vref is 2(V), and initialization voltage Vint is 0(V). By setting each of the voltages as above, both of voltages Vss and Vint can be set to a ground voltage. Further, each of the voltages applied to pixel circuit 12 (i, j) can be a positive value or 0 (V).

In threshold detection period T 2 , it is desirable to set transistor Q 24 ON. However, if the leakage current of first capacitor C 21 is negligibly small, transistor Q 24 can be set to OFF. In this case, control signals CNT 24 (i) and CNT 23 (i) can be shared.

Fourth Embodiment

The structure of display device 10 in the fourth embodiment is similar to that of first embodiment illustrated in FIG. 1 . However, structure of pixel circuit 12 (i, j) differs from that of the first embodiment.

FIG. 12 is a circuit diagram of pixel circuit 12 (i, j) of display apparatus 10 according to the fourth embodiment. In the description of this embodiment, components which were described earlier in the first embodiment have the same reference numerals and may not be described in detail. As described in the first embodiment, pixel circuit 12 (i, j) of the present embodiment also has organic EL device D 20 , driving transistor Q 20 , first capacitor C 21 , second capacitor C 22 , and transistors Q 21 to Q 24 which operate as switches.

In the fourth embodiment, transistor Q 55 , which is a fifth switch for cutting off the current, is further provided between the drain of transistor Q 20 and the power supply of voltage Vdd in order to supply current to organic EL device 20 . A drain of driving transistor Q 55 is connected to power source line 31 ; a source of driving transistor Q 55 is connected to the drain of driving transistor Q 20 ; a source of driving transistor Q 20 is connected to an anode of organic EL device D 20 ; and a cathode of organic EL device D 20 is connected to power source line 32 , and a gate of transistor Q 55 is connected to control signal line 55 (i) which supplies control signal CNT 55 (i).

Next, an operation of pixel circuit 12 (i, j) according to the fourth embodiment is described.

Similarly to the first embodiment, one-frame period is divided into four periods, (i.e. initialization period T 1 , threshold detection period T 2 , writing period T 3 , and luminescence period T 4 ).

FIG. 13 is a timing diagram illustrating an operation of pixel circuit 12 (i, j) according to the fourth embodiment. The timing diagram of image signal voltage Vsg (j), control signals CNT 21 (i) to CNT 24 (i) are the same as those of the first embodiment shown in FIG. 4 .

Initialization Period T 1

Similarly to the first embodiment, at time t 1 , control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF. Control signals CNT 22 (i), CNT 23 (i), and CNT 24 (i) are set to high level to set transistors Q 21 , Q 23 , and Q 24 ON. Control signal CNT 55 (i) can be either low level or high level. Reference voltage Vref is thereby applied to nodes Tp 1 and Tp 2 . Initialization voltage Vint is applied to node Tp 3 .

Similarly to the first embodiment, voltage (Vref−Vint), which is higher than threshold voltage Vth, is charged to second capacitors C 22 . In this case, the current corresponding to the G-S voltage of driving transistor Q 20 is supplied from power supply line 31 to voltage line 34 via transistor Q 55 , driving transistor Q 20 , and transistor Q 23 by setting transistor Q 55 ON.

In this embodiment, initialization period T 1 is set to 1 micro second also.

Threshold Detection Period T 2

At time t 2 , control signal CNT 55 (i) is set to high level to set transistor Q 55 ON, and control signal CNT 23 (i) is set to low level to set transistor Q 23 OFF. As a result, current flows in driving transistor Q 20 because the voltage V 22 is applied between the gate and source of driving transistor Q 20 . Second capacitor C 22 is then discharged by this current, and voltage V 22 decreases toward threshold voltage Vth.

Threshold detection period T 2 is set to 10 micro seconds also in the fourth embodiment because a long time is required before the voltage V 22 falls to threshold voltage Vth.

Writing Period T 3

At time t 3 , control signal CNT 55 (i) is set low level to set transistor Q 55 OFF. Control signal CNT 24 (i) is set low level to set transistor Q 24 OFF. Further, control signal CNT 22 (i) is set to high level to set transistor Q 22 ON. As a result, voltage of node Tp 1 turns to image signal voltage Vsg (j) and voltage (Vref−Vsg) (which corresponds to image signal voltage Vsg′) is charged to first capacitor C 21 .

In this case, when image signal voltage Vsg′ is larger than zero, the voltage larger than threshold voltage Vth is applied between the gate and source of driving transistor Q 20 . However, current does not flow in driving transistor Q 20 because transistor Q 55 is OFF and voltage V 22 thereby does not change. Threshold voltage Vth of driving transistor Q 20 is compensated accurately because the voltage V 22 (i.e. voltage charged in second capacitor C 22 ) is maintained to the threshold voltage Vth which is fixed in threshold detecting period T 2 .

Luminescence Period T 4

At time t 4 , control signal CNT 55 (i) is set to high level to set transistor Q 55 ON. Thereafter, control signal CNT 22 (i) is set to low level to set transistor Q 22 OFF and control signal CNT 21 (i) set to low level to set transistor Q 21 OFF similarly to the first embodiment. Voltage (Vsg′+Vth), which is larger than threshold voltage Vth, is thereby applied between the gate and source of driving transistor Q 20 . Thus, the current corresponding to the G-S voltage of driving transistor Q 20 is supplied to organic EL device D 20 .

In the fourth embodiment, a non-light emitting period can be set as necessary having an adequate length at an adequate timing after writing period T 3 . In order to set the non-light emitting period, at time t 5 , control signal CNT 55 (i) is set to low level to set transistor Q 55 OFF. This stops organic EL device D 20 from emitting light because the current does not flow into driving transistor Q 20 . During the non-light emitting period, a current path for discharging first capacitor C 21 and second capacitor C 22 is cut off so that the amounts of voltages V 21 and V 22 are maintained. At time T 6 , the non-light emitting period returns to light emitting period T 4 by setting control signal CNT 55 (i) high level and turning transistor Q 55 ON.

As discussed above, in the fourth embodiment, transistor Q 55 (a switch for cutting off the current flowing into organic EL device D 20 ) is provided in the drain side of driving transistor Q 20 . This structure can also reduce an adverse influence caused by the dispersion of threshold voltage Vth of driving transistor Q 20 . Further, even when threshold voltage Vth changes with the time, organic EL device D 20 can emit light properly with luminosity corresponding to image signal.

In threshold detecting period T 2 , it is desirable to set transistor Q 24 ON. However, if leakage current of the first capacitor C 21 is negligibly small, transistor Q 24 can be set to OFF. In this case, control signals CNT 24 (i) and CNT 23 (i) can be shared.

Transistor Q 55 in the fourth embodiment is an N-channel TFT; however, transistor Q 55 can be formed by a P-channel TFT instead. Generally, P-channel TFT can make “ON resistance” small when voltage is high. This lowers power consumption of transistor Q 55 . In this context, “ON resistance” means resistance between the drain and source electrodes of transistor when transistor is ON.

According to the fourth embodiment, transistors Q 55 are provided for each of pixel circuits 12 (i, j) independently. Instead, one transistor Q 55 can be provided commonly for multiple pixel circuits 12 (i, j). For example, one transistor Q 55 can be provided for every pixel rows (i.e. pixel circuits 12 (i, 1)- 12 (i, m)) or can be provided for every multiple pixel rows.

Each of the numerical values such as voltages in the first to fourth embodiments are examples. These values may be set optimally based on characteristics of organic EL device or specification of the display apparatus.

The present disclosure is useful for an active-matrix display apparatus employing a current light emitting device.