Semiconductor integrated circuit

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2013-47194, filed on Mar. 8, 2013, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate to a semiconductor integrated circuit.

When power supply wires are arranged in a semiconductor integrated circuit, wires for VDD and wires for VSS are arranged in each routing layer, and wires in different routing layers are connected to each other by via plugs. In this case, if the power supply wires and the via plugs occupy many routing tracks in each routing layer, signal wire efficiency becomes lower. On the other hand, if the number of the power supply wires and the number of the via plugs are simply reduced in order to prevent the signal wire efficiency from becoming lower, a drop of the power supply voltage becomes larger.

FIG. 1 is a perspective view illustrating a structure of a semiconductor integrated circuit of a first embodiment;

FIG. 2 is a plan view illustrating the structure of the semiconductor integrated circuit of the first embodiment;

FIG. 3 is a perspective view illustrating a structure of a semiconductor integrated circuit of a second embodiment;

FIG. 4 is a plan view illustrating the structure of the semiconductor integrated circuit of the second embodiment;

FIG. 5 is another plan view illustrating the structure of the semiconductor integrated circuit of the second embodiment;

FIG. 6 is another perspective view illustrating the structure of the semiconductor integrated circuit of the second embodiment; and

FIGS. 7A and 7B are plan views for explaining a method of arranging M 4 power supply wires of the second embodiment.

Embodiments will now be explained with reference to the accompanying drawings.

In one embodiment, a semiconductor integrated circuit includes one or more power supply strap wires arranged in a first routing layer and extending in a first direction. The circuit further includes one or more auxiliary power supply strap wires arranged in a second routing layer below the first routing layer and extending in the first direction. The circuit further includes intermediate power supply wires arranged in a third routing layer between the first and second routing layers, each of the intermediate power supply wires electrically connecting one of the power supply strap wires to one of the auxiliary power supply strap wires. The circuit further includes power supply rails arranged in a fourth routing layer below the second routing layer, extending in a second direction perpendicular to the first direction, and electrically connected to the auxiliary power supply strap wires. The circuit further includes upper power supply strap wires arranged in a fifth routing layer above the first routing layer, extending in the second direction, and electrically connected to the power supply strap wires. An interval in the first direction between the intermediate power supply wires is larger than an interval in the first direction between the power supply rails, and is smaller than an interval in the first direction between the upper power supply strap wires.

First Embodiment

(1) Description of Structure in FIG. 1

FIG. 1 is a perspective view illustrating a structure of a semiconductor integrated circuit of a first embodiment.

FIG. 1 illustrates power supply wires in an M 1 routing layer, an M 2 routing layer above the M 1 routing layer, an M 3 routing layer above the M 2 routing layer, an M 4 routing layer above the M 3 routing layer, an M 5 routing layer above the M 4 routing layer, an M 6 routing layer above the M 5 routing layer, and an M 7 routing layer above the M 6 routing layer. The M 6 , M 4 , M 5 , M 1 and M 7 routing layers are examples of first, second, third, fourth and fifth routing layers, respectively. Further, reference signs T 1 to T 7 denote the thicknesses of the power supply wires in the M 1 to M 7 routing layers, respectively.

FIG. 1 also illustrates first-layer via plugs V 1 electrically connecting the power supply wires in the M 1 and M 2 routing layers, second-layer via plugs V 2 electrically connecting the power supply wires in the M 2 and M 3 routing layers, third-layer via plugs V 3 electrically connecting the power supply wires in the M 3 and M 4 routing layers, fourth-layer via plugs V 4 electrically connecting the power supply wires in the M 4 and M 5 routing layers, fifth-layer via plugs V 5 electrically connecting the power supply wires in the M 5 and M 6 routing layers, and sixth-layer via plugs V 6 electrically connecting the power supply wires in the M 6 and M 7 routing layers. The via plugs V 5 and V 4 are examples of first and second via plugs, respectively. Further, reference signs H 1 to H 6 denote the thicknesses of the via plugs V 1 to V 6 , respectively.

FIG. 1 also illustrates X and Y directions that are parallel to the M 1 to M 7 routing layers and are perpendicular to each other, and a Z direction perpendicular to the M 1 to M 7 routing layers. The Y and X directions are examples of first and second directions, respectively.

All the power supply wires in FIG. 1 are VDD wires. The present embodiment also can be applied to the case where all the power supply wires in FIG. 1 are VSS wires, and the case where all the power supply wires in FIG. 1 are wires that supply potentials other than VDD and VSS.

(2) Description of Structure in FIG. 2

FIG. 2 is a plan view illustrating the structure of the semiconductor integrated circuit of the first embodiment.

Subscripts in the reference signs M 1 to M 7 are added to distinguish power supply wires in the same layer. In FIG. 2 , the M 2 and M 3 routing layers and the via plugs V 1 to V 6 are omitted for ease of illustration.

The M 6 routing layer includes a power supply strap wire M 6 A . The power supply strap wire M 6 A extends in the direction. Although the M 6 routing layer includes one power supply strap wire in FIG. 2 , it may include two or more power supply strap wires.

The M 4 routing layer includes an auxiliary power supply strap wire M 4 A . The auxiliary power supply strap wire M 4 A extends in the Y direction. The wire M 6 A corresponds to a main power supply strap wire, whereas the wire M 4 A corresponds to an auxiliary power supply strap wire that mediates connection between the main power supply strap wire and power supply rails to be described later. Although the M 4 routing layer includes one auxiliary power supply strap wire in FIG. 2 , it may include two or more auxiliary power supply strap wires.

The M 5 routing layer includes a plurality of intermediate power supply wires that electrically connects one power supply strap wire M 6 A to one auxiliary power supply strap wire M 4 A . FIG. 4 illustrates three intermediate power supply wires M 5 A to M 5 C as examples of such intermediate power supply wires.

The intermediate power supply wires M 5 A to M 5 C are arranged periodically along the Y direction. A reference sign α 1 denotes the Y-directional interval between the intermediate power supply wires M 5 A to M 5 C .

The M 1 routing layer includes a plurality of power supply rails electrically connected to the auxiliary power supply strap wire M 4 A . FIG. 2 illustrates five power supply rails M 1 A to M 1 E as examples of such power supply rails. The wires M 1 A to M 1 E extend in the X direction and are arranged so as to be adjacent to one another. The wires M 1 A to M 1 E are electrically connected to the auxiliary power supply strap wire M 4 A with the intermediation of the power supply wires in the M 2 and M 3 routing layers (see FIG. 1 ).

The power supply rails M 1 A to M 1 E are arranged periodically along the Y direction. A reference sign β 1 denotes the Y-directional interval between the power supply rails M 1 A to M 1 E . In the present embodiment, the interval α 1 between the intermediate power supply wires M 5 A to M 5 C is set to be larger than the interval β 1 between the power supply rails M 1 A to M 1 E (α 1 >β 1 ).

A wire structure of the present embodiment can be applied to, for example, the case where power supply is supplied to standard cells each including two types of power supply rail connecting terminals (VDD and VSS connecting terminals) in the M 1 routing layer. In this case, VDD power supply rails, VSS power supply rails, and the standard cells are arranged in the following manner, for example, 1) The VDD power supply rails are arranged in the M 1 routing layer, and the interval between the VDD power supply rails is set to β 1 . 2) The VSS power supply rails are arranged in the M 1 routing layer so as to be alternate with the VDD power supply rails, and the interval between the VSS power supply rails is set to be β 1 . 3) The standard cells are arranged in spaces between the VDD power supply rails and the VSS power supply rails, so that the VDD and VSS power supply rails are respectively connected to the VDD and VSS connecting terminals of the standard cells.

Further, the wire structure of the present embodiment can also be applied to, for example, the case where power is supplied to standard cells each including three or more types of power supply rail connecting terminals in the M 1 routing layer. In this case, three or more types of power supply rails are arranged at positions respectively corresponding to the power supply rail connecting terminals.

Further, the interval between the intermediate power supply wires M 5 A to M 5 C may be configured by repeating N types of values α 1 , α 2 , . . . , α N (N is an integer equal to or more than 2), instead of the single value α 1 . Similarly, the interval between the power supply rails M 1 A to M 1 E may be configured by repeating M types of values β 1 , β 2 , . . . , β M (M is an integer equal to or more than 2), instead of the single value β 1 . That is, the pitch between the intermediate power supply wires M 5 A to M 5 C and the pitch between the power supply rails M 1 A to M 1 E may be non-constant in the above-mentioned repetition. Such a wire structure is adopted for, for example, the case where standard cell rows having different heights are alternately provided and the case where rows which include no cell and are used for signal wires, are provided periodically between the standard cell rows. In this case, the wire structure of the present embodiment is configured such that α i >β j is established (i and j are arbitrary integers that satisfy i=1 to N and j=1 to M).

The semiconductor integrated circuit of the present embodiment may include M 7 and higher routing layers. In this case, as illustrated in FIG. 2 , the semiconductor integrated circuit of the present embodiment may further include a plurality of power supply strap wires (hereinafter referred to as “upper power supply strap wires”) that extend in the X direction in the M 7 routing layer. This can further enhance a power supply supplying function.

The M 7 routing layer includes a plurality of upper power supply strap wires electrically connected to the power supply strap wire M 6 A . FIG. 2 illustrates two upper power supply strap wires M 7 A and M 7 B as examples of such upper power supply strap wires. The wires M 7 A and M 7 B extend in the X direction and are arranged so as to be adjacent to each other.

The upper power supply strap wires M 7 A and M 7 B are arranged periodically along the Y direction. A reference sign γ 1 denotes the Y-directional interval between the upper power supply strap wires M 7 A and M 7 B . In the present embodiment, the interval α 1 between the intermediate power supply wires M 5 A to M 5 is set to be smaller than the interval γ 1 between the upper power supply strap wires M 7 A and M 7 B (α 1 <γ 1 ).

The interval between the intermediate power supply wires M 5 A to M 5 C may be configured by repeating N types of values α 1 , α 2 , . . . , α N (N is an integer equal to or more than 2), instead of the single value α 1 . Similarly, the interval between the upper power supply strap wires M 7 A and M 7 B may be configured by repeating L types of values γ 1 , γ 2 , . . . , γ L (L is an integer equal to or more than 2), instead of the single value γ 1 . That is, the pitch between the intermediate power supply wires M 5 A to M 5 C and the pitch between the upper power supply strap wires M 7 A and M 7 B may be non-constant in the above-mentioned repetition. In this case, the wire structure of the present embodiment is configured such that α i >γ k is established (i and k are arbitrary integers that satisfy i=1 to N and k=1 to L).

(3) Advantages of Semiconductor Integrated Circuit of First Embodiment

Advantages of the semiconductor integrated circuit of the first embodiment will be described in detail with reference to FIG. 1 and FIG. 2 .

In the case where power supply wires and via plugs that connect the power supply strap wire M 6 A to the power supply rails M 1 A to M 1 E are arranged at the same number in each routing layer, the routing tracks available for signal wires in the X direction directly below the power supply strap wire M 6 A are restricted by the power supply wires and the via plugs that connect the power supply strap wire M 6 A to the power supply rails M 1 A to M 1 E , in the M 1 , M 3 , and M 5 routing layers in which the X direction is a preferred routing direction. For example, in the case where the thickness T 6 of the M 6 routing layer is larger than the thicknesses T 1 to T 5 of the M 1 to M 5 routing layers, it is desirable to set the size of the via plug V 5 to be larger than the sizes of the via plugs V 1 to V 4 for manufacture reasons. In this case, the sizes of the intermediate power supply wires M 5 A to M 5 C become larger accordingly, and therefore the usable signal routing track number becomes smaller.

In contrast, in the present embodiment, the interval α 1 between the intermediate power supply wires M 5 A to M 5 C is set to be larger than the interval β 1 between the power supply rails M 1 A to M 1 E (α 1 >β 1 ). As a result, according to the present embodiment, the interval α 1 is set to be larger, and the number of the intermediate power supply wires M 5 A to M 5 is made smaller, whereby a large region for signal wire arrangement can be secured in the M 5 routing layer.

Meanwhile, in the case where the interval α 1 between the intermediate power supply wires M 5 A to M 5 C is larger than the interval γ 1 between the upper power supply strap wires M 7 A and M 7 B , effects of the auxiliary power supply strap wire M 4 A become larger and a current path detours, in a power supplying route from the upper power supply strap wires M 7 A and M 7 B to the power supply rail connecting terminals of the standard cells in the M 1 routing layer. Therefore, in the power supplying route, a rate of a drop of the power supply voltage in the auxiliary power supply strap wire M 4 A becomes larger. This is remarkable in the case where the thickness T 4 of the M 4 routing layer is smaller than the thickness T 6 of the M 6 routing layer.

In contrast, in the present embodiment, the interval α 1 between the intermediate power supply wires M 5 A to M 5 C is set to be smaller than the interval γ 1 between the upper power supply strap wires M 7 A and M 7 B (α 1 <γ 1 ). As a result, according to the present embodiment, the interval α 1 is set to be smaller than the interval γ 1 , and the number of the intermediate power supply wires M 5 A to M 5 E is made larger than the number of the upper power supply strap wires M 7 A and M 7 B , whereby a problem that an insufficient number of the intermediate power supply wires M 5 A to M 5 E causes an excessive drop of the power supply voltage can be suppressed.

According to the present embodiment, the configuration described above can reduce regions used for power supply wires, and can increase routing tracks usable for signal wires. As a result, according to the present embodiment, signal wire congestion can be alleviated, and signal wire efficiency can be improved. This can be expected to suppress, for example, an increase in costs due to an increase in chip area, an increase in signal wire length for detouring around power supply wires, a decrease in accuracy of timing control, an increase in cell area, and an increase in consumed power.

Although the intermediate power supply wires M 5 A to M 5 C , the power supply rails M 1 A to M 1 E , and the upper power supply strap wires M 7 A and M 7 B are arranged periodically in the present embodiment, the semiconductor integrated circuit of the present embodiment may include both a periodic region in which these wires are arranged periodically and a non-periodic region in which these wires are arranged non-periodically. In this case, the relation of β 1 <α 1 <γ 1 can be set within the periodic region.

Second Embodiment

(1) Description of Structure in FIG. 3

FIG. 3 is a perspective view illustrating a structure of a semiconductor integrated circuit of a second embodiment.

FIG. 3 illustrates power supply wires in an M 1 routing layer, an M 2 routing layer above the M 1 routing layer, an M 3 routing layer above the M 2 routing layer, an M 4 routing layer above the M 3 routing layer, an M 5 routing layer above the M 4 routing layer, and an M 6 routing layer above the M 5 routing layer.

FIG. 3 also illustrates first-layer via plugs V 1 electrically connecting the power supply wires in the M 1 and M 2 routing layers, second-layer via plugs V 2 electrically connecting the power supply wires in the M 2 and M 3 routing layers, third-layer via plugs V 3 electrically connecting the power supply wires in the M 3 and M 4 routing layers, fourth-layer via plugs V 4 electrically connecting the power supply wires in the M 4 and M 5 routing layers, and fifth-layer via plugs V 5 electrically connecting the power supply wires in the M 5 and M 6 routing layers.

(2) Description of Structure in FIG. 4

FIG. 4 is a plan view illustrating the structure of the semiconductor integrated circuit of the second embodiment.

Subscripts in reference signs M 1 to M 6 and reference signs V 1 to V 5 are added to distinguish power supply wires and via plugs in the same layer. In FIG. 4 , the M 2 routing layer and the via plugs V 1 and V 2 are omitted for ease of illustration.

The M 6 routing layer includes a first power supply strap wire M 6 A that is a VDD (first voltage) wire and a second power supply strap wire M 6 B that is a VSS (second voltage) wire. The wires M 6 A and M 6 B extend in the Y direction and are arranged so as to be adjacent to one another. A reference sign L denotes a central wire between the wires M 6 A and M 6 B .

Although the M 6 routing layer includes two power supply strap wires in FIG. 4 , it may include three or more power supply strap wires. Each of the power supply strap wires may be a VDD wire and may be a VSS wire.

The M 4 routing layer includes a first auxiliary power supply strap wire M 4 A that is a VDD wire and a second auxiliary power supply strap wire M 4 B that is a VSS wire. The wires M 4 A and M 4 B extend in the Y direction and are arranged so as to be adjacent to one another.

In the present embodiment, a width W 2 of the auxiliary power supply strap wires M 4 A and M 4 B is set to be smaller than a width W 1 of the power supply strap wires M 6 A and M 6 B . Further, a distance D 2 between the auxiliary power supply strap wires M 4 A and M 4 B is set to be smaller than a distance D 1 between the power supply strap wires M 6 A and M 6 B . In addition, the first and second auxiliary power supply strap wires M 4 A and M 4 B are arranged so as to be closer to the central line L than the first and second power supply strap wires M 6 A and M 6 B .

Although the M 4 routing layer includes two auxiliary power supply strap wires in FIG. 4 , it may include three or more auxiliary power supply strap wires. Each of the auxiliary power supply strap wires may be a VDD wire and may be a VSS wire.

The M 5 routing layer includes a first intermediate power supply wire M 5 A that is a VDD wire and a second intermediate power supply wire M 5 B that is a VSS wire. Each of the wires M 5 A and M 5 B electrically connects one of the power supply strap wires M 6 A and M 6 B to one of the auxiliary power supply strap wires M 4 A and M 4 B . Specifically, the wire M 5 A electrically connects the first power supply strap wire M 6 A to the first auxiliary power supply strap wire M 4 A . The wire M 5 B electrically connects the second power supply strap wire M 6 B to the second auxiliary power supply strap wire M 4 B . The wires M 5 A and M 5 B extend in the X direction and are arranged on the same straight line.

The first intermediate power supply wire M 5 A includes a first region R 1 that overlaps with the first power supply strap wire M 6 A , and a second region R 2 that does not overlap with the first power supply strap wire M 6 A . Further, the second intermediate power supply wire M 5 B includes a third region R 3 that overlaps with the second power supply strap wire M 6 B , and a fourth region R 4 that does not overlap with the second power supply strap wire M 6 B . The second and fourth regions R 2 and R 4 are respectively located so as to be closer to the central line L than the first and third regions R 1 and R 3 .

The M 5 routing layer may include two or more first intermediate power supply wires that electrically connect the first power supply strap wire M 6 A to the first auxiliary power supply strap wire M 4 A , and two or more second intermediate power supply wires that electrically connect the second power supply strap wire M 6 B to the second auxiliary power supply strap wire M 4 B . A specific example of such a structure will be described later with reference to FIG. 5 .

Hereinafter, the fifth-layer via plugs V 5 are referred to as upper via plugs, and the fourth-layer via plugs V 4 are referred to as lower via plugs.

The upper via plugs V 5 includes one or more upper via plugs V 5 A1 to V 5 A3 that electrically connect the first power supply strap wire M 6 A to the first intermediate power supply wire M 5 A , and one or more upper via plugs V 5 B1 to V 5 B3 that electrically connect the second power supply strap wire M 6 B to the second intermediate power supply wire M 5 B . As illustrated in FIG. 4 , the former upper via plugs V 5 A1 to V 5 A3 are arranged so as to overlap with the first region R 1 , and the latter upper via plugs V 5 B1 to V 5 B3 are arranged so as to overlap with the third region R 3 .

Further, the lower via plugs V 4 includes one or more lower via plugs V 4 A1 to V 4 A6 that electrically connect the first auxiliary power supply strap wire M 4 A to the first intermediate power supply wire M 5 A , and one or more lower via plugs V 4 B1 to V 4 B6 that electrically connect the second auxiliary power supply strap wire M 4 B to the second intermediate power supply wire M 5 B . As illustrated in FIG. 4 , the former lower via plugs V 4 A1 to V 4 A6 are arranged so as to overlap with the second region R 2 , and the latter lower via plugs V 4 B1 to V 4 B6 are arranged so as to overlap with the fourth region R 4 .

In the present embodiment, although all of the lower via plugs V 4 A1 to V 4 B6 overlap with the second or fourth region R 2 or R 4 , only a part of the lower via plugs V 4 A1 to V 4 36 may overlap with the second or fourth region R 2 or R 4 . For example, six of the twelve lower via plugs V 4 A1 to V 4 B6 may be located in the second or fourth region R 2 or R 4 in FIG. 4 , and the other six may be located in the first or third region R 1 or R 3 in FIG. 4 .

In the present embodiment, a thickness H 5 of the upper via plugs V 5 is set to be larger than a thickness H 4 of the lower via plugs V 4 (see FIG. 3 ). Further, a width P 1 of the upper via plugs V 5 is set to be larger than a width P 2 of the lower via plugs V 4 . As a result, an area P 1 2 of the upper via plugs V 5 is larger than an area P 2 2 of the lower via plugs V 4 . In addition, the lower via plugs V 4 are arranged so as to be closer to the central line L than the upper via plugs V 5 .

In the present embodiment, a wire thickness T 5 of the M 5 routing layer is set to be larger than a wire thickness T 4 of the M 4 routing layer (see FIG. 3 ). As a result, the area of each upper via plug V 5 is larger than the area of each lower via plugs V 4 .

Further, in the present embodiment, the X-directional width and the Y-directional width of the upper via plugs V 5 may be different, and the X-directional width and the Y-directional width of the lower via plugs V 4 may be different.

The intermediate power supply wires M 5 A and M 5 B have a function of replacing the upper via plugs V 5 with the lower via plugs V 4 that are closer to the central line L. That is, the intermediate power supply wires M 5 A and M 5 B function as a via position changing wires that change the positions of the via plugs for connecting the power supply strap wires M 6 A and M 6 B to the auxiliary power supply strap wires M 4 A and M 4 B . Further, the intermediate power supply wires M 5 A and M 5 B have a function of replacing the upper via plugs V 5 with the lower via plugs V 4 having a different size (an area and a thickness).

The M 1 to M 3 routing layers will be described in detail.

The M 1 routing layer includes a plurality of first power supply rails M 1 B and M 1 D that are VDD wires, and a plurality of second power supply rails M 1 A and M 1 C that are VSS wires. In FIG. 4 , the plurality of first power supply rails M 1 B and M 1 D are electrically connected to one first auxiliary power supply strap wire M 4 A , and the plurality of second power supply rails M 1 A and M 1 C are electrically connected to one second auxiliary power supply strap wire M 4 B .

The first and second power supply rails M 1 A to M 1 D extend in the X direction and are arranged so as to be adjacent to one another. In the M 1 routing layer, the first power supply rails M 1 B and M 1 D and the second power supply rails M 1 A and M 1 C are alternately arranged.

As illustrated in FIG. 4 , both of the first and second intermediate power supply wires M 5 A and M 5 B are arranged so as not to overlap with the first power supply rails M 1 B and M 1 D and the second power supply rails M 1 A and M 1 C . Specifically, in FIG. 4 , the intermediate power supply wires M 5 A and M 5 B are arranged between the first power supply rail M 1 B and the second power supply rail M 1 C adjacent to each other.

Standard cells or gate array cells (not illustrated) are arranged between the first and second power supply rails M 1 A to M 1 D . A VDD potential and a VSS potential are supplied to these cells from the first and second power supply rails M 1 A to M 1 D . In the present embodiment, the wire structure illustrated in FIG. 4 is repetitively provided on a chip for each region in which these cells are arranged.

The M 3 routing layer includes a plurality of first power supply wires M 3 B and M 3 D that are VDD wires, and a plurality of second power supply wires M 3 A and M 3 C that are VSS wires. The first power supply wires M 3 B and M 3 D electrically connect the first auxiliary power supply strap wire M 4 A to the first power supply rails M 1 B and M 1 D , respectively. Further, the second power supply wires M 3 A and M 3 C electrically connect the second auxiliary power supply strap wire M 4 B to the second power supply rails M 1 A and M 1 C , respectively. The first and second power supply wires M 3 A to M 3 D extend in the X direction and correspond to the first and second power supply rails M 1 A to M 1 D on a one-to-one basis.

As illustrated in FIG. 4 , each of the first and second power supply wires M 3 A and M 3 includes a region between the first and second auxiliary power supply strap wires M 4 A and M 4 B . Specifically, in FIG. 4 , the power supply wires M 3 A and M 3 C are arranged across the central line L.

As described above, the power supply wires M 3 A to M 3 D respectively correspond to the power supply rails M 1 A to M 1 D on a one-to-one basis. Accordingly, as illustrated in FIG. 4 , the Y-directional pitch (interval) between the power supply wires M 3 A to M 3 D is coincident with the Y-directional pitch (interval) between the power supply rails M 1 A to M 1 D .

Meanwhile, each of the intermediate power supply wires M 5 A and M 5 B corresponds to the plurality of power supply rails M 1 A to M 1 D . Accordingly, in the present embodiment, the Y-directional pitch of the intermediate power supply wires M 5 A and M 5 B (the pitch between the first intermediate power supply wire M 5 A and another first intermediate power supply wire (not illustrated) and the pitch between the second intermediate power supply wire M 5 B and another second intermediate power supply wire (not illustrated)) can be set to be equal to or more than twice the Y-directional pitch between the power supply rails M 1 A to M 1 D . A specific example of such a structure will be described later with reference to FIG. 5 .

The above description of the power supply wires in the M 3 routing layer similarly applies to the power supply wires in the M 2 routing layer.

Regions in the M 1 to M 6 routing layers in which power supply wires and cells do not exist can be used for signal wires. In the present embodiment, the X direction is a preferred routing direction for the signal wires in the M 1 , M 3 , and M 5 routing layers, and the Y direction is a preferred routing direction for the signal wires in the M 2 , M 4 , and M 6 routing layers.

The semiconductor integrated circuit of the present embodiment may include M 7 and higher routing layers. In this case, the semiconductor integrated circuit of the present embodiment may further include first and second upper power supply strap wires that extend in the X direction in the M 7 routing layer. This can further enhance a power supplying function. A specific example of the first and second upper power supply strap wires will be described later with reference to FIG. 5 and FIG. 6 .

In the present embodiment, the M 6 and higher routing layers are thick enough to supply electric power to a large region on a chip. In FIG. 3 , a thickness T 6 of the M 6 routing layer is set to be larger than thicknesses T 1 to T 5 of the M 1 to M 5 routing layers. Because the M 6 routing layer is thick, the sheet resistance of each of the first and second power supply strap wires M 6 A and M 6 B is low. Overall, the power supply wire width and the power supply wire interval of the M 6 routing layer are set to be larger than the power supply wire width and the power supply wire interval of the M 1 to M 5 routing layers. Further, the smallest interval between the upper via plugs V 5 is larger than the smallest interval between the lower via plugs V 4 .

(3) Description of Structure in FIGS. 5 and 6

FIG. 5 is another plan view illustrating the structure of the semiconductor integrated circuit of the second embodiment. FIG. 5 illustrates a larger region than FIG. 3 and FIG. 4 .

FIG. 6 is another perspective view illustrating the structure of the semiconductor integrated circuit of the second embodiment. FIG. 6 illustrates a part of the region of FIG. 5 .

Hereinafter, the structure illustrated in FIG. 5 will be described. FIG. 6 serves to check a three-dimensional position relation of power supply wires illustrated in FIG. 5 .

FIG. 5 illustrates power supply wires in the M 7 routing layer above the M 6 routing layer, in addition to the power supply wires in the M 1 , M 4 , M 5 , and M 6 routing layers. In FIG. 5 , the M 2 and M 3 routing layers and the via plugs V 1 to V 5 are omitted for ease of illustration. In FIG. 5 , the sixth-layer via plugs V 6 electrically connecting the power supply wires in the M 6 and M 7 routing layers are also omitted.

The M 5 routing layer includes a plurality of first intermediate power supply wires M 5 A , M 5 C , and M 5 E that are VDD wires, and a plurality of second intermediate power supply wires M 5 B , M 5 D , and M 5 F that are VSS wires. The former wires M 5 A , M 5 C , and M 5 E electrically connect the first power supply strap wire M 6 A to the first auxiliary power supply strap wire M 4 A , and the latter wires M 5 B , M 5 D , and M 5 F electrically connect the second power supply strap wire M 6 B to the second auxiliary power supply strap wire M 4 B .

As illustrated in FIG. 5 , the first intermediate power supply wires M 5 A , M 5 C , and M 5 E are arranged periodically along the Y direction. A reference sign α 1 denotes the Y-directional interval between the first intermediate power supply wires M 5 A , M 5 C , and M 5 E . Similarly, the second intermediate power supply wires M 5 B , M 5 D , and M 5 F are arranged periodically along the Y direction. A reference sign α 2 denotes the Y-directional interval between the second intermediate power supply wires M 5 B , M 5 D , and M 5 F . In the present embodiment, although α 1 and α 2 are set to the same value, they may be set to different values.

The M 1 routing layer includes a plurality of first power supply rails M 1 B , M 1 D , M 1 F , and M 1 H that are VDD wires, and a plurality of second power supply rails M 1 A , M 1 , M 1 E , M 1 G , and M 1 1 that are VSS wires. The former wires M 1 B , M 1 D , M 1 F , and M 1 H are electrically connected to the first auxiliary power supply strap wire M 4 A , and the latter wires M 1 A , M 1 C , M 1 E , M 1 G , and M 1 1 are electrically connected to the second auxiliary power supply strap wire M 4 B . The wires M 1 A to M 1 1 extend in the X direction, and the first power supply rails and the second power supply rails are alternately arranged.

As illustrated in FIG. 5 , the first power supply rails M 1 B , M 1 D , M 1 F , and M 1 H are arranged periodically along the Y direction. A reference sign β 1 denotes the Y-directional interval between these first power supply rails. Similarly, the second power supply rails M 1 A , M 1 C , M 1 E , M 1 G , and M 1 1 are arranged periodically along the Y direction. A reference sign β 2 denotes the Y-directional interval between these second power supply rails. In the present embodiment, although β 1 and β 2 are set to the same value, they may be set to different values.

The M 7 routing layer includes a plurality of first upper power supply strap wires M 7 A and M 7 C that are VDD wires, and a plurality of second upper power supply strap wires M 7 B and M 7 D that are VSS wires. The former wires M 7 A and M 7 C are electrically connected to the first power supply strap wire M 6 A , and the latter wires M 7 B and M 7 D are electrically connected to the second power supply strap wire M 6 B . The wires M 7 A to M 7 D extend in the X direction, and the first upper power supply strap wires and the second upper power supply strap wires are alternately arranged.

As illustrated in FIG. 5 , the first upper power supply strap wires M 7 A and M 7 C are arranged periodically along the Y direction. A reference sign γ 1 denotes the Y-directional interval between these first upper power supply strap wires. Similarly, the second upper power supply strap wires M 7 B and M 7 D are arranged periodically along the Y direction. A reference sign γ 2 denotes the Y-directional interval between these second upper power supply strap wires. In the present embodiment, although γ 1 and γ 2 are set to the same value, they may be set to different values.

In the present embodiment, the interval α 1 between the first intermediate power supply wires M 5 A , M 5 C , and M 5 E is set to be larger than the interval β 1 between the first power supply rails M 1 B , M 1 D , M 1 F , and M 1 H , and is set to be smaller than the interval γ 1 between the first upper power supply strap wires M 7 A and M 7 C (β 1 <α 1 <γ 1 ).

Further, in the present embodiment, the interval α 2 between the second intermediate power supply wires M 5 B , M 5 D , and M 5 F is set to be larger than the interval β 2 between the second power supply rails M 1 A , M 1 C , M 1 E , M 1 G , and M 1 1 , and is set to be smaller than the interval γ 2 between the second upper power supply strap wires M 7 B and M 7 D (β 2 <α 2 <γ 2 ).

Although the intermediate power supply wires, the power supply rails, and the upper power supply strap wires are arranged periodically in the present embodiment, the semiconductor integrated circuit of the present embodiment may include both a periodic region in which these wires are arranged periodically and a non-periodic region in which these wires are arranged non-periodically. In this case, the relations of β 1 <α 1 <γ 1 and β 2 <α 2 <γ 2 can be set within the periodic region.

(4) Advantages of Semiconductor Integrated Circuit of Second Embodiment

Advantages of the semiconductor integrated circuit of the second embodiment will be described in detail with reference to FIG. 3 to FIG. 6 .

In the present embodiment, the wire width W 1 and the wire distance D 1 of the power supply strap wires M 6 A and M 6 B are set to be large. The reason for this is that, because the thickness T 6 of the M 6 routing layer is large, the wires M 6 A and M 6 B have no choice but to be roughly processed due to design rules.

Meanwhile, in the present embodiment, the wire width W 2 and the wire distance D 2 of the auxiliary power supply strap wires M 4 A and M 4 B are set to be smaller than the wire width W 1 and the wire distance D 1 , respectively. The reason for this is that, because the thickness T 4 of the M 4 routing layer is smaller than the thickness T 6 , the wires M 4 A and M 4 B can be more finely processed.

Hereinafter, advantages obtained by setting the wire width W 2 and the wire distance D 2 to be small will be described with reference to FIGS. 7A and 7B . FIGS. 7A and 7B are plan views for explaining a method of arranging the M 4 power supply wires of the second embodiment.

FIG. 7A illustrates the first and second auxiliary power supply strap wires M 4 A and M 4 B whose wire distance D 2 is set to be large. Reference signs S denote regions in which signal wires cannot be arranged because the regions is excessively close to the auxiliary power supply strap wire M 4 A or M 4 B . Further, reference signs W denote the X-directional width of the regions S. In the case of FIG. 7A , signal wires cannot be arranged inside of the auxiliary power supply strap wires M 4 A and M 4 B and inside of the four regions S.

FIG. 7B illustrates the first and second auxiliary power supply strap wires M 4 A and M 4 B whose wire distance D 2 is set to be small. In FIG. 7B , the wire distance D 2 is set to be smaller than twice the width W. In FIG. 7B , two regions S between the auxiliary power supply strap wires M 4 A and M 4 B are connected to become a region S′ having an area smaller than the total area of the two regions S (S′<2×S).

As a result, regions in which signal wires cannot be arranged are 4×S in FIG. 7A , whereas regions in which signal wires cannot be arranged are 2×S+S′ in FIG. 7B which is smaller than 4×S. Accordingly, in the case of FIG. 7B , the area for signal wire arrangement is larger compared with the case of FIG. 7A . The area for signal wire arrangement can also be made larger by making the wire width W 2 of the auxiliary power supply strap wires M 4 A and M 4 B be smaller.

As described above, according to the present embodiment, the wire width W 2 and the wire distance D 2 of the auxiliary power supply strap wires M 4 A and M 4 B are made smaller, whereby the area for signal wire arrangement can be made larger.

In the present embodiment, the wire width W 2 and the wire distance D 2 are smaller than the wire width W 1 and the wire distance D 1 , respectively, and therefore the power supply strap wires M 6 A and M 6 B and the auxiliary power supply strap wires M 4 A and M 4 B are offset with respect to each other as illustrated in FIG. 4 .

Accordingly, the first intermediate power supply wire M 5 A of the present embodiment includes the first region R 1 that overlaps with the first power supply strap wire M 6 A , and the second region R 2 that does not overlap with the first power supply strap wire M 6 A , in order to connect the wire M 6 A and the wire M 4 A that are offset with respect to each other (see FIG. 4 ). With this configuration, the wire M 6 A and the wire M 5 A can be connected using the first region R 1 , and the wire M 4 A and the wire M 5 A can be connected using the second region R 2 .

Similarly, the second intermediate power supply wire M 5 B of the present embodiment includes the third region R 3 that overlaps with the second power supply strap wire M 6 B , and the fourth region R 4 that does not overlap with the second power supply strap wire M 6 B , in order to connect the wire M 6 B and the wire M 4 B (see FIG. 4 ). With this configuration, the wire M 6 B and the wire M 5 B can be connected using the third region R 3 , and the wire M 4 B and the wire M 5 B can be connected using the fourth region R 4 .

In the present embodiment, in order to connect the power supply strap wires M 6 A and M 6 B and the intermediate power supply wires M 5 A and M 5 B configured as described above, the upper via plugs V 5 are arranged so as to overlap with the first or third region R 1 or R 3 .

In the present embodiment, in order to connect the auxiliary power supply strap wires M 4 A and M 4 B and the intermediate power supply wires M 5 A and M 5 B configured as described above, at least a part the lower via plugs V 4 are arranged so as to overlap with the second or fourth region R 2 or R 4 .

In the present embodiment, the intermediate power supply wires M 5 A and M 5 B in FIG. 4 extend in the X direction and are arranged on the same straight line. Such a configuration is advantageous in that a larger region for signal wire arrangement can be secured in the M 5 routing layer compared with, for example, the case where the wires M 5 A and M 5 B extend in the Y direction and the case where the wires M 5 A and M 5 B are arranged on different straight lines. Further, in the present embodiment, the intermediate power supply wires M 5 C and M 5 D in FIG. 5 are arranged on the same straight line, and the intermediate power supply wires M 5 E and M 5 F in FIG. 5 are arranged on the same straight line.

In the present embodiment, as illustrated in FIG. 5 , the interval α 1 between the first intermediate power supply wires is set to be larger than the interval β 1 between the first power supply rails, and the interval α 2 between the second intermediate power supply wires is set to be larger than the interval β 2 between the second power supply rails. As a result, according to the present embodiment, the intervals α 1 and α 2 are set to be large and the number of the intermediate power supply wires M 5 A to M 5 F is reduced, whereby a larger region for signal wire arrangement can be secured in the M 5 routing layer.

In the present embodiment, as illustrated in FIG. 5 , the interval α 1 between the first intermediate power supply wires is set to be smaller than the interval γ 1 between the first upper power supply strap wires, and the interval α 2 between the second intermediate power supply wires is set to be smaller than the interval γ 2 between the second upper power supply strap wires. As a result, according to the present embodiment, the intervals α 1 and α 2 are set to be smaller than the intervals γ 1 and γ 2 , and the number of the intermediate power supply wires M 5 A to M 5 F are made larger than the number of the upper power supply strap wires M 7 A to M 7 D , whereby a problem that an insufficient number of the intermediate power supply wires M 5 A to M 5 F causes an excessive drop of the power supply voltage can be suppressed.

According to the present embodiment, the configuration described above can reduce regions used for power supply wires, and can increase routing tracks usable for signal wires. As a result, according to the present embodiment, signal wire congestion can be alleviated, and signal wire efficiency can be improved. This can be expected to suppress, for example, an increase in costs due to an increase in chip area, an increase in signal wire length for detouring around power supply wires, a decrease in accuracy of timing control, an increase in cell area, and an increase in consumed power.

In the present embodiment, the power supply strap wires M 6 A and M 6 B and the auxiliary power supply strap wires M 4 A and M 4 B may be arranged so as not to be offset with respect to each other. In this case, according to the present embodiment, the adoption of a structure that satisfies the relations of β 1 <α 1 <γ 1 and β 2 <α 2 <γ 2 described above can lead to, for example, an increase in routing tracks usable for signal wires while suppressing the drop of the power supply voltage.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel circuits described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the circuits described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.