Display panel

This application claims the priority benefit of Taiwan application serial no. 102115086, filed on Apr. 26, 2013. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

1. Field of Invention

The invention relates to a display panel, and especially, to a display panel having a multi-split type (MST) circuit architecture.

2. Description of Related Art

In recent years, as semiconductor technology flourishes, portable electronic products and flat display products have been developed accordingly. Due to the driving modes and the display effects, active display panels have been commonly used. In general, pixels in the active display panel are turned on through gate driving signals provided by gate driving chips, so as to set the brightness (or gray-level values) displayed by the pixels. In order to reduce production costs of liquid crystal displays, some of the manufacturers have brought forward the application of thin film transistors (TFT) directly on glass substrates to make multi-stage shift registers, thereby replacing the conventionally used gate driving chips to reduce production costs of flat displays.

In flat displays, the circuit area of the shift registers disposed in the display panel affects the circuit area of the pixels disposed in the display panel, which relatively affects the overall size and appearance of the flat displays. Therefore, relevant display industries have already invested in slim border design in order to make slim and compact displays without sacrificing the display quality, so as to satisfy consumers' requirements.

The invention provides a display panel which removes control units from a gate driving circuit to reduce a circuit area of the gate driving circuit and to further slim down a border of the display panel.

The invention provides a display panel which includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The substrate has a display area and a peripheral area. The pixels are disposed on the display area. The scan lines are disposed on the substrate, are respectively coupled to the corresponding pixels, and extend from the display area to the peripheral area. The pull-down control circuit is disposed on the peripheral area, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of first pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals, and the shift registers are coupled to the pull-down control circuit to receive the first pull-down signals. The shift registers enable the gate driving signals in sequence according to the clock signals and pull down the gate driving signals in sequence according to the first pull-down signals, respectively. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

In light of the above, in the embodiments of the invention, the display panel removes the pull-down control units from the shift registers of the gate driving circuit, so that the removed pull-down control units become an independent pull-down control circuit. Furthermore, in the embodiments of the invention, the gate driving circuit and the pull-down control circuit of the display panel are arranged in sequence along a side of the display area to reduce the circuit area of the gate driving circuit and to slim down the border of the display panel.

FIG. 1 is a schematic system diagram of a display panel according to an embodiment of the invention.

FIG. 2A is a schematic circuit diagram of a shift register according to an embodiment of the invention.

FIG. 2B is a schematic circuit diagram of a pull-down unit according to an embodiment of the invention.

FIG. 2C is a schematic waveform diagram of clock signals and gate driving signals according to an embodiment of the invention.

FIG. 3A is a schematic circuit diagram of a shift register according to another embodiment of the invention.

FIG. 3B is a schematic circuit diagram of a pull-down unit according to another embodiment of the invention.

FIG. 4 is a schematic system diagram of a display panel according to another embodiment of the invention.

FIG. 5A is a schematic circuit diagram of a shift register according to still another embodiment of the invention.

FIG. 5B is a schematic circuit diagram of a pull-down unit according to still another embodiment of the invention.

FIG. 5C is a schematic circuit diagram of a pull-down unit according to yet another embodiment of the invention.

FIG. 6 is a schematic system diagram of a display panel according to still another embodiment of the invention.

FIG. 7A is a schematic circuit diagram of a shift register according to yet another embodiment of the invention.

FIG. 7B is a schematic circuit diagram of a push-up unit according to an embodiment of the invention.

FIG. 8 is a schematic system diagram of a display panel according to yet another embodiment of the invention.

FIG. 1 is a schematic system diagram of a display panel according to an embodiment of the invention. The display panel 100 includes a substrate 110 , a plurality of pixels PX, a plurality of scan lines 115 , gate driving circuits 120 _ 1 and 120 _ 2 , and pull-down control circuits 130 _ 1 and 130 _ 2 . The substrate 100 has a display area 111 and a peripheral area 113 . The pixels PX are disposed on the display area 111 . The scan lines 115 are disposed on the substrate 111 , are respectively coupled to the corresponding pixels PX, and extend from the display area 111 to the peripheral area 113 , so that the scan lines 115 are coupled to the corresponding gate driving circuits (such as 120 _ 1 and 120 _ 2 ).

The pull-down control circuit 130 _ 1 is disposed on the peripheral area 113 , receives a plurality of clock signals (e.g., four clock signals CK 1 L, CK 1 BL, CK 2 L, and CK 2 BL), and has a plurality of pull-down units 131 to provide a plurality of the first pull-down signals (such as D 11 to D 13 ). Similarly, the pull-down control circuit 130 _ 2 is also disposed on the peripheral area 113 and receives a plurality of clock signals (e.g., four clock signals CK 1 R, CK 1 BR, CK 2 R, and CK 2 BR) to provide a plurality of first pull-down signals (such as D 21 to D 23 ), wherein operation of the pull-down control circuit 130 _ 2 may refer to that of the pull-down control circuit 130 _ 1 . Herein, phases of the clock signals CK 1 L, CK 1 BL, CK 2 L, and CK 2 BL, which are received by the pull-down control circuit 130 _ 1 , can respectively lead those of the clock signals CK 1 R, CK 1 BR, CK 2 R, and CK 2 BR, which are received by the pull-down control circuit 130 _ 2 .

The gate driving circuit 120 _ 1 is disposed on the peripheral area 113 and has a plurality of shift registers 121 . The shift registers 121 are coupled to one of the scan lines 115 respectively to provide a plurality of odd-numbered gate driving signals (such as G 1 and G 3 ) to the scan lines 115 . Moreover, the shift registers 121 are coupled to the pull-down control circuit 130 _ 1 to receive the corresponding first pull-down signals (such as D 11 to D 13 ). The shift registers 121 enable the odd-numbered gate driving signals (such as G 1 and G 3 ) in sequence according to the clock signals CK 1 L, CK 1 BL, CK 2 L, and CK 2 BL and pull down the odd-numbered gate driving signals (such as G 1 and G 3 ) in sequence according to the first pull-down signals (such as D 11 to D 13 ) respectively, wherein the pull-down control circuit 130 _ 1 and the gate driving circuit 120 _ 1 are arranged in sequence along a left side of the display area 111 .

The gate driving circuit 120 _ 2 is disposed on the peripheral area 113 , wherein the gate driving circuit 120 _ 2 is coupled to the scan lines 115 to provide a plurality of even-numbered gate driving signals (such as G 2 and G 4 ) to the scan lines 115 and is coupled to the pull-down control circuit 1302 to receive the corresponding first pull-down signals (such as D 21 to D 23 ). The gate driving circuit 120 _ 2 enables the even-numbered gate driving signals (such as G 2 and G 4 ) in sequence according to the clock signals CK 1 R, CK 1 BR, CK 2 R, and CK 2 BR and pull down the even-numbered gate driving signals (such as G 2 and G 4 ) in sequence according to the first pull-down signals (such as D 21 to D 23 ) respectively, wherein operation of the gate driving circuit 120 _ 2 may refer to that of the gate driving circuit 120 _ 1 , and the pull-down control circuit 130 _ 2 and the gate driving circuit 120 _ 2 are arranged in sequence along a right side of the display area 111 .

According to the above, since the gate driving circuits 120 _ 1 and 120 _ 2 pull down the gate driving signals (such as G 1 to G 4 ) according to the first pull-down signals (such as D 11 to D 13 and D 21 to D 23 ), circuits of the shift registers 121 used to decide the pull-down time sequence of the gate driving signals (such as G 1 to G 4 ) may be removed without affecting operation of the shift registers 121 . Thereby, the circuit area of the gate driving circuits 120 _ 1 and 120 _ 2 may be reduced, so as to slim down a border of the display panel.

Additionally, in the present embodiment, the pull-down control circuit 130 _ 1 is disposed below the gate driving circuit 120 _ 1 . In other embodiments, however, the pull-down control circuit 130 _ 1 may be disposed above the gate driving circuit 120 _ 1 or the pull-down control circuit 130 _ 1 may be disposed both sides of below and above the gate driving circuit 120 _ 1 at the same time, which may be modified by those having ordinary skill in the art. Similarly, the pull-down control circuit 130 _ 2 may not only be disposed below the gate driving circuit 120 _ 2 but also be disposed above the gate driving circuit 120 _ 2 or the pull-down control circuit 130 _ 2 may be disposed both sides of below and above the gate driving circuit 120 _ 2 at the same time.

FIG. 2A is a schematic circuit diagram of a shift register according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 2A . In the present embodiment, the shift register 121 a is an example of the shift register 121 in the gate driving circuit 120 _ 1 , and the exemplary shift register 121 outputs the gate driving signal G 3 (corresponding to the i th gate driving signal, wherein i is an positive integer). In addition, the shift register 121 a is assumed to be capable of performing bidirectional scanning and receiving the first pull-down signal D 12 . In the present embodiment, the shift register 121 a includes a pre-charge unit 210 , a voltage push-up unit 220 , and a voltage pull-down unit 230 . The pre-charge unit 210 includes transistors T 1 and T 2 (corresponding to the first transistor and the second transistor). The voltage push-up unit 220 includes a transistor T 5 (corresponding to the fifth transistor) and a capacitor C 1 (corresponding to the first capacitor). The voltage pull-down unit 230 includes transistors T 3 and T 4 (corresponding to the third transistor and the fourth transistor).

A source of the transistor T 1 (corresponding to the first terminal) receives a forward scanning voltage VF, a drain of the transistor T 1 (corresponding to the second terminal) is coupled to an internal voltage Q, and a gate of the transistor T 1 (corresponding to the control terminal) receives the gate driving signal G 1 (corresponding to the (i−1) th gate driving signal). A source of the transistor T 2 (corresponding to the first terminal) receives a reverse scanning voltage VB, a drain of the transistor T 2 (corresponding to the second terminal) is coupled to the internal voltage Q, and a gate of the transistor T 2 (corresponding to the control terminal) receives the gate driving signal G 5 (corresponding to the (i+1) th gate driving signal). The forward scanning voltage VF is one of a gate high voltage (such as 15 volts) and a gate low voltage VGL (such as −10 volts), and the reverse scanning voltage VB is the other one of the gate high voltage and the gate low voltage. In other words, when the display panel 100 performs forward scanning, the forward scanning voltage VF is the gate high voltage, and the reverse scanning voltage VB is the gate low voltage; when the display panel 100 performs reverse scanning, the forward scanning voltage VF is the gate low voltage, and the reverse scanning voltage VB is the gate high voltage.

According to the above, when the display panel 100 performs forward scanning, and the gate driving signal G 1 is enabled, the enabled gate driving signal G 1 charges the internal voltage Q through the turned-on transistor T 1 ; when the display panel 100 performs reverse scanning, and the gate driving signal G 5 is enabled, the enabled gate driving signal G 5 charges the internal voltage Q through the turned-on transistor T 2 . Therefore, the pre-charge unit 210 can pre-charge the internal voltage Q.

A drain of the transistor T 5 (corresponding to the first terminal) receives the clock signal CK 2 L (corresponding to the first clock signal), a source of the transistor T 5 (corresponding to the second terminal) is coupled to the gate driving signal G 3 , and a gate of the transistor T 5 (corresponding to the control terminal) receives the internal voltage Q. The capacitor C 1 is coupled between the source and the drain of the transistor T 5 . Therefore, the voltage push-up unit 220 can push up the gate driving signal G 3 according to the internal voltage Q.

A drain of the transistor T 3 (corresponding to the first terminal) receives the internal voltage Q, a source of the transistor T 3 (corresponding to the second terminal) receives the gate low voltage VGL, and a gate of the transistor T 3 (corresponding to the control terminal) receives the corresponding first pull-down signal D 12 . Therefore, the voltage pull-down unit 230 can pull down the internal voltage Q and the gate driving signal G 3 according to the first pull-down signal D 12 .

FIG. 2B is a schematic circuit diagram of a pull-down unit according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 2B . In the present embodiment, the pull-down unit 131 a includes transistors T 6 and T 7 (corresponding to the sixth transistor and the seventh transistor). A drain of the transistor T 6 (corresponding to the first terminal) receives the forward scanning voltage VF, a source of the transistor T 6 (corresponding to the second terminal) is coupled to the first pull-down signal D 12 , and a gate of the transistor T 6 (corresponding to the control terminal) receives the clock signal CK 1 BL (corresponding to the second clock signal). A drain of the transistor T 7 (corresponding to the first terminal) receives the reverse scanning voltage VB, a source of the transistor T 7 (corresponding to the second terminal) is coupled to the first pull-down signal D 12 , and a gate of the transistor T 7 (corresponding to the control terminal) receives the clock signal CK 1 L (corresponding to the third clock signal). The forward scanning voltage VF and the reverse scanning voltage VB may be set in the same manner as described in the embodiment shown in FIG. 2A and is thus not reiterated herein.

FIG. 2C is a schematic waveform diagram of clock signals and gate driving signals according to an embodiment of the invention. Please refer to FIG. 1 , FIG. 2A , FIG. 2B , and FIG. 2C . In the present embodiment, enabling periods of the clock signals CK 1 L, CK 1 BL, CK 2 L and CK 2 BL partially overlap with one another and are not exactly the same, wherein the clock signal CK 1 BL can be regarded as an inverse signal of the clock signal CK 1 L (that is, having 180-degree phase difference), and the clock signal CK 2 BL can be regarded as an inverse signal of the clock signals CK 2 L (that is, having 180-degree phase difference). Herein, the display panel 100 performing forward scanning is exemplified for illustration, and the display panel 100 performing reverse scanning can then be understood accordingly.

When the gate driving signal G 1 is enabled, the forward scanning voltage VF, which is the gate high voltage, pre-charges the internal voltage Q. When the clock signal CK 2 L is enabled, the voltage level of the gate driving signal G 2 is pushed up (which is regarded as enabling). When the clock signal CK 1 BL is enabled, the voltage level of the first pull-down signal D 12 is pushed up (which is regarded as enabling), so that the voltage level of the internal voltage Q and the voltage level of the gate driving signal G 3 are pulled down to the gate low voltage VGL. According to the above, the enabling period of the clock signal CK 2 L and the enabling period of the clock signal CK 1 BL partially overlap, and the enabling period of the clock signal CK 2 L and the enabling period of the clock signal CK 1 L partially overlap. Moreover, a phase of the clock signal CK 2 L leads that of the clock signal CK 1 BL, and the phase of the clock signal CK 2 L lags that of the clock signal CK 1 L.

As shown in FIG. 2A , when the shift register 121 a is assumed to output the gate driving signal G 1 , the gate of the transistor T 1 can be coupled to a start signal STVL, so that the pre-charge unit 210 of the shift register 121 a , which outputs the gate driving signal G 1 , can pre-charge the internal voltage.

FIG. 3A is a schematic circuit diagram of another shift register according to another embodiment of the invention. Please refer to FIG. 1 , FIG. 2A , and FIG. 3A . In the present embodiment, the shift register 121 b is substantially the same as the shift register 121 a . The shift register 121 b is assumed to perform unidirectional scanning, wherein the same or similar reference numbers as those in the first embodiment are used herein to represent the same or similar components. The difference between the shift registers 121 a and 121 b lies in a pre-charge unit 310 of the shift register 121 b . Specifically, the pre-charge unit 310 includes a transistor T 8 (corresponding to the ninth transistor). A source (corresponding to the first terminal) and a gate (corresponding to the control terminal) of the transistor T 8 receive the gate driving signal G 1 , and a drain (corresponding to the second ten final) of the transistor T 8 is coupled to the internal voltage Q.

FIG. 3B is a schematic circuit diagram of a pull-down unit according to another embodiment of the invention. Please refer to FIG. 1 and FIG. 3B . In the present embodiment, a pull-down unit 131 b includes a transistor T 9 (corresponding to the eighth transistor). A drain (corresponding to the first terminal) and a gate (corresponding to the control terminal) of the transistor T 9 receive the clock signal CK 1 BL (corresponding to the fourth clock signal), and a source of the transistor T 9 (corresponding to the second terminal) is coupled to the first pull-down signal D 12 . As shown in FIG. 2C , the enabling period of the clock signal CK 2 L and the enabling period of the clock signal CK 1 BL partially overlap, and the phase of the clock signal CK 2 L leads that of the clock signal CK 1 BL.

FIG. 4 is a schematic system diagram of a display panel according to another embodiment of the invention. Please refer to FIG. 1 and FIG. 4 . The display panel 400 is substantially the same as the display panel 100 . The differences between the display panels 400 and 100 lie in gate driving circuits 420 _ 1 and 420 _ 2 and pull-down control circuits 430 _ 1 and 430 _ 2 , wherein the same or similar reference numbers are used herein to represent the same or similar components. The pull-down control circuit 430 _ 1 has a plurality of pull-down units 431 to provide a plurality of the first pull-down signals (such as D 11 to D 13 ) and a plurality of the second pull-down signals (such as D 31 to D 33 ) to the gate driving circuit 420 _ 1 . The pull-down control circuit 430 _ 2 provides a plurality of the first pull-down signals (such as D 21 to D 23 ) and a plurality of the second pull-down signals (such as D 41 to D 43 ) to the gate driving circuit 4202 , wherein operation of the pull-down control circuit 430 _ 2 may refer to that of the pull-down control circuit 430 _ 1 .

The gate driving circuit 420 _ 1 has a plurality of shift registers 421 to provide a plurality of odd-numbered gate driving signals (such as G 1 and G 3 ), and each shift register 421 pulls down the corresponding odd-numbered gate driving signal (such as G 1 and G 3 ) and its internal voltage Q according to the corresponding first pull-down signal (such as D 11 to D 13 ) and the corresponding second pull-down signal (such as D 31 to D 33 ). The gate driving circuit 420 _ 2 serves to provide a plurality of even-numbered gate driving signals (such as G 2 and G 4 ), and operation of the gate driving circuit 420 _ 2 may refer to that of the gate driving circuit 420 _ 1 .

FIG. 5A is a schematic circuit diagram of a shift register according to still another embodiment of the invention. Please refer to FIG. 2A , FIG. 4 , and FIG. 5A . The shift register 421 a is substantially the same as the shift register 121 a , and the difference lies in a voltage pull-down unit 530 , wherein the same or similar reference numbers are used herein to represent the same or similar components. In the present embodiment, the shift register 421 a is assumed to receive the first pull-down signal D 12 and the second pull-down signal D 32 , and the shift register 421 a outputs the gate driving signal G 3 . The voltage pull-down unit 530 includes transistors T 10 to T 12 (corresponding to the tenth transistor to the twelfth transistor).

A drain of the transistor T 10 (corresponding to the first terminal) receives the second pull-down signal D 32 , a source of the transistor T 10 (corresponding to the second terminal) receives the gate low voltage VGL, and a gate of the transistor T 10 (corresponding to the control terminal) receives the internal voltage Q. A drain of the transistor T 11 (corresponding to the first terminal) is coupled to the internal voltage Q, a source of the transistor T 11 (corresponding to the second terminal) receives the gate low voltage VGL, and a gate of the transistor T 11 (corresponding to control terminal) receives the second pull-down signal D 32 . A drain of the transistor T 12 (corresponding to the first terminal) is coupled to the gate driving signal G 3 , a source of the transistor T 12 (corresponding to the second terminal) receives the gate low voltage VGL, and a gate of the transistor T 12 (corresponding to the control terminal) receives the first pull-down signal D 12 .

FIG. 5B is a schematic circuit diagram of a pull-down unit according to still another embodiment of the invention. Please refer to FIG. 4 and FIG. 5B . In the present embodiment, a pull-down unit 431 a includes transistors T 13 to T 16 (corresponding to the thirteenth transistor to the sixteenth transistor). A drain of the transistor T 13 (corresponding to the first terminal) receives the forward scanning voltage VF, a source of the transistor T 13 (corresponding to the second terminal) is coupled to the first pull-down signal D 12 , and a gate of the transistor T 13 (corresponding to the control terminal) receives the clock signal CK 1 BL (corresponding to the fifth clock signal). A drain of the transistor T 14 (corresponding to the first terminal) receives the reverse scanning voltage VB, a source of the transistor T 14 (corresponding to the second terminal) is coupled to the first pull-down signal D 12 , and a gate of the transistor T 14 (corresponding to the control terminal) receives the clock signal CK 1 L (corresponding to the sixth clock signal).

A drain of the transistor T 15 (corresponding to the first terminal) receives the forward scanning voltage VF, a source of the transistor T 15 (corresponding to the second terminal) is coupled to the second pull-down signal D 32 , and a gate of the transistor T 15 (corresponding to the control terminal) receives the clock signal CK 2 L (corresponding to the fifth clock signal). A drain of the transistor T 16 (corresponding to the first terminal) receives the reverse scanning voltage VB, a source of the transistor T 16 (corresponding to the second terminal) is coupled to the second pull-down signal D 32 , and a gate of the transistor T 16 (corresponding to the control terminal) receives the clock signal CK 2 BL (corresponding to the sixth clock signal). The forward scanning voltage VF and the reverse scanning voltage VB may be set in the same manner as described in the embodiment shown in FIG. 2A and is not reiterated herein.

FIG. 5C is a schematic circuit diagram of a pull-down unit according to yet another embodiment of the invention. Please refer to FIG. 5A to FIG. 5C . In the embodiment shown in FIG. 5A and FIG. 5B , the shift registers are applied to bidirectional scanning, whereas the pull-down unit 431 b described herein is the shift register which is applied to unidirectional scanning. For instance, the pre-charge unit 210 of the shift register 421 a is replaced by the pre-charge unit 310 shown in FIG. 3A . The pull-down unit 431 b includes transistors T 17 and T 18 (corresponding to the seventeenth transistor and the eighteenth transistor). A drain (corresponding to the first terminal) and a gate (corresponding to the control terminal) of the transistor T 17 receive the clock signal CK 1 BL (corresponding to the fifth clock signal), and a source of the transistor T 17 (corresponding to the second terminal) is coupled to the first pull-down signal D 12 . A drain (corresponding to the first terminal) and a gate (corresponding to the control terminal) of the transistor T 18 receive the clock signal CK 2 L (corresponding to the fifth clock signal), and a source of the transistor T 18 (corresponding to the second terminal) is coupled to the second pull-down signal D 32 . As shown in FIG. 2C , enabling periods of the clock signals CK 1 BL and CK 2 L partially overlap, and the phase of the clock signal CK 2 L leads that of the clock signal CK 1 BL.

FIG. 6 is a schematic system diagram of a display panel according to still another embodiment of the invention. Please refer to FIG. 1 and FIG. 6 . A display panel 600 is substantially the same as the display panel 100 . The differences between the display panels 600 and 100 lie in gate driving circuits 620 _ 1 and 620 _ 2 and push-up control circuits 630 _ 1 and 630 _ 2 , wherein the push-up control circuits 630 _ 1 and 630 _ 2 are disposed on the peripheral area 113 . The same or similar reference numbers are used herein to represent the same or similar components. The push-up control circuit 630 _ 1 receives the clock signals CK 1 L, CK 1 BL, CK 2 L, and CK 2 BL, and the push-up control circuit 630 _ 2 receives the clock signals CK 1 R, CK 1 BR, CK 2 R, and CK 2 BR. The push-up control circuit 630 _ 1 has a plurality of push-up units 631 to provide a plurality of push-up signals (such as U 11 to U 13 ) to the gate driving circuit 620 _ 1 according to the clock signals CK 1 L, CK 1 BL, CK 2 L, and CK 2 BL. The push-up control circuit 630 _ 2 provides a plurality of push-up signals (such as U 21 to U 23 ) to the gate driving circuit 620 _ 2 according to the clock signals CK 1 R, CK 1 BR, CK 2 R, and CK 2 BR, wherein operation of the push-up control circuit 630 _ 2 may refer to that of the pull-down control circuit 630 _ 1 .

The gate driving circuit 620 _ 1 has a plurality of shift registers 621 to provide a plurality of odd-numbered gate driving signals (such as G 1 and G 3 ), wherein each shift register 621 pulls down the corresponding odd-numbered gate driving signal (such as G 1 and G 3 ) according to the corresponding first pull-down signal (such as D 11 to D 13 ) and pushes up the corresponding odd-numbered gate driving signal (such as G 1 and G 3 ) according to the corresponding push-up signal (such as U 11 to U 13 ). That is, each shift register 621 enables the corresponding odd-numbered gate driving signal (such as G 1 and G 3 ). The gate driving circuit 620 _ 2 is to provide a plurality of even-numbered gate driving signals (such as G 2 and G 4 ), wherein operation of the gate driving circuit 620 _ 2 may refer to that of the gate driving circuit 620 _ 1 .

The gate driving circuit 620 _ 1 and the push-up control circuit 630 _ 1 are arranged in sequence along a left side of the display area 111 ; the gate driving circuit 620 _ 2 and the push-up control circuit 630 _ 2 are arranged in sequence along a right side of the display area 111 . In the present embodiment, the push-up control circuit 630 _ 1 is disposed below the gate driving circuit 620 _ 1 . In other embodiments, however, the push-up control circuit 630 _ 1 may be disposed above the gate driving circuit 620 _ 1 or the push-up control circuit 630 _ 1 may be disposed both sides of below and above the gate driving circuit 620 _ 1 at the same time, which may be modified by people having ordinary skill in the art. Similarly, the push-up control circuit 630 _ 2 may not only be disposed below the gate driving circuit 620 _ 2 but also be disposed above the gate driving circuit 620 _ 2 or the push-up control circuit 630 _ 2 may be disposed both sides of below and above the gate driving circuit 620 _ 2 at the same time.

FIG. 7A is a schematic circuit diagram of a shift register according to yet another embodiment of the invention. Please refer to FIG. 2A , FIG. 6 , and FIG. 7A . The shift register 621 a is substantially the same as the shift register 121 a , and the difference lies in a voltage push-up unit 720 , wherein the same or similar reference numbers are used herein to represent the same or similar components. In the present embodiment, the shift register 621 a is assumed to receive the first pull-down signal D 12 and the push-up signal U 12 , and the shift register 621 a outputs the gate driving signal G 3 . The voltage push-up unit 720 includes transistors T 19 and T 20 (corresponding to the nineteenth transistor and the twentieth transistor).

A drain of the transistor T 19 (corresponding to the first terminal) receives the push-up signal U 12 , and a gate of the transistor T 19 (corresponding to the control terminal) receives the internal voltage Q. A source of the transistor T 20 (corresponding to the first terminal) is coupled to the gate high voltage VGH, a drain of the transistor T 20 (corresponding to the second terminal) is coupled to the gate driving signals G 3 , and a gate of the transistor T 20 (corresponding to control terminal) is coupled to a source of the transistor T 19 (corresponding to the second terminal).

FIG. 7B is a schematic circuit diagram of a push-up unit according to an embodiment of the invention. Please refer to FIG. 6 and FIG. 7B . In the present embodiment, a push-up unit 631 a includes transistors T 21 and T 22 (corresponding to the twenty-first transistor and the twenty-second transistor) and a capacitor C 2 (corresponding to the second capacitor). A drain (corresponding to the first terminal) and a gate (corresponding to the control terminal) of the transistor T 21 receive the clock signal CK 1 L (corresponding to the eleventh clock signal), and a source of the transistor T 21 (corresponding to the second terminal) is coupled to the push-up signal U 12 . A drain (corresponding to the first terminal) and a gate (corresponding to the control terminal) of the transistor T 22 receive the clock signal CK 2 L (corresponding to the twelfth clock signal). The capacitor C 2 is coupled between a source of the transistor T 22 (corresponding to the second terminal) and the push-up signal U 12 . As shown in FIG. 2C , enabling periods of the clock signals CK 1 L and CK 2 L partially overlap, and the phase of the clock signal CK 1 L leads that of the clock signal CK 2 L.

FIG. 8 is a schematic system diagram of a display panel according to yet another embodiment of the invention. Please refer to FIG. 4 , FIG. 6 , and FIG. 8 . A display panel 800 is substantially the same as the display panel 600 , but the pull-down control circuits 130 _ 1 and 130 _ 2 of the display panel 600 are replaced by pull-down control circuits 430 _ 1 and 430 _ 2 as shown in FIG. 4 . Furthermore, the main difference lies in gate driving circuits 820 _ 1 and 820 _ 2 , wherein the same or similar reference numbers are used herein to represent the same or similar components.

The gate driving circuit 820 _ 1 has a plurality of shift registers 821 to provide a plurality of odd-numbered gate driving signals (such as G 1 and G 3 ), wherein each shift register 821 pulls down the corresponding odd-numbered gate driving signal (such as G 1 and G 3 ) and its internal voltage Q according to the corresponding first pull-down signal (such as D 11 to D 13 ) and the corresponding second pull-down signal (such as D 31 to D 33 ), and each shift registers 821 pushes up the corresponding odd-numbered gate driving signal (such as G 1 and G 3 ) according to the corresponding push-up signal (such as U 11 to U 13 ). That is, each shift register 821 enables the corresponding odd-numbered gate driving signal (such as G 1 and G 3 ). The gate driving circuit 8202 is to provide a plurality of even-numbered gate driving signals (such as G 2 and G 4 ), and operation of the gate driving circuit 820 _ 2 may refer to that of the gate driving circuit 820 _ 1 .

When the shift register 821 is the shift register performing bidirectional scanning, the circuit of the shift register 821 may refer to those shown in FIG. 5A and FIG. 7A . That is, the circuit of the shift register 821 is similar to the circuit of the shift register 621 a but the voltage pull-down unit 230 thereof is replaced with the pull-down unit 530 of the shift register 421 a . Alternatively, when the shift register 821 is the shift register performing unidirectional scanning, the circuit of the shift register 821 may refer to those shown in FIG. 3A , FIG. 5A , and FIG. 7A . That is, the circuit of the shift register 821 is similar to the circuit the shift register 621 a but the voltage pull-down unit 230 thereof is replaced with the pull-down unit 530 of the shift register 421 a and the pre-charge unit 210 thereof is replaced with the pre-charge unit 310 of the shift register 121 b.

Additionally, in the embodiments described above, the gate driving circuits (such as 120 _ 1 , 120 _ 2 , 420 _ 1 , 420 _ 2 , 620 _ 1 , 620 _ 2 , 820 _ 1 , and 820 _ 2 ) are disposed on the both sides of the display area 111 . In other embodiments, however, the gate driving circuits may be integrated into a single circuit and disposed on a side of the display area 111 . Similarly, the pull-down control circuits (such as 130 _ 1 , 130 _ 2 , 430 _ 1 , and 430 _ 2 ) may also be integrated into a single circuit and disposed on a side of the display area 111 . In addition, the push-up control circuits (such as 630 _ 1 and 630 _ 2 ) may also be integrated into a single circuit and disposed on a side of the display area 111 .

To sum up, in the embodiments of the invention, the display panel removes the pull-down control units from the shift registers of the gate driving circuit, so that the removed pull-down control units become an independent pull-down control circuit. Furthermore, in the embodiments of the invention, the gate driving circuits and the pull-down control circuits of the display panel are disposed in sequence along a side of the display area to reduce the circuit area of the gate driving circuits and to slim down the border of the display panel. Besides, the boost circuit in the shift registers may be removed, so that the removed boot circuit may become an independent push-up control circuit, and that the circuit area of the gate driving circuits may be further reduced.