Fully integrated adjustable DC current reference based on an integrated inductor reference

The disclosed technology relates generally to electrical circuitry and, more specifically, to the development of an adjustable DC current reference.

Significant efforts were made to develop an integrated DC voltage reference insensitive to Process, Voltage and Temperature (PVT) variations. The DC voltage references are usually based on the Silicon bandgap. To create a DC current reference insensitive to PVT one need in theory just an integrated resistor insensitive to PVT. Unfortunately, integrated resistors are very sensitive to process variations and they drift with temperature. Clearly post fabrication control is needed to adjust the value of such a resistor.

The option of trimming the resistor post-fabrication does not resolve the temperature drift problem and one can trim only before packaging so the value of the current reference cannot be tuned post-trimming. It is true that if temperature drift is not a concern, trimming is a simple and robust solution. Trimming is done usually based on an external resistor. Using an integrated inductor reference could simplify the trimming process.

The option of using a resistor component external to the integrated circuit to set the current has at least the following disadvantages:

The external resistor requires additional pads.

The external resistor requires additional space on the integrated circuit support board i.e. printed circuit board.

The external resistor generates noise or picks up noise from the board and requires decoupling capacitors.

The external resistor value will drift with temperature.

The object of the present invention is to exploit the fact that the integrated inductance value is insensitive to PVT variations to create an adjustable DC current reference.

A novel fully integrated adjustable DC current reference is developed. The reference current is set by the ratio of a DC voltage generated using a band-gap reference and a tuned resistor based on an inductor reference. An AC signal is necessary to develop a relationship between the resistor tuned and the inductor reference. A computation unit which could be designed as an analog circuit is necessary to compute the value of the resistor in relationship to the reference inductor.

Classic circuits are used to develop and analyze the relationship between the reference inductor and the tunable resistor that sets the DC current reference. The fundamental novelty is the DC current reference is ultimately a function of the integrated inductance value and the DC bandgap reference voltage. According to published measured results, the value of the inductance is insensitive to process, voltage and temperature variations. Therefore, assuming the DC bandgap reference voltage is insensitive to changes in process, voltage and temperature variations, so is the DC current reference.

FIG. 1 shows a fully integrated adjustable DC current reference based on an integrated bogie reference inductor of an embodiment of the disclosed technology.

FIG. 2 shows a relationship solver computing the current based on the phase difference between V 1 and V 2 .

FIG. 3 shows an adjustable ratio matching circuit of an embodiment of the disclosed technology.

To understand the operation of the circuit the insensitivity of inductance to PVT variations is first emphasized. The model of an on-chip inductor, which in its simplest form can be just a metal trace, is complex at high frequencies in the GHz range. However, at lower frequencies (e.g. 200 MHz) the capacitors may be ignored and the impedance of a small inductor (e.g. 1 nH) can be written as Z L =jωL Bogie +R series . It is very important to note that only the inductance L Bogie is insensitive to PVT variations while R series is sensitive to PVT like any other on-chip resistor.

Embodiments of the disclosed technology will become clearer in view of the following description of the drawings.

The following arguments demonstrate that L Bogie is insensitive to PVT variations:

Theoretical formulas in Razavi [1], Lee [2], Georgescu [3] show small dependency of the metal trace thickness and strong dependency of the layout which does not vary significantly with PVT changes.

Simulations were described in the U.S. Provisional Application Ser. No. 61/690,534, and Silvaco [4] showing that changes of up to 20% in various process parameters (e.g. metal trace thickness) result in changes of 1% in inductance.

Measured results in Kang et al. [5] FIG. 10 show insensitivity of L Bogie to temperature variations especially at lower frequencies (e.g. 200 MHz).

Once the L Bogie insensitivity to PVT variations has been demonstrated the circuit in FIG. 1 the preferred embodiment can be explained.

The current through the load Z Load 107 is set as the ratio of V 1 112 and the drain source resistance R tune1 of the MOSFET in triode M tune1 108 . R tune1 is set using the voltage V tune 110 . M O 106 is a current buffer.

Due to the operational amplifier OA 1 105 the voltage V 1 112 is composed of a DC component equal to V re f DC 102 added to a sinusoidal AC component of frequency ω due to

103 connected to the positive terminal of the operational amplifier through capacitor C 104 . V srcAC 103 can and should be a sinusoidal signal generated by a crystal (e.g. 200 MHz). V re f DC 102 is a known constant voltage generated for example by a Silicon band-gap reference and designed to be insensitive to PVT variations. The following relationship holds:

V 1 =V refDC +kV srcAC   (Eq. 1)

where k is a coupling constant.

The following relationship holds characterizing the DC component of the reference current:

The tuning resistor R tune1 due to M tune1 108 is ratio matched to R tune2 due to M tune2 109 using an adjustable ratio matching circuit 116 . One can set in a digital fashion positive integers n and m such that: R tune1 =R/m, R tune2 =R/n so one can set:

An example of an adjustable ratio matching circuit 116 to perform this task is shown in FIG. 3 . The critical component of the system is the Bogie Reference Inductor 101 which is essential in generating a voltage V 2 113 using operational amplifier OA 2 111 . The following relationship holds at frequency ω the frequency of operation of V srcAC 103 between the sinusoidal components of V 2 113 and V 1 112 :

We can set R tune1 which is tuned simultaneously with R tune2 by using a relationship solver 114 between V 2 113 and V 1 112 . The relationship solver 114 determines a relationship between V 2 113 and V 1 112 . The result can be used to determine a relationship between R tune1 and jωL Bogie . An example relationship solver 114 which computes the phase difference between two sinusoidal voltages is shown in FIG. 2 .

Computing the phases φ 1 and φ 2 respectively for two ratios n 1 /m 1 and n 2 /m 2 between R tune1 and R tune2 the following equations can be written:

If V re f DC /R tune1 =I re f DCdesired , the desired DC current then the tuning process has ended and the AC signal V srcAC 103 can be turned off else one needs to adjust V tune to decrease or increase R tune1 .

The relationship solver 114 in FIG. 1 is a phase detector described in FIG. 2 . The input voltages in FIG. 2 V 2 213 and V 1 212 are the two sinusoidal input signals V 2 113 and V 1 112 in FIG. 1 . Two buffers 201 and 203 protect the circuit from loading. Two differentiators 204 and 205 remove the effect of the DC difference. The comparators 206 and 207 transform the sinusoids into square waves. The phase difference between the two square waves is determined using for example a XOR gate 208 and a low pass filter 209 . An analog to digital converter 210 converts the phase difference into a digital number. The current computation is done by a computation engine 211 using the following relationship derived from Eq. (2) and Eq. (7),

The adjustable ratio matching circuit which controls the ratio of R tune1 due to 108 to R tune2 due to M tune2 109 is shown in FIG. 3 . Each transistor M tune1 308 and 309 is composed of a number of identical unit devices M 313 . In the case of M tune1 308 using the complementary switches S W 312 and S W 311 the gate is grounded for x unit devices and connected to V tune 310 for m unit devices to operate in triode. As a result: tune

R tune ⁢ ⁢ 1 = R m ( Eq . ⁢ 9 )

where R is the triode drain source resistance of the unit transistor.

Similarly:

The integers m and n can be controlled digitally to set various matching ratios.

The factors that limit the precision of the DC current value which can be achieved using the method described are mismatch between components, DC offsets and finite gain of the operational amplifiers.

While the disclosed technology has been taught with specific reference to the above embodiments, a person having ordinary skill in the art will recognize that changes can be made in form and detail without departing from the spirit and the scope of the disclosed technology. The described embodiments are to be considered in all respects only as illustrative and not restrictive. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope. Combinations of any of the methods and apparatuses described hereinabove are also contemplated and within the scope of the invention.