Maximum voltage selection circuit and method and sub-selection circuit

This application claims the benefit of priority to People's Republic of China Patent Application Serial No. 201210227979.7, filed Jun. 29, 2012.

A maximum voltage selection circuit is generally required in an integrated circuit. The main function of the maximum voltage selection circuit is to select and output a maximum voltage from a plurality of existing voltages to supply other circuits in the integrated circuit.

FIG. 1 is a maximum voltage selection circuit with three channels of voltages. As shown in FIG. 1 , when the differences in voltage between a first input voltage VCC 1 , a second input voltage VCC 2 and a third input voltage VCC 3 are relatively large, the maximum voltage selection circuit can select a maximum voltage as an output voltage VMAX. However, since generally, neither of the first input voltage VCC 1 , the second input voltage VCC 2 and the third input voltage VCC 3 is zero volts, a gate connection of a P-type metal oxide semiconductor field effect transistor (PMOS) connected to one of the first input voltage VCC 1 , the second input voltage VCC 2 or the third input voltage VCC 3 may have inadequate driving capacity to provide the output voltage VMAX at the output of the maximum voltage selection circuit. Additionally, when the voltage differences between the first input voltage VCC 1 , the second input voltage VCC 2 and the third input voltage VCC 3 are relatively small or the voltages are the same, the PMOS devices in the maximum voltage selection circuit may not operate normally may not generate the output voltage VMAX.

This document discusses, among other things, devices systems and methods to select a maximum voltage in integrated circuits. An example of a sub-selection circuit includes an enable mode circuit and a disable mode circuit. The enable mode circuit can be configured to operate when an operating mode signal is an enable signal, employ a comparator structure, set its state as an output enable state and set states of the sub-selection circuits other than itself as output disable states, and output its input voltage as a maximum voltage via a PMOS transistor when its input voltage is larger than a reference voltage. The disable mode circuit can be configured to operate when the operating mode signal is an disable signal, employ a power latch structure, set its state as the output enable state and set the states of the sub-selection circuits other than itself as the output disable states, and output its input voltage as the maximum voltage via the PMOS transistor when its input voltage is larger than the reference voltage.

An example of a maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N input voltages, wherein N is a positive integer greater than zero. The peripheral signal circuit can provide an operating mode signal and a reference voltage to the selection circuit. The selection circuit can include N sub-selection circuits, the N input voltages are correspondingly coupled to the N sub-selection circuits, each of the sub-selection circuits determines its operating mode according to the operating mode signal, sets its state as the output enable state and sets the states of the sub-selection circuits other than itself as the output disable states, and outputs its input voltage as a maximum voltage via a PMOS transistor when its input voltage is larger than the reference voltage in the operating mode.

An example of a maximum voltage selection method includes correspondingly transmitting N input voltages to the N sub-selection circuits. The method also includes each sub-selection circuit determining its operating mode according to a current operating mode signal, and each sub-selection circuit setting its state as the output enable state and setting the states of the other sub-selection circuits other than itself as the output disable state, and outputting its input voltage as a maximum voltage via a PMOS transistor when its input voltage is larger than the reference voltage in a determined operating mode.

A system example includes a maximum voltage selection circuit, a maximum voltage selection method and a sub-selection circuit. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N input voltages, the peripheral signal circuit provides the operating mode signal and the reference voltage to the selection circuit. The selection circuit includes N sub-selection circuits, the N input voltages are correspondingly coupled to the N sub-selection circuits, each of the sub-selection circuits determines its operating mode according to the operating mode signal, and sets its state as the output enable state and sets the states of the sub-selection circuits other than itself as the output disable states, and outputs its input voltage as a maximum voltage via a PMOS transistor when its input voltage is larger than the reference voltage in the operating mode. Thus, the driving capability of the output voltage is increased, and the output voltage is ensured to be normal when the voltage differences between the multi-voltages are relatively small or the voltages are the same.

Also, the disclosure may set the sub-selection circuit according to the number of the voltages that are required to be compared, allowing the design and application of the maximum voltage selection circuit to be more flexible.

FIG. 1 is a schematic view of a maximum voltage selection circuit with three channels of voltages in the relevant art.

FIG. 2 is a schematic view of the structure of a sub-selection circuit according to some embodiments.

FIG. 3 is a schematic view of the specific structure of a first sub-selection circuit according to some embodiments.

FIG. 4 is a schematic view of the structure of a maximum voltage selection circuit according to some embodiments.

FIG. 5 is a schematic view of the specific structure of a maximum voltage selection circuit with three channels of input voltages according to some embodiments.

FIG. 6 is a flowchart of a maximum voltage selection method according to some embodiments.

FIG. 7 is a schematic view of the operating state when the maximum voltage selection circuit operates in a disable mode according to some embodiments.

FIG. 8 is a schematic view of the operating state when the maximum voltage selection circuit operates in an enable mode according to some embodiments.

In general, a maximum voltage selection circuit selects and outputs a maximum voltage from a plurality of existing voltages. A maximum voltage selection circuit can be formed by a peripheral signal circuit and a selection circuit with N channels of input voltages; N being a positive integer greater than zero. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit. The selection circuit can include N sub-selection circuits, and N input voltages coupled to the N sub-selection circuits respectively. Each of the sub-selection circuits determines its operating mode according to the operating mode signal, and when its input voltage is larger than the reference voltage in the operating mode, sets its state as the output enable state and sets the states of other sub-selection circuits as the output disable state, and outputs its input voltage as a maximum voltage through a PMOS transistor.

The subject matter of the present application is described in detail below with reference to the drawings and specific embodiments.

FIG. 2 shows an example of a sub-selection circuit. The sub-selection circuit includes an enable mode circuit 21 and a disable mode circuit 22 .

The enable mode circuit 21 is configured to operate when an operating mode signal received at an input to the enable mode circuit 21 is an enable signal. The enable mode circuit includes a comparator. When an input voltage of the enable mode circuit is larger than a reference voltage, the enable mode circuit 21 sets itself to an output enable state, sets other sub-selection circuits to an output disable state, and outputs its input voltage as a maximum voltage through a PMOS transistor.

The disable mode circuit 22 is configured to operate when the operating mode signal is a disable signal. The disable mode circuit 22 includes a power latch. When an input voltage of the disable mode circuit is larger than the reference voltage, the disable mode circuit 22 sets itself to the output enable state, sets the other sub-selection circuits to the output disable state, and outputs its input voltage as the maximum voltage through the PMOS transistor.

When there is a bias current in the circuit, the operating mode signal having a high level is used as the enable signal. When there is no bias current in the circuit, the operating mode signal having a low level is used as the disable signal.

The reference voltage is the sum of a feedback voltage and voltages of related circuits. The feedback voltage is an output voltage of the maximum voltage selection circuit fed back based on the operating mode signal.

When N equals three, and there are three channels of input voltages, these three channels of input voltages are coupled to three sub-selection circuits described above respectively. Specifically, a first input voltage VCC 1 is coupled to a first sub-selection circuit, a second input voltage VCC 2 is coupled to a second sub-selection circuit, and a third input voltage VCC 3 is coupled to a third sub-selection circuit.

Taking the first sub-selection circuit to which the first input voltage VCC 1 is coupled as an example, the first sub-selection circuit, as shown in FIG. 3 , includes a first resistor R 31 , a second resistor R 32 , a third resistor R 33 , a first PMOS transistor (or PMOS) P 31 , a second PMOS P 32 , a third PMOS P 33 , a fourth PMOS P 34 , a fifth PMOS P 35 , a sixth PMOS P 36 , a seventh PMOS P 37 , a first NMOS transistor (or NMOS) N 31 , a second NMOS N 32 , a third NMOS N 33 , a fourth NMOS N 34 , a fifth NMOS N 35 , a sixth NMOS N 36 , and an inverter OP 1 .

An end of the first resistor R 31 and the second resistor R 32 connected in parallel is connected to the first input voltage VCC 1 , another end is connected to the source of the first PMOS P 31 . The gate of the first PMOS P 31 is connected to a feedback voltage VPB. The drain of the first PMOS P 31 is its state node VO 1 , and is connected to the input of the inverter OP 1 and the drain of the third PMOS P 33 , the drain of the sixth PMOS P 36 , the drain of the first NMOS N 31 , the drain of the third NMOS N 33 and the drain of the fifth NMOS N 35 . The gate of the first NMOS N 31 is connected to the gate of the fourth NMOS N 34 and a control signal VNB corresponding to an operating mode signal VEN. The source of the first NMOS N 31 is connected to the drain of the second NMOS N 32 and the source of the fourth NMOS N 34 . The gate of the second NMOS N 32 is connected to the operating mode signal VEN, and the source is connected to a ground voltage VSS. The gate of the third NMOS N 33 is a node VO 2 for receiving the state of the second sub-selection circuit, and the source of the third NMOS N 33 is connected to the drain of the fourth NMOS N 34 , the source of the fifth NMOS N 35 and the drain of the sixth NMOS N 36 . The gate of the fifth NMOS N 35 is a node VO 3 for receiving the state of the third sub-selection circuit. The source of the sixth NMOS N 36 is connected to the ground voltage VSS through the third resistor R 33 , and the gate of the sixth NMOS N 36 is connected to an inverted signal VENB of the operating mode signal VEN. The source of the second PMOS P 32 is connected to the first input voltage VCC 1 , the gate of the second PMOS P 32 is connected to the operating mode signal VEN and the gate of the fourth PMOS P 34 , and the drain of the second PMOS P 32 is connected to the source of the third PMOS P 33 . The gate of the third PMOS P 33 is connected to the feedback voltage VPB. The source of the fourth PMOS P 34 is connected to the first input voltage VCC 1 , and the drain of the fourth PMOS P 34 is connected to the source of the fifth PMOS P 35 . The gate of the fifth PMOS P 35 is the node VO 3 for receiving the state of the third sub-selection circuit, and the drain of the fifth PMOS P 35 is connected to the source of the sixth PMOS P 36 . The gate of the sixth PMOS P 36 is the node VO 2 for receiving the state of the second sub-selection circuit. The source of the seventh PMOS P 37 is connected to the first input voltage VCC 1 , the gate of the seventh PMOS P 37 is connected to the output of the inverter OP 1 , and the drain of the seventh PMOS P 37 is connected to the output voltage VMAX.

In a more specific implementation, the first resistor R 31 and the second resistor R 32 may be implemented as one resistor.

When the operating mode signal VEN is at a high level, the control signal VNB corresponding to the operating mode signal VEN is a bias voltage, causing a bias current and causing the first NMOS N 31 and the fourth NMOS N 34 to form a current mirror, and when VEN is at a low level, the control signal VNB is at a low level.

When the operating mode signal VEN is at the high level, the first resistor R 31 , the second resistor R 32 , the first PMOS P 31 , the seventh PMOS P 37 , the first NMOS N 31 , the second NMOS N 32 , the third NMOS N 33 , the fourth NMOS N 34 , the fifth NMOS N 35 and the inverter OP 1 form the enable mode circuit 21 . The first resistor R 31 , the second resistor R 32 , the first PMOS P 31 , the first NMOS N 31 , the second NMOS N 32 , the third NMOS N 33 , and the fourth NMOS N 34 form the comparator structure. When the first input voltage VCC 1 is larger than the reference voltage, the drain current of the first PMOS P 31 will be larger than the sum of the drain currents of the first NMOS N 31 and the fourth NMOS N 34 , and thus, its state node VO 1 is set to be at the high level, i.e., output enable state, resulting the second sub-selection circuit and the third sub-selection circuit to be in the output disable state through the state node VO 1 . That is, both the node VO 2 and the node VO 3 receive the low level, then the seventh PMOS P 37 is turned on and the output voltage VMAX of the drain of the seventh PMOS P 37 is the first input voltage VCC 1 . The reference voltage is the sum of the feedback voltage VPB and a voltage VGSP. The voltage VGSP is the sum of the gate-source voltage VGS of the first PMOS P 31 and the voltage across the first resistor R 31 or the second resistor R 32 when the current of the first PMOS P 31 is equal to the sum of the currents of the first NMOS N 31 and the fourth NMOS N 34 .

Here, the seventh PMOS P 37 in each of the other sub-selection circuits is turned off. In the sub-selection circuit under discussion, since both the third NMOS N 33 and the fifth NMOS N 35 are turned off in the current branch of the fourth NMOS N 34 , VCC 1 may be maintained at the maximum value provided that the current of the first PMOS P 31 is larger than that of the first NMOS N 31 . When a certain sub-selection circuit among the other sub-selection circuits is in the output enable state, in the sub-selection circuit under discussion, the current of the first PMOS P 31 will be less than the sum of the currents of the first NMOS N 31 and the fourth NMOS N 34 , thereby causing the sub-selection circuit under discussion into the output disable state, and the sub-selection circuit under discussion can be set to the output enable state only if the current of the first PMOS P 31 is larger than the sum of the currents of the first NMOS N 31 and the fourth NMOS N 34 .

When the operating mode signal VEN is at the low level, the third resistor R 33 , the second PMOS P 32 , the third PMOS P 33 , the fourth PMOS P 34 , the fifth PMOS P 35 , the sixth PMOS P 36 , the seventh PMOS P 37 , the third NMOS N 33 , the fifth NMOS N 35 , the sixth NMOS N 36 , and the inverter OP 1 form the disable mode circuit 22 . The third resistor R 33 , the second PMOS P 32 , the third PMOS P 33 , the fourth PMOS P 34 , the fifth PMOS P 35 , the sixth PMOS P 36 , the third NMOS N 33 , the fifth NMOS N 35 and the sixth NMOS N 36 form the power latch structure. When the first input voltage VCC 1 is larger than the reference voltage, the third PMOS P 33 is turned on, and thus, its state node VO 1 is set to be at the high level, i.e., output enable state, resulting the second sub-selection circuit and the third sub-selection circuit to be in the output disable state through the state node VO 1 . That is, both the node VO 2 and the node VO 3 receive the low level, and all of the fourth PMOS P 34 , the fifth PMOS P 35 , and the sixth PMOS P 36 are turned on, the output enable state of the state node VO 1 is latched, the seventh PMOS P 37 is turned on and the output voltage VMAX of the drain of the seventh PMOS P 37 becomes the first input voltage VCC 1 . At this point, the seventh PMOS P 37 in each of the other sub-selection circuits is turned off. The reference voltage is the sum of the feedback voltage VPB, a VGS 1 of the third PMOS P 33 and a VGS 2 of the second PMOS P 32 . The on-resistance of the third PMOS P 33 is less than that of the third NMOS N 33 and the fifth NMOS N 35 , which can allow the voltage of the state node VO 1 to reach the threshold of the inverter OP 1 when the third PMOS P 33 is turned on.

Here, the third NMOS N 33 , the fifth NMOS N 35 , the fourth PMOS P 34 , the fifth PMOS P 35 and the sixth PMOS P 36 form a NOR gate with two inputs. When one of the other two sub-selection circuits is in the output enable state, the sub-selection circuit under discussion will turn into the output disable state. With regard to N channels of input voltages, a NOR gate with N−1 inputs corresponding to the sub-selection circuits for the respective channels of input voltages are required to generate the output enable state.

The first sub-selection circuit also includes a fourth resistor R 34 , a fifth resistor R 35 , an eighth PMOS P 38 and a ninth PMOS P 39 . The source of the eighth PMOS P 38 is connected to the first input voltage VCC 1 , the gate of the eighth PMOS P 38 is connected to the second input voltage VCC 2 through the fourth resistor R 34 , and the drain of the eighth PMOS P 38 is connected to the source of the ninth PMOS P 39 . The gate of the ninth PMOS P 39 is connected to the third input voltage VCC 3 through the fifth resistor R 35 , and the drain of the ninth PMOS P 39 is a voltage-protection output node PRAIL. When the first input voltage VCC 1 is the largest, both the eighth PMOS P 38 and the ninth PMOS P 39 are turned on, and the voltage-protection output node PRAIL is at the first input voltage VCC 1 .

The circuit structures of the second sub-selection circuit and the third sub-selection circuit are the same as the first sub-selection circuit. However, the second sub-selection circuit is to determine whether the second input voltage VCC 2 is the maximum voltage and the third sub-selection circuit is to determine whether the third input voltage VCC 3 is the maximum voltage.

In view of the sub-selection circuit described above, the disclosure also provides a maximum voltage selection circuit including a peripheral signal circuit 41 and a selection circuit 42 with N channels of input voltages, as shown in FIG. 4 .

The peripheral signal circuit 41 provides an operating mode signal and a reference voltage to the selection circuit 42 .

The selection circuit 42 includes N sub-selection circuits 421 , N channels of input voltages are coupled to the N sub-selection circuits 421 respectively, each of the sub-selection circuits 421 determines its operating mode according to the operating mode signal, and when its input voltage is larger than the reference voltage in the operating mode, sets itself to the output enable state, sets the other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.

The N sub-selection circuits 421 are shown in FIG. 2 , each of the sub-selection circuit 421 including an enable mode circuit 21 and a disable mode circuit 22 .

The enable mode circuit 21 is configured to operate when the operating mode signal is an enable signal. The enable mode circuit 21 includes a comparator, and when the input voltage of the enable mode circuit 21 is larger than a reference voltage, the enable mode circuit 21 sets itself to an output enable state, sets other sub-selection circuits to an output disable state, and outputs its input voltage as a maximum voltage through a PMOS.

The disable mode circuit 22 is configured to operate when the operating mode signal is a disable signal. The disable mode circuit 22 includes a power latch, and when the input voltage of the disable mode circuit 22 is larger than the reference voltage, the disable mode circuit 22 sets itself to the output enable state, sets the other sub-selection circuits to the output disable state, and outputs its input voltage as the maximum voltage through the PMOS.

When there is a bias current in the circuit, the operating mode signal having a high level is used as the enable signal, and when there is no bias current in the circuit, the operating mode signal having a low level is used as the disable signal.

The reference voltage may be the sum of a feedback voltage and voltages of related circuits. The feedback voltage can be an output voltage of the maximum voltage selection circuit fed back based on the operating mode signal.

As shown in FIG. 5 , the maximum voltage selection circuit includes a peripheral signal circuit 41 and a selection circuit 42 with three channels of input voltages, wherein the selection circuit 42 includes three sub-selection circuits, the state nodes of the three sub-selection circuits are connected to each other in turn, i.e., the state node VO 1 of the first sub-selection circuit 1 itself is connected to the node VO 2 of the second sub-selection circuit 2 and the node VO 3 of the third sub-selection circuit 3 , the state node VO 1 of the second sub-selection circuit 2 itself is connected to the node VO 2 of the first sub-selection circuit 1 and the node VO 3 of the third sub-selection circuit 3 , the state node VO 1 of the third sub-selection circuit 3 itself is connected to the node VO 3 of the first sub-selection circuit 1 and the node VO 2 of the second sub-selection circuit 2 ; further, the input voltage nodes of the three sub-selection circuits are also connected to each other in turn.

As shown in FIG. 3 , the first sub-selection circuit includes a first resistor R 31 , a second resistor R 32 , a third resistor R 33 , a first PMOS P 31 , a second PMOS P 32 , a third PMOS P 33 , a fourth PMOS P 34 , a fifth PMOS P 35 , a sixth PMOS P 36 , a seventh PMOS P 37 , a first NMOS N 31 , a second NMOS N 32 , a third NMOS N 33 , a fourth NMOS N 34 , a fifth NMOS N 35 , a sixth NMOS N 36 , and an inverter OP 1 .

An end of the first resistor R 31 and the second resistor R 32 connected in parallel is connected to the first input voltage VCC 1 , another end is connected to the source of the first PMOS P 31 . The gate of the first PMOS P 31 is connected to a feedback voltage VPB. The drain of the first PMOS P 31 is its state node VO 1 and is connected to the input of the inverter OP 1 and the drain of the third PMOS P 33 , the drain of the sixth PMOS P 36 , the drain of the first NMOS N 31 , the drain of the third NMOS N 33 and the drain of the fifth NMOS N 35 . The gate of the first NMOS N 31 is connected to the gate of the fourth NMOS N 34 and a control signal VNB corresponding to an operating mode signal VEN. The source of the first NMOS N 31 is connected to the drain of the second NMOS N 32 and the source of the fourth NMOS N 34 . The gate of the second NMOS N 32 is connected to the operating mode signal VEN, and the source is connected to a ground voltage VSS. The gate of the third NMOS N 33 is a node VO 2 for receiving the state of the second sub-selection circuit, and the source of the third NMOS N 33 is connected to the drain of the fourth NMOS N 34 , the source of the fifth NMOS N 35 and the drain of the sixth NMOS N 36 . The gate of the fifth NMOS N 35 is a node VO 3 for receiving the state of the third sub-selection circuit. The source of the sixth NMOS N 36 is connected to the ground voltage VSS through the third resistor R 33 , and the gate of the sixth NMOS N 36 is connected to an inverted signal VENB of the operating mode signal VEN. The source of the second PMOS P 32 is connected to the first input voltage VCC 1 , the gate of the second PMOS P 32 is connected to the operating mode signal VEN and the gate of the fourth PMOS P 34 , and the drain of the second PMOS P 32 is connected to the source of the third PMOS P 33 . The gate of the third PMOS P 33 is connected to the feedback voltage VPB. The source of the fourth PMOS P 34 is connected to the first input voltage VCC 1 , and the drain of the fourth PMOS P 34 is connected to the source of the fifth PMOS P 35 . The gate of the fifth PMOS P 35 is the node VO 3 for receiving the state of the third sub-selection circuit, and the drain of the fifth PMOS P 35 is connected to the source of the sixth PMOS P 36 . The gate of the sixth PMOS P 36 is the node VO 2 for receiving the state of the second sub-selection circuit. The source of the seventh PMOS P 37 is connected to the first input voltage VCC 1 , the gate of the seventh PMOS P 37 is connected to the output of the inverter OP 1 , and the drain of the seventh PMOS P 37 is connected to the output voltage VMAX.

In a more specific implementation, the first resistor R 31 and the second resistor R 32 may be implemented as one resistor.

When the operating mode signal VEN is at the high level, the first resistor R 31 , the second resistor R 32 , the first PMOS P 31 , the seventh PMOS P 37 , the first NMOS N 31 , the second NMOS N 32 , the third NMOS N 33 , the fourth NMOS N 34 , the fifth NMOS N 35 and the inverter OP 1 form the enable mode circuit 21 . The first resistor R 31 , the second resistor R 32 , the first PMOS P 31 , the first NMOS N 31 , the second NMOS N 32 , the third NMOS N 33 , and the fourth NMOS N 34 form the comparator structure. When the first input voltage VCC 1 is larger than the reference voltage, the drain current of the first PMOS P 31 will be larger than the sum of the drain currents of the first NMOS N 31 and the fourth NMOS N 34 , and thus, its state node VO 1 is set to be at the high level, i.e., output enable state, causing the second sub-selection circuit and the third sub-selection circuit to be in the output disable states through the state node VO 1 . That is, both the node VO 2 and the node VO 3 receive the low level, and then the seventh PMOS P 37 is turned on and the output voltage VMAX of the drain of the seventh PMOS P 37 is the first input voltage VCC 1 . The reference voltage is the sum of the feedback voltage VPB and a voltage VGSP. The voltage VGSP is the sum of the VGS of the first PMOS P 31 and the voltage across the first resistor R 31 or the second resistor R 32 when the current of the first PMOS P 31 is equal to the sum of the currents of the first NMOS N 31 and the fourth NMOS N 34 .

Here, the seventh PMOS P 37 in each of the other sub-selection circuits is turned off; in the sub-selection circuit under discussion, since both the third NMOS N 33 and the fifth NMOS N 35 are turned off in the current branch of the fourth NMOS N 34 , VCC 1 may be maintained at the maximum value provided that the current of the first PMOS P 31 is larger than that of the first NMOS N 31 ; when a certain sub-selection circuit among the other sub-selection circuits is in the output enable state, in the sub-selection circuit under discussion, the current of the first PMOS P 31 will be less than the sum of the currents of the first NMOS N 31 and the fourth NMOS N 34 , thereby resulting in that the sub-selection circuit under discussion is in the output disable state, and the sub-selection circuit under discussion can be set to the output enable state only if the current of the first PMOS P 31 is larger than the sum of the currents of the first NMOS N 31 and the fourth NMOS N 34 .

When the operating mode signal VEN is at the low level, the third resistor R 33 , the second PMOS P 32 , the third PMOS P 33 , the fourth PMOS P 34 , the fifth PMOS P 35 , the sixth PMOS P 36 , the seventh PMOS P 37 , the third NMOS N 33 , the fifth NMOS N 35 , the sixth NMOS N 36 , and the inverter OP 1 form the disable mode circuit 22 . The third resistor R 33 , the second PMOS P 32 , the third PMOS P 33 , the fourth PMOS P 34 , the fifth PMOS P 35 , the sixth PMOS P 36 , the third NMOS N 33 , the fifth NMOS N 35 and the sixth NMOS N 36 form the power latch structure, when the first input voltage VCC 1 is larger than the reference voltage, the third PMOS P 33 is turned on, and thus, its state node VO 1 is set to be high-level, i.e., output enable state, causing the second sub-selection circuit and the third sub-selection circuit to be in the output disable state through the state node VO 1 . That is, both the node VO 2 and the node VO 3 receive the low level, the all of the fourth PMOS P 34 , the fifth PMOS P 35 , and the sixth PMOS P 36 are turned on, the output enable state of the state node VO 1 is latched, the seventh PMOS P 37 is turned on and the output voltage VMAX of the drain of the seventh PMOS P 37 becomes the first input voltage VCC 1 . Here, the seventh PMOS P 37 in each of the other sub-selection circuits is turned off. The reference voltage is the sum of the feedback voltage VPB, a VGS 1 of the third PMOS P 33 and a VGS 2 of the second PMOS P 32 . The on-resistance of the third PMOS P 33 is less than that of the third NMOS N 33 and the fifth NMOS N 35 , which can allow the voltage of the state node VO 1 to reach the threshold of the inverter OP 1 when the third PMOS P 33 is turned on.

Here, the third NMOS N 33 , the fifth NMOS N 35 , the fourth PMOS P 34 , the fifth PMOS P 35 and the sixth PMOS P 36 form a NOR gate with two inputs. When one of the other two sub-selection circuits is in the output enable state, the sub-selection circuit under discussion will turn into the output disable state. With regard to N channels of input voltages, a NOR gate with N−1 inputs corresponding to the sub-selection circuits for the respective channels of input voltages are required to generate the output enable state.

The first sub-selection circuit further includes a fourth resistor R 34 , a fifth resistor R 35 , an eighth PMOS P 38 and a ninth PMOS P 39 . The source of the eighth PMOS P 38 is connected to the first input voltage VCC 1 , the gate of the eighth PMOS P 38 is connected to the second input voltage VCC 2 through the fourth resistor R 34 , and the drain of the eighth PMOS P 38 is connected to the source of the ninth PMOS P 39 . The gate of the ninth PMOS P 39 is connected to the third input voltage VCC 3 through the fifth resistor R 35 , and the drain of the ninth PMOS P 39 is a voltage-protection output node PRAIL. When the first input voltage VCC 1 is the largest, both the eighth PMOS P 38 and the ninth PMOS P 39 are turned on, and the voltage-protection output node PRAIL is at the first input voltage VCC 1 .

The circuit structures of the second sub-selection circuit and the third sub-selection circuit are the same as the first sub-selection circuit. However, the second sub-selection circuit is to determine whether the second input voltage VCC 2 is the maximum voltage, and the third sub-selection circuit is to determine whether the third input voltage VCC 3 is the maximum voltage.

In the maximum voltage selection circuit described above, when the PMOS transistor is turned on by outputting a low level voltage to the gate of the PMOS transistor through an inverter, the maximum voltage having a strong driving capability is output.

In view of the maximum voltage selection circuit described above, the disclosure also provides a maximum voltage selection method, as shown in the flow diagram of FIG. 6 . The method includes the following.

Block 101 : N channels of input voltages are input to N sub-selection circuits respectively.

Block 102 : Each sub-selection circuit determines its operating mode according to the current operating mode signal. The operating mode signal having the high level is used as an enable signal, and the operating mode signal having the low level is used as a disable signal.

Block 103 : for each of the sub-selection circuits in a determined operating mode, when the input voltage is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state, sets the other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS transistor.

In a more specific implementation, when the operating mode signal is the enable signal and it is determined that the input voltage is larger than a reference voltage by using a circuit of a comparator structure, the sub-selection circuit is set to an output enable state and the other sub-selection circuits are set to the output disable state, and the PMOS transistor is turned on to output a maximum voltage and the input voltage of the sub-selection circuit is output as the maximum voltage.

When the operating mode signal is the disable signal and it is determined that the input voltage is larger than a reference voltage by using a circuit of a power latch structure, the sub-selection circuit is set to an output enable state and the other sub-selection circuits are set to the output disable state, and the PMOS transistor is turned on to output a maximum voltage and the input voltage of the sub-selection circuit is output as the maximum voltage.

The reference voltage is an output voltage of the maximum voltage selection circuit fed back based on the operating mode signal.

In the disclosure, tests are carried out on the maximum voltage selection circuit shown in FIG. 5 in an enable mode and a disable mode, respectively, and the results of the tests are shown in FIG. 7 and FIG. 8 , respectively.

FIG. 7 shows an example of a timing diagram of the operating state of the maximum voltage selection circuit operating in a disable mode. It can be seen that the output voltage VMAX of the maximum voltage selection circuit is the first input voltage VCC 1 in the beginning. When the first input voltage VCC 1 is equal to the second input voltage VCC 2 , the maximum voltage selection circuit continues to output the first input voltage VCC 1 . When the second input voltage VCC 2 is larger than the first input voltage VCC 1 by a certain threshold, the output voltage VMAX of the maximum voltage selection circuit is the second input voltage VCC 2 . When the second input voltage VCC 2 is equal to the third input voltage VCC 3 , the maximum voltage selection circuit continues to output the second input voltage VCC 2 . When the third input voltage VCC 3 is larger than the second input voltage VCC 2 by a certain threshold, the output voltage VMAX of the maximum voltage selection circuit is the third input voltage VCC 3 . Therefore, the maximum voltage selection circuit can ensure that the output voltage is normal when the voltage differences between the multi-voltages are relatively small or the same in the disable mode. Here, the threshold may be adjusted by adjusting the driving capability of the PMOS of the disable mode circuit in the maximum voltage selection circuit.

FIG. 8 shows an example of a timing diagram of the operating state of the maximum voltage selection circuit operating in an enable mode. It can be seen that the threshold, at which the maximum voltage selection circuit selects to switch the maximum voltage, is smaller, and the selection of the maximum voltage is more sensitive when compared to the operating state of the maximum voltage selection circuit operating in the disable mode.

What are described above are merely examples and are not intended to limit the scope of the disclosure. The above description is intended to be illustrative, and not restrictive. The above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.