Pixel circuit, active sensing array, sensing device and driving method thereof

This application claims the priority benefit of Taiwan application serial no. 102100298, filed on Jan. 4, 2013. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The technical field relates to a sensing technique, and more particularly, to a sensing device and a pixel circuit, an active sensing array, and a driving method thereof.

Along with the development of optoelectronic technology, sensing devices have been broadly applied to different technical fields, such as optical image sensors, digital radiography sensors (DRS), and touch screen sensors. A sensing device is mainly composed of an active sensing array, and the active sensing array includes a plurality of pixel circuits.

In order to meet the high security demand, a sensing device is designed to have high sensitivity, so that the pixel circuit can detect incident energy of low-dose radiation. Besides, in order to meet the demand for high resolution, the area of a single pixel circuit is relatively reduced, and accordingly the photosensitive area of a sensing element in the pixel circuit is reduced. It should be noted that the intensity of an electric signal generated by the pixel circuit is drastically reduced with the decrease in the radiation dose of the incident energy and the photosensitive area of the sensing element.

The characteristic differences between transistors in the pixel circuit become obvious and can not be neglected due to the weak electric signal. For example, the threshold voltage of each transistor changes with process variation. Besides, when the transistors have different threshold voltages, different sensing results will be produced even though the same incident energy is supplied to each pixel circuit. As a result, sensing errors will be produced.

To resolve the problem mentioned above, some techniques for compensating the threshold voltages of the transistors in a pixel circuit have been developed, such as the “Investigation of gain non-uniformities in the two TFT, current programmed amorphous silicon active pixel sensor for fluoroscopy, chest radiography and mammography tomosynthesis applications” published by N. Safavian et al. in volume 7622 of proceedings of SPIE and the “TFT active image sensor with current-mode readout circuit for digital x-ray fluoroscopy” published by N. Safavian et al. in volume 5969 of proceedings of SPIE.

The technique provided by N. Safavian et al. in the volume 7622 of the proceedings of SPIE cannot provide regional compensation or one-time compensation to the pixel circuits (i.e., cannot effectively compensate each pixel circuit in an active sensing array). Additionally, the pixel circuit disclosed by N. Safavian in the volume 5969 of the proceedings of SPIE has a 3-transistor (3T) structure. Thus, the pixel circuit has a large layout area therefore can only be applied to low-resolution sensing devices.

Thereby, how to eliminate the sensing errors caused by the characteristic differences between different elements when the resolution and sensitivity of a sensing device are improved has become a major subject in the design of sensing devices.

The disclosure provides a pixel circuit, an active sensing array, a sensing device, and a driving method thereof, in which sensing error caused by characteristic differences between different elements is avoided at the same when the resolution and sensitivity of the sensing device are improved.

The disclosure provides a pixel circuit. The pixel circuit is electrically connected to a first scan line, a second scan line, and a data line and includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to a sensing element, and the data line. The reset transistor is electrically connected to the first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and the second scan line. During a compensation period, the reset transistor is turned on in response to a first scanning pulse from the first scan line, so that the sensing transistor is connected into a diode configuration, and the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration in response to switching of a level of the data line.

The disclosure provides a driving method of a pixel circuit. The pixel circuit includes a sensing transistor, a reset transistor, and a storage capacitor. The driving method includes following steps. A data line, a first scan line, and a second scan line are configured to electrically connect the pixel circuit. Wherein, the sensing transistor is electrically connected to a sensing element and the data line, the reset transistor is electrically connected to the first scan line and the sensing transistor, and the storage capacitor is electrically connected to the sensing transistor and the second scan line. During a compensation period, a first scanning pulse is provided to the first scan line to turn on the reset transistor. The sensing transistor is connected into a diode configuration through the turned-on reset transistor. The level of the data line is switched so that the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration.

The disclosure provides an active sensing array. The active sensing array includes M pixel rows. The M pixel rows are corresponding to M first scan lines, M second scan lines, and a plurality of data lines. An i th pixel row is electrically connected to an i th first scan line, an i th second scan line, and the data lines, where M is a positive integer, i is an integer, and 1≦i≦M. The i th pixel row includes a plurality of pixel circuits, and each pixel circuit of the i th pixel row includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to a sensing element and one of the data lines. The reset transistor is electrically connected to the i th first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and the i th second scan line. During a compensation period, the reset transistors of the 1 st to the N th pixel rows are turned on in response to N first scanning pulses from the 1 st to the N th first scan lines, so that the sensing transistors of the 1 st to the N th pixel rows are respectively connected into a diode configuration, where N is an integer not greater than M. Besides, during the compensation period, the storage capacitors of the 1 st to the N th pixel rows charge and discharge to threshold voltages of the sensing transistors having the diode configuration of the 1 st to the N th pixel rows through the sensing transistors having the diode configuration in response to switching of levels of the data lines.

The disclosure provides a driving method of an active sensing array. The active sensing array includes M pixel rows, an i th pixel row includes a plurality of pixel circuits, and each pixel circuit includes a sensing transistor, a reset transistor, and a storage capacitor, where M is a positive integer, i is an integer, and 1≦i≦M. The driving method includes following steps. M first scan lines, M second scan lines, and a plurality of data lines are configured to electrically connect the M pixel rows, wherein the i th pixel row is electrically connected to an i th first scan line, an i th second scan line, and the data lines. During a compensation period, N first scanning pulses are provided to the 1 st to the N th first scan lines to turn on the reset transistors of the 1 st to the N th pixel rows, where N is an integer not greater than M. The sensing transistors of the 1 st to the N th pixel rows are respectively connected into a diode configuration through the turned-on reset transistors of the 1 st to the N th pixel rows. The levels of the data lines are switched so that the storage capacitors of the 1 st to the N th pixel rows charge and discharge to threshold voltages of the sensing transistors having the diode configuration through the sensing transistors having the diode configuration.

The disclosure provides a sensing device. The sensing device includes at least one sensing element and an active sensing array. The active sensing array includes at least one pixel circuit. The at least one pixel circuit is electrically connected to a first scan line, a second scan line, and a data line and includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to the at least one sensing element and the data line. The reset transistor is electrically connected to the first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and the second scan line. During a compensation period, the reset transistor is turned on in response to a first scanning pulse from the first scan line, so that the sensing transistor is connected into a diode configuration, and the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration in response to switching of a level of the data line.

Several exemplary embodiments accompanied with figures are described in detail below to further describe the disclosure in details.

The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure.

FIG. 1A is a diagram of a pixel circuit according to an exemplary embodiment of the disclosure.

FIG. 1B is a diagram of a pixel circuit according to another exemplary embodiment of the disclosure.

FIG. 2 is a signal timing diagram for illustrating a pixel circuit according to an exemplary embodiment of the disclosure.

FIG. 3 is a diagram of a sensing device according to an exemplary embodiment of the disclosure.

FIG. 4 is a signal timing diagram for illustrating a sensing device according to an exemplary embodiment of the disclosure.

FIG. 5 is a signal timing diagram for illustrating a sensing device according to another exemplary embodiment of the disclosure.

FIG. 6 is a signal timing diagram for illustrating a sensing device according to yet another exemplary embodiment of the disclosure.

FIG. 1A is a diagram of a pixel circuit according to an exemplary embodiment of the disclosure. Referring to FIG. 1A , the pixel circuit 100 is electrically connected to a first scan line 110 a , a second scan line 110 b , and a data line 120 and includes a reset transistor M 11 , a sensing transistor M 12 , and a storage capacitor C 1 . The sensing transistor M 12 is electrically connected to a sensing element 101 and the data line 120 . The reset transistor M 11 is electrically connected to the first scan line 110 a and the sensing transistor M 12 . The storage capacitor C 1 is electrically connected to the sensing transistor M 12 and the second scan line 110 b.

In the embodiment illustrated in FIG. 1A , the sensing element 101 is disposed in the pixel circuit 100 . Even though the embodiment illustrated in FIG. 1A demonstrates the disposition of the sensing element 101 , it is not intended to limit the scope of the disclosure. FIG. 1B is a diagram of a pixel circuit according to another exemplary embodiment of the disclosure. As shown in FIG. 1B , the sensing element 101 is disposed outside the pixel circuit 100 . In other words, those skilled in the art can dispose the sensing element 101 inside or outside the pixel circuit 100 according to the design requirement. Additionally, in yet another embodiment, the sensing element 101 may also be stacked on the pixel circuit 100 .

In an actual application, the reset transistor M 11 and the sensing transistor M 12 may be bipolar junction transistors (BJT), metal oxide semiconductor (MOS) transistors, or any other type of transistors. For example, in the embodiment illustrated in FIG. 1A , the reset transistor M 11 and the sensing transistor M 12 are composed of N-channel metal oxide semiconductor (NMOS) transistors. Thus, regarding the structure detail of the pixel circuit 100 in FIG. 1A , the sensing transistor M 12 and the reset transistor M 11 respectively include a first terminal (for example, drain), a second terminal (for example, source), and a control terminal (for example, gate).

The first terminal of the sensing transistor M 12 is electrically connected to the data line 120 , the second terminal of the sensing transistor M 12 is electrically connected to a ground, and the control terminal of the sensing transistor M 12 is electrically connected to the sensing element 101 . The first terminal of the reset transistor M 11 is electrically connected to the first terminal of the sensing transistor M 12 , the second terminal of the reset transistor M 11 is electrically connected to the control terminal of the sensing transistor M 12 , and the control terminal of the reset transistor M 11 is electrically connected to the first scan line 110 a . Besides, a first end of the storage capacitor C 1 is electrically connected to the control terminal of the sensing transistor M 12 , and the second end of the storage capacitor C 1 is electrically connected to the second scan line 110 b.

The pixel circuit 100 senses an incident energy E. The corresponding sensing result can be read through a reading circuit 130 . The reading circuit 130 is electrically connected to the data line 120 through a switch SW 1 . It should be noted that in order to eliminate the sensing errors caused by characteristic differences between different elements, the pixel circuit 100 first compensates the threshold voltages of transistors during a compensation period. Then, the pixel circuit 100 senses the incident energy E during a sensing period and generates a corresponding sensing current during a reading period.

An embodiment of the disclosure will be described with reference to FIG. 2 in order to allow those skilled in the art to better understand the disclosure. FIG. 2 is a signal timing diagram for illustrating a pixel circuit according to an exemplary embodiment of the disclosure. Below, the operation details of the pixel circuit 100 will be explained with reference to both FIG. 1A and FIG. 2 . In FIG. 1A and FIG. 2 , the reference numeral S 11 represents a signal transmitted to the first scan line 110 a , the reference numeral S 12 represents a signal transmitted to the second scan line 110 b , and the reference numeral S 13 represents a signal for controlling the switch SW 1 .

As shown in FIG. 1A and FIG. 2 , during a compensation period T 21 , the reset transistor M 11 receives a first scanning pulse PU 21 from the first scan line 110 a . Thus, the reset transistor M 11 is turned on in response to the first scanning pulse PU 21 . When the reset transistor M 11 is turned on, the first terminal and the control terminal of the sensing transistor M 12 are electrically connected with each other, so that the sensing transistor M 12 is connected into a diode configuration. Besides, during the first half period for transmitting the first scanning pulse PU 21 , the switch SW 1 receives a pulse PU 22 and accordingly is turned on. Moreover, when the switch SW 1 is turned on, the level of the data line 120 is maintained at a bias voltage through the reading circuit 130 . Thus, the bias voltage from the data line 120 charges the storage capacitor C 1 through the sensing transistor M 12 having the diode configuration until the storage capacitor C 1 is charged to the bias voltage. Namely, during the first half transmission period of the first scanning pulse PU 21 , the voltage VG 1 at the control terminal of the sensing transistor M 12 increases to the bias voltage.

On the other hand, during the second half period for transmitting the first scanning pulse PU 21 , the switch SW 1 does not receive any pulse and therefore is turned off. In addition, since the switch SW 1 is turned off, the data line 120 is maintained in a floating state. Thus, the storage capacitor C 1 discharges through the sensing transistor M 12 having the diode configuration, so that the voltage VG 1 at the control terminal of the sensing transistor M 12 gradually decreases. It should be noted that when the voltage VG 1 decreases to the threshold voltage of the sensing transistor M 12 , the sensing transistor M 12 is automatically turned off, so that the storage capacitor C 1 stops discharging. Namely, during the second half transmission period of the first scanning pulse PU 21 , the storage capacitor C 1 discharges to the threshold voltage of the sensing transistor M 12 .

In other words, during the compensation period T 21 , the reset transistor M 11 is turned on in response to the first scanning pulse PU 21 from the first scan line 110 a , so that the sensing transistor M 12 is connected into the diode configuration. On the other hand, the data line 120 is sequentially switched to the bias voltage and the floating state along with the turn-on and turn-off the switch SW 1 . Thus, the storage capacitor C 1 charges and discharges to the threshold voltage of the sensing transistor M 12 through the sensing transistor M 12 having the diode configuration in response to switching of the level of the data line 120 , so as to accomplish the compensation of the pixel circuit 100 .

After the compensation period T 21 , the pixel circuit 100 enters a sensing period T 22 . During the sensing period T 22 , the pixel circuit 100 senses an incident energy E. Because there is no scanning pulse on the first scan line 110 a or the second scan line 110 b , the sensing transistor M 12 and the reset transistor M 11 are both turned off. Besides, an incident energy E is supplied to the sensing element 101 . In the embodiment illustrated in FIG. 1A , the incident energy E is light energy. Namely, the incident energy E may be visible light or invisible light (for example, X ray). Additionally, the sensing element 101 may be a photodiode, a photoresistor, a photoconductor, or a phototransistor.

In another embodiment, the incident energy E may also be mechanical energy, and the sensing element 101 may be a mechanical energy sensor, such as a pressure sensor. In yet another embodiment, the incident energy E may also be thermal energy, and the sensing element 101 may be a temperature sensing element. Similarly, in still another embodiment, the incident energy E may also be any other type of detectable energy, and the sensing element 101 may be a corresponding sensor which is capable of sensing the detectable energy.

Thereby, the sensing element 101 transfers the incident energy E into a corresponding electric signal. For example, the sensing element 101 generates a corresponding sensing voltage according to the intensity of the incident energy E and stores the sensing voltage into the storage capacitor C 1 , so that the voltage VG 1 at the control terminal of the sensing transistor M 12 changes relatively. For example, during the sensing period T 22 , the falling speed of the voltage VG 1 is proportional to the intensity of the incident energy E.

After the sensing period T 22 , the pixel circuit 100 enters a reading period T 23 . During the reading period T 23 , the pixel circuit 100 still cannot receive any scanning pulse from the first scan line 110 a , and accordingly the reset transistor M 11 is still turned off. Additionally, the pixel circuit 100 receives a second scanning pulse PU 23 from the second scan line 110 b . Thus, the sensing transistor M 12 generates a corresponding sensing current in response to the second scanning pulse PU 23 and the voltage stored in the storage capacitor C 1 . Moreover, during the reading period T 23 , the switch SW 1 receives a pulse PU 24 therefore is turned on. Thus, the reading circuit 130 receives the sensing current from the data line 120 through the turned-on switch SW 1 and generates a corresponding sensing result according to the sensing current.

It should be mentioned that the sensing current generated by the sensing transistor M 12 is proportional to the voltage difference ΔV between the voltage VG 1 and the threshold voltage of the sensing transistor M 12 . Besides, the threshold voltage of the sensing transistor M 12 is already stored in the storage capacitor C 1 during the compensation period T 21 , and the voltage VG 1 includes the voltage stored in the storage capacitor C 1 . Thus, the voltage difference ΔV is not affected by the threshold voltage of the sensing transistor M 12 . In other words, the pixel circuit 100 charges and discharges the storage capacitor C 1 to the threshold voltage of the sensing transistor M 12 during the compensation period T 21 and drives the sensing transistor M 12 by the second scanning pulse PU 23 and the voltage stored in the storage capacitor C 1 during the reading period T 23 . Accordingly, the sensing current generated by the sensing transistor M 12 is not affected by the threshold voltage thereof, so that the sensing result generated by the reading circuit 130 is prevented from being affected by the threshold voltage of the transistor.

FIG. 3 is a diagram of a sensing device according to an exemplary embodiment of the disclosure. Referring to FIG. 3 , the sensing device 300 includes an active sensing array 310 , and the active sensing array 310 includes a plurality of pixel circuits (for example, pixel circuits 311 - 314 ), a plurality of first scan lines (for example, first scan lines 321 a and 322 a ), a plurality of second scan lines (for example, second scan lines 321 b and 322 b ), and a plurality of data lines (for example, data lines 331 and 332 ). Each row of pixel circuits constitutes a pixel row and is corresponding to one of the first scan lines and one of the second scan lines. For example, the pixel circuits (for example, 311 and 312 ) in the first row constitute the first pixel row and are electrically connected to the first scan line 321 a , the second scan line 321 b , and the data lines. The pixel circuits (for example, 313 and 314 ) in the second row constitute the second pixel row and are electrically connected to the first scan line 322 a , the second scan line 322 b , and the data lines.

In other words, the active sensing array 310 includes M pixel rows, and the M pixel rows are corresponding to M first scan lines, M second scan lines, and a plurality of data lines. The i th pixel row is electrically connected to the i th first scan line, the i th second scan line, and the data lines, where M is a positive integer, i is an integer, and 1≦i≦M. In addition, each column of pixel circuits is corresponding to a data line. For example, the pixel circuits 311 and 313 in the first column are electrically connected to the data line 331 , and the pixel circuits 312 and 314 in the second column are electrically connected to the data line 332 .

In other words, each pixel circuit is electrically connected to a first scan line, a second scan line, and a data line. Besides, each pixel circuit in the active sensing array 310 has a circuit structure similar to that of the pixel circuit 100 illustrated in FIG. 1A . For example, the pixel circuit 311 includes a sensing element 341 , a reset transistor M 1 _ 1 , a sensing transistor M 1 _ 2 , and a storage capacitor C 31 . The connection and detail operation of aforementioned elements can be referred to related descriptions of the sensing element 101 , the reset transistor M 11 , the sensing transistor M 12 , and the storage capacitor C 1 in FIG. 1A . Similarly, the connections and detail operations of the sensing elements 342 - 344 , the reset transistors M 2 _ 1 -M 4 _ 1 , the sensing transistors M 2 _ 2 -M 4 _ 2 , and the storage capacitors C 32 -C 34 in the pixel circuits 312 - 314 can be deduced by analogy.

The sensing device 300 further includes a plurality of switches (for example, switches SW 31 and SW 32 ), a plurality of reading circuits (for example, reading circuits 351 and 352 ), a scanning circuit 360 and a switching circuit 370 . Each data line is electrically connected to one reading circuit through one switch. For example, the switch SW 31 is electrically connected between the data line 331 and the reading circuit 351 , and the switch SW 32 is electrically connected between the data line 332 and the reading circuit 352 .

Moreover, each reading circuit includes an operational amplifier and a capacitor. The reading circuit 351 includes an operational amplifier OP 31 and a capacitor C 35 . The first input terminal of the operational amplifier OP 31 is electrically connected to the first terminal of the switch SW 31 , and the second input terminal of the operational amplifier OP 31 receives a bias voltage VB 3 . The first end of the capacitor C 35 is electrically connected to the first input terminal of the operational amplifier OP 31 , and the second end of the capacitor C 35 is electrically connected to the output terminal of the operational amplifier OP 31 . The operational amplifier OP 31 and the capacitor C 35 constitute an integrator. Thus, when the switch SW 31 is turned on, the data line 331 is biased at the bias voltage VB 3 through the reading circuit 351 and the reading circuit 351 integrates the sensing current from the data line 331 to generate a corresponding sensing result. Similarly, the reading circuit 352 includes an operational amplifier OP 32 and a capacitor C 36 , and the circuit structure of the reading circuit 352 is similar to that of the reading circuit 351 therefore will not be repeated herein.

On the other hand, the switching circuit 370 is electrically connected between the scanning circuit 360 and the active sensing array 310 and includes a plurality of switching units (for example, switching units 371 and 372 ). Each switching unit includes four terminals 1 - 4 . Taking the switching unit 371 as an example, the four terminals 1 - 4 thereof are electrically connected to a driving channel of the scanning circuit 360 , the ground, the first scan line 321 a , and the second scan line 321 b respectively. Similarly, the four terminals 1 - 4 of the switching unit 372 are electrically connected to a driving channel of the scanning circuit 360 , the ground, the first scan line 322 a , and the second scan line 322 b respectively. In addition, each switching unit has two states. In the first state, the first terminal 1 and the third terminal 3 of the switching unit are electrically connected with each other, and the second terminal 2 and the fourth terminal 4 of the switching unit are electrically connected with each other. In the second state, the first terminal 1 and the fourth terminal 4 of the switching unit are electrically connected with each other, and the second terminal 2 and the third terminal 3 of the switching unit are electrically connected with each other.

FIG. 4 is a signal timing diagram for illustrating a sensing device according to an exemplary embodiment of the disclosure. In FIG. 3 and FIG. 4 , the reference numerals S 31 and S 33 represent signals transmitted to the first scan lines 321 a and 322 a , the reference numerals S 32 and S 34 represent signals transmitted to the second scan lines 321 b and 322 b , and the reference numeral S 35 represents a signal for controlling the switches SW 31 and SW 32 . The operation of the sensing device 300 will be explained in detail with reference to the elements illustrated in FIG. 3 and the timing diagram in FIG. 4 .

The pixel circuits 311 - 314 sequentially enter the compensation period T 41 , a sensing period T 42 , and a reading period T 43 . During the compensation period T 41 , the switching units 371 and 372 in the switching circuit 370 are switched to the first state, and the scanning circuit 360 sequentially transmits first scanning pulses PU 41 and PU 42 . Thus, the first scan lines 321 a and 322 a respectively receive the first scanning pulses PU 41 and PU 42 through the switching circuit 370 , and the second scan lines 321 b and 322 b are switched to the ground level.

The pixel circuits 311 and 312 in the first pixel row receive the first scanning pulse PU 41 from the first scan line 321 a , so that the reset transistors M 1 _ 1 and M 2 _ 1 are turned on. Namely, the reset transistors (for example, M 1 _ 1 and M 2 _ 1 ) in the first pixel row are turned on in response to the first scanning pulse PU 41 from the 1 st first scan line 321 a . When the reset transistors M 1 _ 1 and M 2 _ 1 are turned on, the sensing transistors M 1 _ 2 and M 2 _ 2 are connected into a diode configuration. Namely, the sensing transistors (for example, M 1 _ 2 and M 2 _ 2 ) in the first pixel row are connected into the diode configuration. Additionally, during the transmission period of the first scanning pulse PU 41 , the sensing device 300 first turns on the switches SW 31 and SW 32 by using the pulse PU 43 and then turns off the switches SW 31 and SW 32 .

In other words, during the transmission period of the first scanning pulse PU 41 , the switches SW 31 and SW 32 are sequentially turned on and off, so that the data lines 331 and 332 are sequentially switched to the bias voltage VB 3 and the floating state. Correspondingly, along with the level change of the data lines 331 and 332 , the storage capacitor C 31 in the pixel circuit 311 charges and discharges to the threshold voltage of the sensing transistor M 1 _ 2 , and the storage capacitor C 32 in the pixel circuit 312 charges and discharges to the threshold voltage of the sensing transistor M 2 _ 2 . Namely, the storage capacitors (for example, C 31 and C 32 ) in the first pixel row charge and discharge to the threshold voltage of the sensing transistor (for example, M 1 _ 2 and M 2 _ 2 ) having the diode configuration through the sensing transistors (for example, M 1 _ 2 and M 2 _ 2 ) having the diode configuration in the first pixel row in response to switching of the levels of the data lines.

Next, the pixel circuits 313 and 314 in the second pixel row receive the first scanning pulse PU 42 from the first scan line 322 a , so that the reset transistors M 3 _ 1 and M 4 _ 1 are turned on and accordingly the sensing transistors M 3 _ 2 and M 4 _ 2 are connected into the diode configuration. Namely, the reset transistors (for example, M 3 _ 1 and M 4 _ 1 ) in the second pixel row are turned on in response to the first scanning pulse PU 42 from the first scan line 322 a , so that the sensing transistors (for example, M 3 _ 2 and M 4 _ 2 ) in the second pixel row are respectively connected into the diode configuration.

During the period for transmitting the first scanning pulse PU 42 , the sensing device 300 first turns on the switches SW 31 and SW 32 by using the pulse PU 44 and then turns off the switches SW 31 and SW 32 . Thus, during the transmission period of the first scanning pulse PU 42 , the data lines 331 and 332 are sequentially switched to the bias voltage VB 3 and the floating state. Along with the level change of the data lines 331 and 332 , the storage capacitor C 33 in the pixel circuit 313 charges and discharges to the threshold voltage of the sensing transistor M 3 _ 2 , and the storage capacitor C 34 in the pixel circuit 314 charges and discharges to the threshold voltage of the sensing transistor M 4 _ 2 . Namely, the storage capacitors (for example, C 33 and C 34 ) in the second pixel row charge and discharge to the threshold voltages of the sensing transistors (for example, M 3 _ 2 and M 4 _ 2 ) having the diode configuration in the second pixel row through the sensing transistors (for example, M 3 _ 2 and M 4 _ 2 ) having the diode configuration in response to switching of the levels of the data lines.

In other words, during the compensation period T 41 , the sensing device 300 first compensates the pixel circuits (for example, 311 and 312 ) in the first pixel row and then compensates the pixel circuits (for example, 313 and 314 ) in the second pixel row. Accordingly, the pixel rows are compensated one by one during the compensation period T 41 . Thus, the storage capacitor in each pixel circuit charges and discharges to the threshold voltage of the sensing transistor during the compensation period T 41 .

It should be mentioned that the embodiment illustrated in FIG. 4 exemplarily describes the technique of compensating each pixel circuit during the compensation period T 41 but is not intended to limit the scope of the disclosure. FIG. 5 is a signal timing diagram for illustrating a sensing device according to another exemplary embodiment of the disclosure. As shown in FIG. 5 , during the compensation period T 41 , the first scanning pulses PU 41 and PU 42 are transmitted to the first scan lines 321 a and 322 a at the same time. Besides, during the period for transmitting both the first scanning pulses PU 41 and PU 42 , the sensing device 300 first turns on the switches SW 31 and SW 32 by using the pulse PU 43 and then turns off the switches SW 31 and SW 32 . Thus, the sensing device 300 can compensate the pixel circuits 311 - 314 in the first and the second pixel rows at the same time.

In other words, in the embodiment illustrated in FIG. 5 , every two pixel rows are regarded as a compensation block, and the sensing device 300 compensates the compensation blocks one by one during the compensation period T 41 . Similarly, in another embodiment, the 1 st to the N th pixel rows are considered a compensation block, where N is an integer not greater than M. Namely, the sensing device 300 can perform regional compensation on the pixel circuits in the active sensing array 310 . In yet another embodiment, all the pixel circuits in the active sensing array 310 are regarded as a compensation block (i.e., the 1 st to the M th pixel rows are directly considered a compensation block). FIG. 6 is a signal timing diagram for illustrating a sensing device according to yet another exemplary embodiment of the disclosure. As shown in FIG. 6 , during the compensation period T 41 , a first scanning pulse is transmitted to each first scan line at the same time, so that the sensing device 300 can perform a one-time compensation on all the pixel circuits. In other words, those skilled in the art can use the sensing device 300 to perform row-by-row compensation, regional compensation, or one-time compensation on the pixel circuits during the compensation period T 41 according to the actual design requirement.

After the compensation period T 41 , the pixel circuits 311 - 314 enter the sensing period T 42 . During the sensing period T 42 , the switching units 371 and 372 in the switching circuit 370 remain in the first state. Besides, the scanning circuit 360 does not transmit any scanning pulse, so that the first scan lines 321 a and 322 a are switched to the ground level. Thus, the reset transistors M 1 _ 1 -M 4 _ 1 and the sensing transistors M 1 _ 2 -M 4 _ 2 in the pixel circuits 311 - 314 are all turned off. Besides, an incident energy is supplied to the pixel circuits 311 - 314 . Thus, the sensing elements 341 - 344 respectively generate corresponding sensing voltages according to the intensity of the incident energy and store the sensing voltages into the storage capacitors C 31 -C 34 . Namely, during the sensing period T 42 , the sensing transistors (for example, M 1 _ 2 -M 4 _ 2 ) and the reset transistors (for example, M 1 _ 1 -M 4 _ 1 ) in the M pixel rows are all turned off, and the sensing elements (for example, 341 - 344 ) in the M pixel rows respectively sense a incident energy and store the sensing voltages into the storage capacitors (for example, C 31 -C 34 ) in the M pixel rows.

After the sensing period T 42 , the pixel circuits 311 - 314 enter the reading period T 43 . During the reading period T 43 , the switching units 371 and 372 in the switching circuit 370 are switched to the second state, and the scanning circuit 360 sequentially transmits the second scanning pulses PU 45 and PU 46 . Thus, the second scan lines 321 b and 322 b respectively receive the second scanning pulses PU 45 and PU 46 through the switching circuit 370 , and the first scan lines 321 a and 322 a are switched to the ground level. Additionally, the switches SW 31 and SW 32 receive the signal S 35 with high-level therefore are turned on.

Accordingly, the pixel circuits 311 and 312 in the first pixel row receive the second scanning pulse PU 45 from the second scan line 321 b . Then the sensing transistor M 1 _ 2 in the pixel circuit 311 generates a corresponding sensing current in response to the second scanning pulse PU 45 and the voltage stored in the storage capacitor C 31 . Besides, the sensing transistor M 2 _ 2 in the pixel circuit 312 generates a corresponding sensing current in response to the second scanning pulse PU 45 and the voltage stored in the storage capacitor C 32 .

Thereafter, the pixel circuits 313 and 314 in the second pixel row receive the second scanning pulse PU 46 from the second scan line 322 b . Then, the sensing transistor M 3 _ 2 in the pixel circuit 313 generates a corresponding sensing current in response to the second scanning pulse PU 46 and the voltage stored in the storage capacitor C 33 . Besides, the sensing transistor M 4 _ 2 in the pixel circuit 314 generates a corresponding sensing current in response to the second scanning pulse PU 46 and the voltage stored in the storage capacitor C 34 .

In other words, during the reading period T 43 , each pixel row generates the corresponding sensing currents. Namely, during a reading period, the reset transistors (for example, M 1 _ 1 -M 4 _ 1 ) of the M pixel rows are turned off, and the M pixel rows sequentially receive M second scanning pulses (for example, PU 45 and PU 46 ) from the M second scan lines (for example, 321 b and 322 b ), wherein the sensing transistors in the i th pixel row generate a plurality of sensing currents in response to the second scanning pulse from the i th second scan line and the voltages stored in the storage capacitors in the i th pixel row. Besides, the reading circuits 351 - 352 receive the sensing currents from the data lines 331 - 332 through the turned-on switches SW 31 -SW 32 and generate corresponding sensing results according to the sensing currents.

It should be mentioned that because each pixel circuit has been compensated during the compensation period T 41 , the sensing currents generated by each pixel circuit are not affected by the threshold voltages of the transistors. Thereby, when the resolution and sensitivity of the sensing device 300 are increased, the characteristic differences between different elements (for example, different transistors have different threshold voltages due to process variations) do not affect the sensing device 300 even though the electric signals generated by the pixel circuits are weak. In addition, each pixel circuit is composed of two transistors and one storage capacitor. In other words, each pixel circuit has a simple circuit structure so as to facilitate the miniaturization development of the sensing device 300 .

As described above, in a pixel circuit provided by an exemplary embodiment of the disclosure, a storage capacitor charges and discharges to a threshold voltage of a sensing transistor during a compensation period, and the sensing transistor is driven by a scanning pulse and the voltage stored in the storage capacitor during a reading period. Thus, the sensing current generated by the sensing transistor is not affected by the threshold voltage thereof, and accordingly, any sensing error caused by characteristic differences between different elements is avoided. Moreover, the pixel circuit in the disclosure adopts a 2-transistor (2T) structure so as to facilitate the miniaturization development of the active sensing array.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.