Display device and driving method thereof using timing controllers that control image data being applied to adjacent blocks of pixels

This U.S. non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0148740 filed Dec. 18, 2012, in the Korean Intellectual Property Office, the disclosure of which are incorporated by reference herein in its entirety.

The inventive concepts described herein relate to a display device and a driving method thereof, and more particularly, relate to a display device including a plurality of timing controllers and a driving method thereof.

A display panel includes data lines, gate lines, and pixels. The pixels may be alternately connected with adjacent data lines for inversion driving.

High-resolution displays, such as full HD (1920×1080), ultra HD (3840×260), or quad HD (7680×4320) displays, may be achieved by increasing the number of pixels of the display panel.

Further, demand of high-speed frame driving and large-scaled displays is on the rise.

To respond to such demand, multiple timing controllers drive pixels in their respective corresponding blocks.

When, in such structure, the pixels are alternately connected with adjacent data lines, data loss may occur at a boundary between two adjacent blocks.

An exemplary embodiment of the inventive concept provides a display device comprising a display panel, a first timing controller, and a second timing controller.

The display panel includes m data lines extending in a first direction, gate lines extending in a second direction, a first block, a second block adjacent to the first block, with a k-th data line positioned between the first block and the second block (k being a natural number more than 1 and less than m), and a plurality of pixels respectively disposed in regions defined by the m data lines and the gate lines. At least one first pixel disposed along the first direction among the plurality of pixels is alternately connected with adjacent data lines adjacent to each other in the second direction among the m data lines every u pixels (u is a natural number). The first timing controller receives first image data corresponding to the first block, and the second timing controller receives second image data corresponding to the second block. At least one of a part of the first image data or a part of the second image data is transferred to the first timing controller or the second timing controller.

The second timing controller comprises a memory which stores the second image data on a per-line data basis. A transfer signal generating unit is included in the second timing controller. The transfer signal generating unit generates a data transfer signal that is pulsed once whenever at least two line data are stored. A data communication unit is included in the second timing controller. The data communication unit performs data communication with the first timing controller based on the data transfer signal. A data alignment unit is included in the second timing controller. The data alignment unit rearranges the line data and a part of the first image data received from the first timing controller.

An exemplary embodiment of the inventive concept provides a method of driving a display device. The method comprises receiving a part of first image data through data communication between adjacent timing controllers, receiving second image data, and rearranging the second image data and the part of the first image data and outputting rearranged data.

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept;

FIG. 2 is a block diagram illustrating a display panel according to an exemplary embodiment of the inventive concept;

FIG. 3 is an expanded view of a portion AA in FIG. 1 , according to an exemplary embodiment of the inventive concept;

FIG. 4 is a block diagram illustrating first and second timing controllers in FIG. 1 , according to an exemplary embodiment of the inventive concept;

FIG. 5 is a diagram illustrating input and output signals of first and second timing controllers, according to an exemplary embodiment of the inventive concept;

FIG. 6 is an expanded view of a portion AA in FIG. 1 according to an exemplary embodiment of the inventive concept;

FIG. 7 is a diagram illustrating input and output signals of first and second timing controllers according to an exemplary embodiment of the inventive concept; and

FIG. 8 is a flow chart illustrating a method of driving a display device according to an exemplary embodiment of the inventive concept.

Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The inventive concept, however, may be embodied in various different forms, and should not be construed as being limited to the embodiments set forth herein. Like reference numerals may denote like or similar elements throughout the drawings and the specification.

As used herein, the singular forms “a,” “an” and “the” may include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or intervening elements or layers may be present.

FIG. 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1 , a display device 1000 may include a display panel 100 , a distributor 200 , timing controllers 310 to 380 , data drivers 410 to 480 , and a gate driver 500 .

The display panel 100 may display images. The display panel 100 need not be limited to a specific display panel. For example, a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, and an electrowetting display panel may be used as the display panel 100 .

The display panel 100 may include a plurality of data lines D 1 to D 8 m (m is a natural number) and a plurality of gate lines G 1 to G 2 k (k is a natural number). The data lines D 1 to D 8 m receive data voltages. The data lines D 1 to D 8 m may be extended in a first direction DR 1 . The gate lines G 1 to G 2 k receive gate signals. The gate lines G 1 to G 2 k may be extended in a second direction DR 2 . The gate lines G 1 to G 2 k and the data lines D 1 to D 8 m may be isolated from one another, and may be arranged to cross each other.

A plurality of pixel regions may be defined by the gate lines G 1 to G 2 k and the data lines D 1 to D 8 m. A plurality of pixels may be formed in the plurality of pixel regions, respectively.

The display panel 100 may be divided into a plurality of, for example, first to eighth blocks BP 1 to BP 8 . As shown in FIG. 1 , the display panel 100 is divided into first to eighth blocks BP 1 to BP 8 forming a 4×2 matrix. Boundaries of the first to eighth blocks BP 1 to BP 8 may be defined by a (m+1)-th data line Dm+1, a (2m+1)-th data line D 2 m+1, a (3m+1)-th data line D 3 m+1, and a k-th gate line Gk. Each of the first to eighth blocks BP 1 to BP 8 may include (m×k) pixels.

The distributor 200 may distribute image data input from an external device to the first to eighth timing controllers 310 to 380 . The distributor 200 may divide the image data into first to eighth image data DATA 1 to DATA 8 respectively corresponding to the first to eighth blocks BP 1 to BP 8 and may distribute the first to eighth image data DATA 1 to DATA 8 to the first to eighth timing controllers 310 to 380 , respectively. The number of the timing controllers 310 to 380 may be equal to the number of the blocks BP 1 to BP 8 .

The first to eighth timing controllers 310 to 380 may be classified into a master timing controller and slave timing controllers for synchronization therebetween. For example, the first timing controller 310 may operate as a master timing controller, and each of the second to eighth timing controllers 320 to 380 may operate as a slave timing controller. The first timing controller 310 may be connected with the second to eighth timing controllers 320 to 380 and may provide a synchronization signal Sync to the second to eighth timing controllers 320 to 380 .

The first to eighth timing controllers 310 to 380 may generate data control signals CS_D 1 to CS_D 8 in response to corresponding control signals CS. The first to eighth timing controllers 310 to 380 may provide the generate data control signals CS_D 1 to CS_D 8 to the first to eighth data drivers 410 to 480 , respectively.

The first timing controller 310 may generate a gate control signal CS_G based on the control signal CS and may provide the gate control signal CS_G to the gate driver 500 . However, the inventive concept is not limited thereto. For example, the gate control signal CS_G can be provided to the gate driver 500 from the second to eighth timing controllers 320 to 380 or from the distributor 200 .

Each of the data control signals CS_D 1 to CS_D 8 may include a horizontal start signal for starting an operation of a corresponding data driver, a polarity inversion signal for controlling a polarity of corresponding data, and a load signal for determining a point of time when a data voltage is output from a corresponding data driver.

The gate control signal CS_G may include a vertical start signal for starting an operation of the gate driver 500 , and a gate clock signal for determining a point of time when a gate signal is output.

Of the first to eighth timing controllers 310 to 380 , timing controllers adjacent to each other in the second direction DR 2 perform data communication therebetween. For example, the first and second timing controllers 310 and 320 may perform data communication therebetween, the second and third timing controllers 320 and 330 may perform data communication therebetween, and the third and fourth timing controllers 330 and 340 may perform data communication therebetween.

The fifth and sixth timing controllers 350 and 360 may perform data communication therebetween, the sixth and seventh timing controllers 360 and 370 may perform data communication therebetween, and the seventh and eighth timing controllers 370 and 380 may perform data communication therebetween.

The first timing controller 310 may generate first modulation data M_DATA 1 based on the first image data DATA 1 and based on data communication with the second timing controller 320 . Likewise, the second to eighth timing controllers 320 to 380 may generate second to eighth modulation data M_DATA 2 to M_DATA 8 , respectively. The first to eighth timing controllers 310 to 380 may transfer the first to eighth modulation data M_DATA 1 to M_DATA 8 to the first to eighth data drivers 410 to 480 , respectively.

The first to eighth data drivers 410 to 480 may correspond to the first to eighth timing controllers 310 to 380 , respectively. The first to eighth timing controllers 310 to 380 may convert the first to eighth modulation data M_DATA 1 to M_DATA 8 into analog data voltages, respectively. The analog data voltages may be provided to the first to eighth blocks BP 1 to BP 8 from the first to eighth timing controllers 310 to 380 , respectively.

The first data driver 410 may be connected with the data lines D 1 to Dm and may provide a data voltage corresponding to the first modulation data M_DATA 1 to (m×k) pixels of the first block BP 1 . Likewise, the second data driver 420 may be connected with the data lines Dm+1 to D 2 m and may provide a data voltage corresponding to the second modulation data M_DATA 2 to (m×k) pixels of the second block BP 2 . The same or substantially the same manner may apply to the third to eighth data drivers 430 to 480 .

As shown in FIG. 1 , as an example, the first to eighth timing controllers 310 to 380 and the first to eighth data drivers 410 to 480 are connected in a one-to-one correspondence. In other words, the first to eighth timing controllers 310 to 380 are connected to the first to eighth data drivers 410 to 480 , respectively. However, the inventive concept is not limited thereto. For example, each of the first to eighth timing controllers 310 to 380 may be connected with a plurality of data drivers. As shown in FIG. 1 , when viewed at the plan view, the data drivers 410 to 440 are disposed at an upper side of the display panel 100 , and the data drivers 450 to 480 are disposed at a lower side of the display panel 100 . However, the inventive concept is not limited thereto. For example, when the display panel 100 is separated into blocks disposed only in the second direction DR 2 , the data drivers all may be disposed at one of upper and lower sides of the display panel 100 .

The gate driver 500 may generate a gate signal for driving the gate lines G 1 to G 2 k based on the gate control signal CS_G and may provide the gate signal to the gate lines G 1 to G 2 k.

The gate lines G 1 to G 2 k may be divided into upper gate lines G 1 to Gk and lower gate lines Gk+1 to G 2 k. The upper gate lines G 1 to Gk and lower gate lines Gk+1 to G 2 k may sequentially receive gate signals. The gate signals may be substantially simultaneously applied to the upper gate lines G 1 to Gk and lower gate lines Gk+1 to G 2 k, respectively. For example, some gate signals may be substantially simultaneously applied to the first and 2k-th gate lines G 1 and G 2 k, respectively, and other gate signals may be substantially simultaneously applied to the k-th and (k−1)-th gate lines Gk and Gk+1, respectively.

FIG. 1 illustrates one gate driver 500 . However, the inventive concept is not limited thereto. For example, a plurality of gate drivers can be provided. When a plurality of gate drivers are provided, one of the gate drivers may be provided at a left side of the display panel 100 , and another one of the gate drivers may be provided at a right side of the display panel 100 . When two gate drivers are disposed at left and right sides of the display panel 100 , respectively, one of the two gate drivers may apply gate signals to odd-numbered gate lines of the gate lines G 1 to G 2 k, and the other may apply gate signals to even-numbered gate lines of the gate lines G 1 to G 2 k.

FIG. 2 is a block diagram illustrating a display panel according to an exemplary embodiment of the inventive concept.

Referring to FIG. 2 , a display panel 100 may be substantially rectangular in a plan view.

A distributor 200 may be disposed substantially at a center of the back of the display panel.

First to eighth timing controllers 310 to 380 may be formed on the back of the display panel 100 and may be connected to the distributor 200 .

The first to eighth timing controllers 310 to 380 may be disposed along two opposite sides of the display panel 100 which are parallel with each other in a second direction DR 2 . The first to fourth timing controllers 310 to 340 may be spaced apart from each other and may be disposed along an upper side 101 of the display panel 100 . The fifth to eighth timing controllers 350 to 380 may be spaced apart from each other and may be disposed along a lower side 103 of the display panel 100 .

FIG. 3 is an expanded view illustrating a portion AA in FIG. 1 .

The portion AA in FIG. 1 may be a part of the display panel 100 and may include part of a first block BP 1 , part of a second block BP 2 , and a boundary between the part of the first block BP 1 and the part of the second block BP 2 . However, the inventive concept is not limited thereto. For example, the portion AA can include part of the second block BP 2 , part of a third block BP 3 , and a boundary between the part of the second block BP 2 and the part of the third block BP 3 .

As shown in FIG. 3 , seven data lines Dm−2 to Dm+4 and four gate lines Gj to Gj+3 (j is a natural number less than k−3) are provided. 6×4 pixels P 11 to P 46 are illustrated in FIG. 3 , which are provided in regions defined by the data lines Dm−2 to Dm+4 and the gate lines Gj to Gj+3.

A pixel column may be defined by pixels sharing the same column, and a pixel row may be defined by pixels sharing the same row. For example, a first pixel row may include six pixels P 11 to P 16 sharing a first row, and a first pixel column may include four pixels P 11 to P 41 sharing a first column.

The first block BP 1 and the second block BP 2 may be divided by a (m+1)-th data line Dm+1. Thus, the first block BP 1 may include first to third pixel columns including pixels P 11 to P 41 , P 12 to P 42 , and P 13 to P 43 , and the second block BP 2 may include fourth to sixth pixel columns including pixels P 14 to P 44 , P 15 to P 45 , and P 16 to P 46 .

The pixels in a pixel column may be alternately connected with adjacent data lines positioned at both sides thereof.

In the third pixel column including pixels P 13 to P 43 , for example, the first row pixel P 13 may be connected to the m-th data line Dm, the second row pixel P 23 may be connected to the (m+1)-th data line Dm+1, the third row pixel P 33 may be connected to the m-th data line Dm, and the fourth row pixel P 43 may be connected to the (m+1)-th data line Dm+1.

A first timing controller 310 may receive first image data DATA 1 corresponding to the first block BP 1 , and a second timing controller 320 may receive second image data DATA 2 corresponding to the second block BP 2 . In this case, the pixel P 23 in the second row and third column and the pixel P 43 in the fourth row and third column may be included in the first block BP 1 . However, since the pixels P 23 and P 43 are connected with the (m+1)-th data line Dm+1, to the pixels P 23 and P 43 are supplied with a data voltage from the second timing controller 320 via a second data driver 420 .

However, since the second image data DATA 2 does not include image data corresponding to the pixel P 23 in the second row and third column and the pixel P 43 in the fourth row and third column, data loss may arise.

To address the data loss, timing controllers adjacent to each other in the second direction DR 2 may perform data communication therebetween. For example, the first timing controller 310 may provide the second timing controller 320 with image data corresponding to the pixel P 23 in the second row and third column and the pixel P 43 in the fourth row and third column.

FIG. 4 is a block diagram illustrating first and second timing controllers in FIG. 1 . FIG. 5 is a diagram illustrating input and output signals of first and second timing controllers.

Referring to FIGS. 3 to 5 , a first timing controller 310 may include a first memory 311 , a first transfer signal generating unit 312 , a first data communication unit 313 , a first data alignment unit 314 , and a first output control unit 315 .

A second timing controller 320 may include a second memory 321 , a second transfer signal generating unit 322 , a second data communication unit 323 , a second data alignment unit 324 , and a second output control unit 325 .

The first timing controller 310 may receive a vertical synchronization signal Vsync and a first input enable signal DE 1 _I. The second timing controller 320 may receive the vertical synchronization signal Vsync and a second input enable signal DE 2 _I. When the second timing controller 320 operates as a slave controller, the second timing controller 320 may receive one of the first input enable signal DE 1 _I and second input enable signal DE 2 _I from the first timing controller 310 .

The first timing controller 310 may receive first image data DATA 1 on a per-line data basis, and the second timing controller 320 may receive second image data DATA 2 on a per-line data basis. Each of the first and second image data DATA 1 and DATA 2 may include red data R, green data G, and blue data B.

Referring to FIG. 3 , for example, first line data of the first image data DATA 1 may be data R 11 , G 12 , and B 13 respectively corresponding to pixels P 11 , P 12 and P 13 in a first pixel row of a first block BP 1 . First line data of the second image data DATA 2 may be data R 14 , G 15 , and B 16 respectively corresponding to pixels P 14 , P 15 and P 16 in a first pixel row of a second block BP 2 . In FIG. 5 , “Rx”, “Gx”, and “Bx” each may be image data corresponding to Px in FIG. 3 .

The first memory 311 may store the first image data DATA 1 on a per-line data basis in response to the first input enable signal DE 1 _I.

Each of the first and second transfer signal generating units 312 and 322 may generate a data transfer signal SP. The data transfer signal SP may be a signal for determining a timing when data communication between the first timing controller 310 and the second timing controller 320 is performed. The first and second transfer signal generating units 312 and 322 may provide the data transfer signals SP to the first and second data communication units 313 and 323 , respectively.

The data transfer signal SP may be pulsed whenever the first and second timing controllers 310 and 320 receive two line data.

Each of the first and second data communication units 313 and 323 may perform data communication based on the data transfer signal SP. At least one of a part of the first image data DATA 1 and/or a part of the second image data DATA 2 may be transferred between the first data communication unit 313 and the second data communication unit 323 . The first data communication unit 313 may receive a part of the first image data DATA 1 from the first memory 311 , and the second data communication unit 323 may receive a part of the second image data DATA 2 from the second memory 321 .

A part of the first image data DATA 1 and a part of the second image data DATA 2 may include 8 to 12 data bits.

A part of the first image data DATA 1 may be image data corresponding to pixels P 23 and P 43 included in the first block BP 1 and connected with an (m+1)-th data line Dm+1.

The first data communication unit 313 may transfer blue data B 23 in second line data of the first image data DATA 1 to the second data communication unit 323 .

The blue data B 23 may be included in the first image data DATA 1 received by the first timing controller 310 . However, a pixel P 23 in the second row and third column corresponding to the blue data B 23 is connected with the (m+1)-th data line Dm+1 and receives image data from the second timing controller 320 .

Likewise, the first data communication unit 313 may transfer blue data B 43 in fourth line data of the first image data DATA 1 to the second data communication unit 323 .

The second data communication unit 323 may provide the second data alignment unit 324 with a part of the first image data DATA 1 transferred from the first data communication unit 313 .

Since no image data is transferred from the second data communication unit 323 , the first data communication unit 313 does not provide data to the first data alignment unit 314 . However, the inventive concept is not limited thereto. For example, when image data is transferred from the second data communication unit 323 to the first data communication unit 313 , the first data communication unit 313 may provide the transferred image data to the first data alignment unit 314 .

The first data communication unit 313 and the second data communication unit 323 may transfer data through a serial communication scheme or a parallel communication scheme. For example, inter-integrated circuit (I2C), active serial (AS), and serial peripheral interface (SPI) communication schemes may be used.

The first output control unit 315 may generate an output control signal STV and may output the output control signal STV to the first data alignment unit 314 . The second output control unit 325 may generate an output control signal STV and may output the output control signal STV to the second data alignment unit 324 .

The first data alignment unit 314 may generate first modulation data M_DATA 1 by outputting and rearranging the first image data DATA 1 from the first memory 313 on a per-line data basis.

The first modulation data M_DATA 1 may be image data obtained by rearranging the first image data DATA 1 considering a data line connected with each pixel.

The first data alignment unit 314 may rearrange line data once whenever two line data are read. For example, the first data alignment unit 314 may generate the first modulation data M_DATA 1 by rearranging second line data R 21 , G 22 and B 23 without rearranging first line data R 11 , G 12 and G 13 of the first image data DATA 1 .

The first data alignment unit 314 may generate a first output enable signal DE 1 _O based on the output enable signal STV. The first output enable signal DE 1 _O may be a clock signal synchronizer) with a falling time of the output enable signal STV.

The first data alignment unit 314 may output the first output enable signal DE 1 _O and the first modulation data M_DATA 1 synchronized with the first output enable signal DE 1 _O.

The second data alignment unit 324 may read the second image data DATA 2 from the second memory 321 on a per-line data basis and may receive a part of the first image data DATA 1 transferred from the first data communication unit 313 . The second data alignment unit 324 may generate second modulation data DATA 2 by rearranging the second image data DATA 2 and a part of the first image data DATA 1 . The rearranged second image data DATA 2 and rearranged part of the first image data DATA 1 may he applied to their respective corresponding pixels. The second data alignment unit 324 may rearrange line data once whenever two line data are read. For example, the second data alignment unit 324 does not rearrange first line data R 14 , G 15 and B 16 of the second image data DATA 2 . The second data alignment unit 324 may rearrange second line data R 24 , G 25 and B 26 of the second image data DATA 2 and the blue data B 23 transferred from the first data communication unit 313 .

The second data alignment unit 324 may rearrange data and outputs the blue data B 23 to a (m+1)-th data line Dm+1, red data R 24 to a (m+2)-th data line Dm+2, and green data G 25 to a (m+3)-th data line.

Second line data of the second modulation data M_DATA 2 may include the blue, red and green data B 23 , R 24 and G 25 that are part of the first image data DATA 1 .

The second data alignment unit 324 may generate a second output enable signal DE 2 _O based on the output enable signal STV. The second output enable signal DE 2 _O may be a clock signal synchronized with a falling time of the output enable signal STV.

The second data alignment unit 324 may output the second output enable signal DE 2 _O and the second modulation data M_DATA 2 synchronized with the second output enable signal DE 2 _O. In an exemplary embodiment of the inventive concept, the first and second timing controllers 310 and 320 may perform unidirectional data communication therebetween. However, the inventive concept is not limited thereto. For example, the first and second timing controllers 310 and 320 can perform bi-directional data communication therebetween.

FIG. 6 is an expanded view illustrating portion AA in FIG. 1 according to an exemplary embodiment of the inventive concept. FIG. 7 is a diagram illustrating input and output signals of first and second timing controllers according to an exemplary embodiment of the inventive concept.

This embodiment of the inventive concept may be the same or substantially the same as the exemplary embodiment of the inventive concept described above in connection with FIGS. 1 to 5 except for the structure of pixels, data transfer signals, and first and second modulation data.

As illustrated in FIG. 6 , pixels in a pixel column may be alternately connected to adjacent data lines positioned at both sides thereof every u pixels (u is a natural number more than 2). As shown in FIG. 6 , as an example, pixels in each pixel column are alternately connected to adjacent data lines every two pixels.

Referring to FIG. 6 , in a third pixel column including pixels P 13 to P 43 , for example, a first row pixel P 13 and a second row pixel P 23 may be connected to an m-th data line Dm, and a third row pixel P 33 and a fourth row pixel P 43 may be connected to a (m+1)-th data line Dm+1.

Referring to FIGS. 4, 6, and 7 , a data transfer signal SP 1 may have u (u is a natural number more than 2) sequential pulses while 2u line data are continuously received by a first timing controller 310 . The data transfer signal SP 1 may have u pulses continuously while 2u line data are continuously received by a second timing controller 320 .

For example, since pixels are alternately connected adjacent data lines every two pixels, the data transfer signal SP 1 may have two sequential pulses whenever four line data are received by the first timing controller 310 or the second timing controller 320 . The data transfer signal SP 1 does not have a pulse when first line data and second line data are received by the first timing controller 310 or the second timing controller 320 . The data transfer signal SP 1 may have a pulse when third line data is received by the first timing controller 310 or the second timing controller 320 , and the data transfer signal SP 1 may have a pulse when fourth line data is received by the first timing controller 310 or the second timing controller 320 .

A timing when the data transfer signal SP 1 is pulsed may be determined according to a timing when data loss occurs. Thus, when data lines connected with pixels in FIG. 6 are changed, a timing when the data transfer signal SP 1 is pulsed may vary.

A first data communication unit 313 and a second data communication unit 323 may perform data communication therebetween based on the data transfer signal SP 1 . The first data communication unit 313 may transfer blue data B 33 of third line data and blue data B 43 of fourth line data to the second data communication unit 323 .

A first data alignment unit 314 may rearrange line data twice whenever four line data are read. For example, the first data alignment unit 314 does not rearrange first line data R 11 , G 12 , and B 13 and second line data R 21 , G 22 , and B 23 . The first data alignment unit 314 may generate first modulation data M′_DATA 1 by rearranging third line data R 31 , G 32 , and B 33 and fourth line data R 41 , G 42 , and B 43 of the first image data DATA 1 .

A second data alignment unit 324 may rearrange line data twice whenever four line data are read. For example, the second data alignment unit 324 does not rearrange first line data R 14 , G 15 , and B 16 and second line data R 24 , G 25 , and B 26 . The second data alignment unit 324 may rearrange third line data R 34 , G 35 , and B 36 of the second image data DATA 2 and the blue data B 33 transferred from the first data communication unit 313 . The second data alignment unit 324 may rearrange fourth line data R 44 , G 45 , and B 46 of the second image data DATA 2 and the blue data B 43 transferred from the first data communication unit 313 .

FIG. 8 is a flow chart illustrating a method of driving a display device according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 1 and 8 , in operation S 1 , a second timing controller 320 may receive second image data DATA 2 . The second image data DATA 2 may be image data corresponding to a second block BP 2 . Likewise, a first timing controller 310 may receive first image data DATA 1 . The first image data DATA 1 may be image data corresponding to a first block BP 1 .

Each of the first and second blocks BP 1 and BP 2 may include pixels which are alternately connected to adjacent data lines every pixel.

In operation S 2 , a part of the first image data DATA 1 may be transmitted through data communication between timing controllers. For example, the second timing controller 320 may receive a part of the first image data through data communication between the first and second timing controllers 310 and 320 . A part of the first image data DATA 1 may be image data corresponding to pixels connected with a (m+1)-th data line.

In operation S 3 , the second timing controller 320 may rearrange the second image data and a part of the first image data DATA 1 and may output rearranged data.

The first and second timing controllers 310 and 320 may perform unidirectional or bi-directional data communication therebetween. The first and second timing controllers 310 and 320 may perform serial or parallel communication therebetween.

A method of driving a display device according to an exemplary embodiment of the inventive concept may drive a display device without data loss even where pixels are alternately disposed, by performing data communication between adjacent timing controllers.

While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the inventive concept as Defined by the following claims.